Texas Instruments AFE5805EVM User manual

User's Guide
SLOU222C–March 2008–Revised March 2015
AFE5805EVM
The AFE5805EVM is an evaluation tool designed for the ultrasound analog front-end (AFE) device
AFE5805. In order to deserialize the outputs of the AFE5805, an ADSDeSer-50EVM or TSW1400EVM is
needed during the evaluation.
Contents
1 Introduction ................................................................................................................... 2
1.1 AFE5805EVM Kit Contents........................................................................................ 2
1.2 Features.............................................................................................................. 2
1.3 Power Supplies ..................................................................................................... 3
1.4 Indicators............................................................................................................. 3
2 Board Configuration ......................................................................................................... 4
2.1 I/O and Power Connectors ........................................................................................ 4
2.2 Jumpers and Setup................................................................................................. 5
2.3 Test Points........................................................................................................... 7
3 Board Operation ............................................................................................................. 8
3.1 Software Installation and Operation.............................................................................. 8
3.2 Hardware Setup ................................................................................................... 10
3.3 Clock Selection .................................................................................................... 11
3.4 Data Analysis ...................................................................................................... 12
4 Schematics and Layout.................................................................................................... 12
4.1 Schematics......................................................................................................... 12
4.2 PCB Layout ........................................................................................................ 12
4.3 Bill of Materials .................................................................................................... 21
5 Typical Performance....................................................................................................... 24
Appendix A TSW1400 for Evaluating AFE5805 ............................................................................. 26
Appendix B High Speed Data Converter Pro (HSDCPro) GUI Installation .............................................. 36
List of Figures
1 AFE5805EVM LED Locations.............................................................................................. 3
2 AFE5805EVM I/O Connectors and Locations ........................................................................... 4
3 Locations of Jumpers, JTAG, and Switches on the AFE5805EVM ................................................... 5
4 Default Setup for Jumpers.................................................................................................. 6
5 AFE5805EVM USB SPI Interface for TGC Mode ....................................................................... 8
6 AFE5805EVM USB SPI Interface for CW Mode......................................................................... 9
7 AFE5805EVM USB SPI Interface for ADC Setup...................................................................... 10
8 Typical AFE5805 Bench Setup........................................................................................... 11
9 Clock Selection Jumper Configurations ................................................................................. 11
10 Top Layer, Signal........................................................................................................... 13
11 Inner Layer 1, Ground ..................................................................................................... 14
12 Inner Layer 2, Signal....................................................................................................... 15
13 Inner Layer 3, Power....................................................................................................... 16
14 Inner Layer 4, Ground ..................................................................................................... 17
15 Bottom Layer, Signal....................................................................................................... 18
SPI is a trademark of Motorola, Inc.
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16 Top Silk Screen Layer..................................................................................................... 19
17 Bottom Silk Screen Layer ................................................................................................. 20
18 Typical Performances of AFE5805....................................................................................... 24
19 Typical Performance of AFE5805 With (a) HP8644 and (b) Onboard 40-MHz Clock ............................ 25
20 Connection between TSW1400EVM and AFE5805................................................................... 26
21 Connection of the Instruments............................................................................................ 27
22 AFE5805 EVM GUI ........................................................................................................ 28
23 User Interface: Step-by-Step setup...................................................................................... 29
24 User Interface: Frequency Load Value to Signal Generator.......................................................... 30
25 Typical Performance of AFE5805........................................................................................ 31
26 Single Tone FFT Test Data Plot in EXCELL ........................................................................... 32
27 Single Tone FFT Test Data Saved as filename.jpeg.................................................................. 33
28 Typical Performance of AFE5805 in Non-Coherent Case............................................................ 34
29 User Interface: Time Domain Format.................................................................................... 35
30 HSDCPro Install (Begin)................................................................................................... 36
31 HSDCPro Install (Install Directory)....................................................................................... 37
32 HSDCPro Install (TI License Agreement)............................................................................... 38
33 HSDCPro Install (NI License Agreement)............................................................................... 39
34 HSDCPro Install (Start Installation)...................................................................................... 40
35 HSDCPro Install (Installation Progress)................................................................................. 41
36 HSDCPro Install (Installation Complete) ................................................................................ 42
37 HSDCPro Install (h)........................................................................................................ 43
38 HSDCPro Install............................................................................................................ 43
List of Tables
1 AFE5805EVM Default Settings When Powered On................................................................... 10
2 Channel-to-Channel Matching Between the AFE5805EVM and ADSDeSER-50EVM............................ 11
3 Bill of Materials ............................................................................................................. 21
1 Introduction
The AFE5805 includes an 8-channel, voltage-controlled amplifier (VCA) and an 8-channel, 50-MSPS
analog-to-digital converter (ADC). The outputs of the ADC are 8-channel LVDS outputs, which can be
deserialized by the ADSDeSer-50EVM or TSW1400EVM. The AFE5805 evaluation module (EVM)
provides an easy way to examine the performance and functionalities of AFE5805.
1.1 AFE5805EVM Kit Contents
The AFE5805EVM kit contains the following:
• AFE5805 EVM board
• USB cable
1.2 Features
• Characterizes the AFE5805
• Supports CW functionalities test
• Provides 8-channel low-voltage differential signal (LVDS) outputs from the ADC
• Compatible with the standard TI LVDS deserializer ADSDeSer-50EVM or TSW1400EVM
• Communicates with a personal computer (PC) through a USB interface
• RS-232 interface also can be configured in case users wish to control the AFE5805 with a
microcontroller. MSP430 programming is required.
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LED 4
LED 1, 2
LED 3
www.ti.com Introduction
• Includes multiple power management solutions for the AFE5805 and other devices.
• Onboard Vcntl generator (0 V - 1.2 V).
1.3 Power Supplies
The AFE5805EVM requires only ±5-V power supplies for operation.
1.4 Indicators
The AFE5805EVM has four LEDs onboard as shown in Figure 1. The states of these LEDs demonstrate
the normal operation of the AFE5805EVM.
• LED1, LED2: +3.3-VA and +3.3-VD power supply indicators. They show the normal operation of 3.3-V
power regulators.
• LED 3: MCU operation indicator. Flashing state can indicate the normal operation of the MSP430 when
the MSP430 is appropriately programmed.
• LED 4: 1.8-V power indicators
Figure 1. AFE5805EVM LED Locations
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Ext
CLK In
Low Jitter
CLK In
Vctrl In
+/- 5V PWR
CW Out
LVDS
Outputs
R12
USB
Board Configuration www.ti.com
2 Board Configuration
This section describes in detail the locations and functionalities of inputs, outputs, jumpers, and test points
of the AFE5805EVM.
2.1 I/O and Power Connectors
Pin A1 of the AFE5805 is marked by a white dot on its package as well as a white dot on the board. The
positions and functions of the AFE5805EVM connectors are discussed in this section.
Figure 2. AFE5805EVM I/O Connectors and Locations
• Analog Inputs Ch1-Ch8 (J1-J3, J5-J7, J9, J10): Single-ended analog signal inputs with 50-Ω
termination and AC-coupling
• CW Output (J4): CW output after I/V translator
• Vcntl Input (J8 optional): VCA gain control voltage of AFE5805, 0 V to 1.2 V, when this SMA connector
is used, shunt P3 must be removed. .
• Low-Jitter CLK Source Input (J11): This input accepts clocks with low-jitter noise, such as HP8644
output. 20- to 50-MHz, 50% duty-cycle clock with 1- to 2-Vrms amplitude can be used. When J11 is
used, ensure that shunts P18, P23, and P22 are removed.
• External CLK Input (J13): ADC Clock input, such as FPGA outputs. However, the AFE5805 does not
achieve satisfactory performances due to the high-jitter noise of the clock.
• ±5-V PWR connector (P2): Power supply input
• Regulated power supply outputs (P1, P4, and P24): 3.3-VA, 3.3-VD, 2.5-VA, 1.8-VD outputs.
Connectors need to be installed.
• RS-232 Input (P17): PC serial port interface for setting AFE5805
• USB input (P25): USB interface to control the AFE5805 (default)
• LVDS Outputs Ch1-Ch8 (P26): Differential LVDS data outputs
• R12 is used to adjust the onboard Vcntl from 0 V to 1.2 V. P3 must be shorted when onboard Vcntl is
used.
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P7
P8
P16
P5
P15 P14 P13
P12
P11
SW1 SW2
P20 P19
S1
P22
P18
P9
P6
P10
P23
P3
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2.2 Jumpers and Setup
In the following detailed description, the board has been set to default mode (see Figure 3).
Figure 3. Locations of Jumpers, JTAG, and Switches on the AFE5805EVM
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Figure 4. Default Setup for Jumpers
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• P5: Power-down pin for the VCA section of the AFE5805. Grounded (default mode) or High (+3.3 VD)
for power-down mode.
• P6, P10: AFE5805 ADC clock input selection: Transformer-based differential clock, single-ended
LVCMOS clock, or future clock option (needs U4 for support). The default mode uses the transformer-
based differential clock.
• P7: MSP430 microcontroller JTAG interface
• P8: MAX3221 (RS-232) power-off jumper. When the jumper is removed, MAX3221 is completely
powered off. In the default mode, the jumper is uninstalled because the USB interface is used.
• P9: SPI™ interface for U4.
• P11: TI internal use. Default is floating.
• P12: Power-down pin for ADS. Active High (+3.3 VD). Floating for default mode.
• P13: External ADS reference voltage inputs. Floating in the internal reference mode.
• P14: EN_SM: In the default mode, P14 connects to +3.3 VD, and the state machine is enabled. The
AFE5805 is operated using only one SPI port (ADS SPI port).
• P15: RST pin; connects to H4 in the default mode through 0-Ωresistors.
• P16: Debug port for monitoring VCA and ADS SPI signals.
• P19: TI internal use. Connects to 3.3 VD.
• P20: INT/EXT reference mode selection. +3.3 VD for the internal reference mode (default); GND for
the external reference mode.
• P22: Uses onboard 40-MHz clock or external clock through J13. The default mode uses the onboard
clock
• P23: Power-on onboard 40-MHz clock generator. Default is on.
• P18: Because U4 is uninstalled, this jumper must be set as Figure 4 shows
• S1: MSP430 reset button
• SW1, SW2: CW outputs summation switch. Individual CW output current can be summed through the
I/V translator U1 when its corresponding switch is set to ON.
2.3 Test Points
Multiple test points are provided on the EVM. Detail descriptions follow. Under normal operation mode, it
is unnecessary to measure voltages at most of these test points.
• TP1: GND
• TP2: GND
• TP3: VCM
• TP4: Vcntl test point
• TP5: GND
• TP6: GND
• TP7: Test point, TI internal only
• TP8: +5 V
• TP9: CM
• TP10:GND
• TP11: -5 V
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3 Board Operation
This section describes how to operate the AFE5805EVM for evaluation purposes. Both software and
hardware installation and operation are discussed.
3.1 Software Installation and Operation
The AFE5805EVM USB SPI Ver1 software and AFE5805EVM driver can be dowloaded from the TI
website on the AFE5805 product folder under Tools & software. Run the AFE5805EVM driver install.exe
and the setup.exe to install the driver and software, respectively. The personal computer (PC) should
recognize the EVM after software installation.
To launch the software after successful installation, click:
Start Menu →All Programs →Texas Instruments →AFE5805EVM USB SPI →AFE5805EVM USB SPI
Three different modes are shown in Figure 5,Figure 6, and Figure 7.
The software updates the AFE5805 registers as soon as users change any current setup (i.e., the
program sends out new register values due to any value change). It is recommended that users change at
least one register value before measurement. Therefore, the register values in a device can be
synchronized to the displayed values on the software interface.
In most cases, users only need to change the VCA setup. The ADC setup can remain the same as the IC
is powered up.
Figure 5. AFE5805EVM USB SPI Interface for TGC Mode
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Figure 6. AFE5805EVM USB SPI Interface for CW Mode
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Figure 7. AFE5805EVM USB SPI Interface for ADC Setup
3.2 Hardware Setup
When the AFE5805EVM is powered on in the default mode, the AFE5805 is set as described in Table 1.
Table 1. AFE5805EVM Default Settings When Powered On
VCA ADS
TGC mode Differential clock
PGA = 20 dB Digital Gain = 0
Clamp=Enable Other parameters are as stated in data sheet
Filter = 15 MHz
Initial measurements can be made under these default settings. See the AFE5805 data sheet
(SBOS5805) for additional settings.
As previously mentioned, the deserializer ADSDeSER-50EVM or TSW1400EVM is required. See details in
the ADSDeSER-50EVM user's guide (SBAU091) or TSW1400EVM user's guide (SLWU087B). An
example bench setup is shown in Figure 8. Band-pass filters are required for signal source in order to
ensure the correct SNR measurements of the AFE5805.
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(a) Transformer Default (b) Single-Ended Clock (c) Future CLK Input Option Based on U4
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AFE58XX Evaluation Setup Best Practice
(1) Select the lowest phase noise models
(2) An additional Bandpass filter after the signal source is needed. This serves to filter the harmonic distortion of
the signal generator and band-limit the noise. Without using filter; the SNR and SFDR will be that of the
signal geverator, not that of AFE58XX.
(3) For a coherent AFE58XX evaluation, connect the 10M reference on the back of the clock and to the 10M
reference input on the back of the analog input source. For some equipment, one must also use the on-
screen menus to select "ext Reference"
(4) The Logic Analyzer is used when a large amount of data (> 64K samples) is needed.
(5) If ADSDeSER EVM is chosen then the Logic Analyzer is a must, ADSDeSER EVM does not provide the
function to transfer the data back to PC directly.
Figure 8. Typical AFE5805 Bench Setup
The channel order of the AFE5805 outputs is not the same as that of the ADS527x outputs.
Consequently, the channel number on the ADSDeSER-50EVM or AFE5805EVM can be misleading.
Table 2 provides channel-to-channel sequence matching between the ADSDeSER-50EVM and the
AFE5805EVM.
Table 2. Channel-to-Channel Matching Between the AFE5805EVM and ADSDeSER-50EVM
AFE5805 FCLK CH4 CH3 CH2 CH1 CH5 CH6 CH7 CH8 LCLK
ADSDESER FCLK CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 LCLK
For example, when an analog signal is present on CH1 of the AFE5805EVM, the corresponding 12-bit
digital output can be seen on CH4 of the ADSDeSER-50EVM.
3.3 Clock Selection
The AFE5805 can be clocked through a transformer-based differential clock, single-ended clock, or future
clock input options provided by U4 as Figure 9 shows.
Figure 9. Clock Selection Jumper Configurations
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The clock source of the EVM can be the onboard 40-MHz clock, HP8644 low-jitter clock source, or
external clock source. The best performance of this EVM is achieved when the low-jitter clock source
HP8644 is used. P22, P23, and P18 should be removed in order to disable the onboard clock.
When HP8644 or similar clock sources are unavailable, the onboard 40-MHz clock is the desirable source.
The jumpers P22, P23, and P18 should be configured as shown in Figure 4 (i.e., the default setup for
AFE5805EVM). In this mode, the transformer-based differential clock is used.
3.4 Data Analysis
Based on the data file acquired by a logic analyzer, the performance of AFE5805 can be evaluated.
Appendix A provides a solution (TI TSW1400EVM) to analyze the data file using the PC. Appendix B
provides a step by step process on how to download the HSDCPro software. Coherent sampling is
recommended, but is not mandatory. Due to the frequency accuracy requirement of coherence sampling,
two HP8644s are required for generating an ADC clock and analog signal. For most users, this may be
infeasible. Data analysis based on windowing is a more suitable approach.
4 Schematics and Layout
This section provides the schematics, the AFE5805EVM board layout, and the bill of materials.
4.1 Schematics
The schematics appear at the end of the document.
4.2 PCB Layout
The AFE5805EVM uses a six-layer printed-circuit board. The following figures show each layer.
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Figure 10. Top Layer, Signal
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Figure 11. Inner Layer 1, Ground
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Figure 12. Inner Layer 2, Signal
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Figure 13. Inner Layer 3, Power
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Figure 14. Inner Layer 4, Ground
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Figure 15. Bottom Layer, Signal
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Figure 16. Top Silk Screen Layer
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Figure 17. Bottom Silk Screen Layer
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