Texas Instruments TSW1200EVM User manual

User's GuideSLAU212A – April 2007 – Revised August 2008
TSW1200EVM: High-Speed LVDS Deserializer andAnalysis System
Contents1 Introduction ................................................................................................................... 32 Functionality .................................................................................................................. 33 Hardware Configuration ..................................................................................................... 54 Software Installation ....................................................................................................... 125 User Interface ............................................................................................................... 166 MATLAB™ Interface ....................................................................................................... 227 Schematics and Bill of Materials ......................................................................................... 238 Circuit Board Layout and Layer Stackup ................................................................................ 30
List of Figures
1 Position of Power Connections ............................................................................................ 52 Position of Switches and Jumpers ......................................................................................... 73 EEPROM Configuration Options ........................................................................................... 84 Position of LEDs ............................................................................................................. 95 Position of Input, Output, and USB Connections ...................................................................... 116 Pinout of Header Posts for Parallel Output Data ....................................................................... 127 TSW1200 User Interface Installation .................................................................................... 138 Hardware Device Manager ................................................................................................ 149 Found New Hardware Windows .......................................................................................... 1510 User Interface Initial Setup Screen ...................................................................................... 1611 User Interface Single FFT format ........................................................................................ 2012 User Interface Time Domain Format..................................................................................... 2213 Schematic Diagram Page 1 ............................................................................................... 2314 Schematic Diagram Page 2 ............................................................................................... 2415 Schematic Diagram Page 3 ............................................................................................... 2516 Schematic Diagram Page 4 ............................................................................................... 2617 Schematic Diagram Page 5 ............................................................................................... 2718 TSW1200C Layout Top Layer ............................................................................................ 3019 TSW1200C Layout Layer Two ........................................................................................... 3120 TSW1200C Layout Power Plane ......................................................................................... 3221 TSW1200C Layout Ground Plane ....................................................................................... 3322 TSW1200C Layout Layer 5 ............................................................................................... 3423 TSW1200C Layer 6 ........................................................................................................ 3524 TSW1200C Bottom Layer ................................................................................................. 3625 Circuit Board Stackup ...................................................................................................... 37
List of Tables
1 Bill of Materials ............................................................................................................. 28
SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System 1Submit Documentation Feedback

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Windows is a trademark of Microsoft Corporation.LabVIEW is a trademark of National Instruments Corporation.MATLAB is a trademark of The MathWorks, Inc..Xilinx is a trademark of Xilinx, Inc..
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1 Introduction
2 Functionality
www.ti.com Introduction
The Texas Instruments TSW1200 High-Speed LVDS Deserializer and Analysis System provides acomprehensive set of hardware and user interface software to effectively evaluate the performance of awide range of Texas Instruments (TI) high-speed, analog- to-digital converters (ADC), particularly thosehigh-speed ADCs that employ an low-voltage differential signal (LVDS) format for the data converter’soutput data. With a high-quality, low-jitter clock and a high-quality input frequency provided to theevaluation module, the TSW1200 system can be used to demonstrate data sheet performancespecifications.
The TSW1200 hardware has a high-speed connector that plugs into an evaluation module (EVM) for theADC. Firmware for an FPGA on the TSW1200EVM has an interface to various LVDS data formats andFIFO memory sufficient to capture as much as 64K samples of data. A USB connection transfers thecaptured data to a personal computer for post-processing. The user Interface software controls theTSW1200 hardware and displays the FFT and important statistics related to the performance of the ADC.
Many TI high-speed ADCs have LVDS outputs for the digitized data. These ADCs are generally availableon an EVM that connects directly to the TSW1200EVM. The common connector between the ADC EVMand the TSW1200EVM is a Samtec high-speed connector suitable for differential pairs of pins separatedby ground. A common pinout for the connector across a family of EVMs has been established. At present,the interface between the ADC EVM and the TSW1200EVM has defined connections for 14 pairs of LVDSplus two clock lines. The connector pinout has an additional 14 LVDS pairs for future product support. Inmost cases, if a TI ADC supports LVDS outputs, then the TSW1200 system can be used to capture datafrom the ADC. If the ADC supports a CMOS single-ended format, then the TSW1100 system is intendedto interface to it.
The data format for the LVDS data bus can be in one of many formats, all supported by the TSW1200.For single-channel, high-speed ADCs, the data format is commonly parallel dual-data rate with one clockline. Dual-data rate means that both the rising and falling edges of the clock strobe data into theTSW1200. For multichannel ADCs, the data is commonly presented in a serialized format, whereindividual bits of the output data are presented on an LVDS line one bit at a time, at a higher data ratethan the sample rate of the ADC.
The firmware in the FPGA on the TSW1200 is designed to accommodate both parallel DDR formats andserial LVDS formats, although not at the same time. The EEPROM on the TSW1200EVM is large enoughto hold two distinct program files for the FPGA. One program bit file supports the parallel DDR format andthe other bit file supports serial LVDS formats. The TSW1200 can be set to support the desired dataformat by simply setting two jumpers and pressing the PROGRAM button.
The parallel DDR FPGA program supports several types of data formats. One common format presentsodd-numbered data bits on the bus on one clock edge and even-numbered data bits on the bus on theother clock edge. This format is commonly used for ADCs with sampling rates up to 250 MHz. For thisbit-wise DDR format, the parallel data bus uses half as many LVDS pairs as there are bits in the sample.For example, a 16-bit ADC uses eight LVDS pairs for data plus an LVDS clock pair for bit-wise DDR. Forhigher sample rates up to 500 MHz, a sample-wise DDR format is often used. For sample-wise DDR, thedata bus width has as many LVDS pairs as the bit resolution of the ADC. On one clock edge, a datasample from the ADC is registered; on the next clock edge, the next data sample from the ADC isregistered.
The serial FPGA program also supports several data formats. For one-wire serial formats, the data isserialized onto a single LVDS pair at a rate that is 12 times the sample rate for an ADC with a 12-bitresolution. A one-wire serialization format also is used for 14-bit and 16-bit data at data rates 14 or 16times the sample rate, respectively. For serial data formats, a DDR LVDS bit clock is used to strobe theserial data bits and to deserialize the data. An additional clock pair provided at the sample rate of the ADCidentifies the sample-word boundaries in the serial data. For multichannel ADCs, a single-bit clock and asingle sample-rate clock (frame clock) is used for all of the LVDS data channels. The other common serialdata format is two-wire serialization. Two-wire serialization is similar to one-wire serialization except that adata channel uses two LVDS pairs to carry the serialized data at a rate that is half of what it is for one-wireserialization. Two-wire serialization commonly is used for sample rates up to 125 MHz, whereas one-wireserialization generally is used for sample rates up to 65 MHz.
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Functionality www.ti.com
The FPGA firmware for the TSW1200 generally consists of two major functions: the LVDS ADC interfaceand the FIFO capture. The LVDS ADC interface supports either the various parallel DDR interfaces or thevarious serial interfaces as previously described. The LVDS ADC interface code in the FPGA reformatsthe data into a standard single-ended parallel data word with sample clock. This parallel sample word plusclock is output continuously to header posts on the TSW1200 for capture by a logic analyzer. The paralleldata word with sample clock also is presented to the FIFO capture logic. Note that for parallel DDR dataformats, the header output posts are not enabled by default, as the data rate (up to a 500-MHz samplerate) is often too fast to be feasible for a single-ended CMOS output.
The TSW1200 FPGA has enough FIFO buffer to capture as much as a 65536-sample record length fromthe continuous sample data stream coming from the LVDS ADC interface. The TSW1200 FPGA designincludes a UART function that can transfer data to and from a USB interface device on the TSW1200board. The USB interface device on the TSW1200EVM connects to a personal computer (PC) runningWindows™ over a standard USB cable. The operation of the FIFO capture logic is controlled by writesfrom the PC USB port to a register map defined within the FPGA. The user interface software on the PCselects by register operations such things as record length of data to capture, which channel of an ADC tocapture from, and then the user interface software downloads the captured data from the TSW1200 forprocessing in the form of an FFT or time-domain display.
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3 Hardware Configuration
3.1 Power Connections
TSW1200
Ground
J7
J14 J15
Selects 5 V
Output for J15
(Default)
Selects J7 for
6 V Input
(Default)
Selects J5
for 6 V Input
J22
JP8
6 V I/O
+6 V
Input
www.ti.com Hardware Configuration
In this section, the various portions of the TSW1200EVM hardware are described.
The TSW1200EVM hardware is designed to operate from a single-supply voltage of greater than 6 Vdc.For convenience, two options can supply power to the TSW1200EVM. A bench power supply can supplypower to banana jack connections on the TSW1200EVM, or a laptop-style power module that is includedwith the TSW1200 hardware can supply power. Figure 1 shows the relative position of the powerconnections on the TSW1200EVM (revision B or C of the hardware).
CAUTION
TI recommends that the black banana jack J14 be connected to a benchground even if the 6-V external power brick is connected to J7. Intermittent lossof the USB connection can sometimes be observed without a good ground fromthe TSW1200EVM to the bench ground reference.
Figure 1. Position of Power Connections
Care must be taken in selection of the input power supply. One jumper selects whether the 6-V inputpower comes from the banana jack, or whether it comes from the external power module. Another jumperselects whether to connect the onboard regulated 5 V to the red banana jack for output. If the red bananajack is used to input 6 V from a bench power supply, the onboard regulated 5 V must not be connected tothe red banana jack for output at the same time. Doing so causes the onboard 5-V regulator to fail overtime.
SLAU212A – April 2007 – Revised August 2008 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System 5Submit Documentation Feedback

3.2 Switches and Jumpers
3.2.1 Pushbuttons
3.2.2 Jumpers
Hardware Configuration www.ti.com
Four pushbutton switches are mounted on the TSW1200EVM. Two pushbutton switches currently havedefined functions; two of the switches are reserved for future use.
The PROGRAM pushbutton (SW3) causes the FPGA to reload its bit file from the FPGA EEPROM on theTSW1200EVM. The EEPROM currently is large enough to hold two FPGA bit files. When the FPGA loadsa bit file, it loads the bit file indicated by the position of the jumpers J11 and J10. When power is firstapplied to the TSW1200EVM, the FPGA also loads its bit file from the EEPROM as determined by thejumpers J11 and J10. Therefore, pressing the PROGRAM pushbutton has the same effect aspower-cycling the FPGA. All register settings in the FPGA and any data held in the FPGA are lost onloading the bit file, and the FPGA then is in its initial default configuration.
The RESET (SW4) pushbutton causes the FPGA to clear the FIFO storage, but does not clear any of theregister settings in the FPGA. Any configuration of the FPGA done through register operations such assetting the UART baud rate will persist after pushing the RESET pushbutton. FPGA register settings onlyare cleared by pressing the PROGRAM pushbutton. For this reason, the RESET pushbutton has limitedutility in this revision of the TSW1200EVM; this pushbutton may have more utility defined for it in futurerevisions of the FPGA firmware.
The PROM RESET (SW2) is reserved for future use, as is pushbutton SW5.
Jumpers J10 and J11 select the bit file to be programmed into the FPGA as indicated in Figure 2 . TheEEPROM is currently large enough to contain two complete programming files for the FPGA, withprovision to later install a larger EEPROM with the capability to store four complete programming bit filesfor the FPGA.
Bit file CFG1 (jumper J10 set to LO and jumper J11 set to HI) is defined for use with ADC EVMs thatemploy a parallel LVDS DDR (dual-data rate) format. Bit file CFG2 is defined for use with ADC EVMs thatemploy a serialized data format, whether a one-wire serial format or a two-wire serial format. See Figure3.
Simply moving the position of the jumpers J10 and J11 has no immediate effect. The FPGA does not loadits programming bit file except on initial power up or until the PROGRAM pushbutton is pressed. Tochange the operation of the TSW1200EVM for use with a parallel DDR format or with a serial LVDSformat, the jumpers J10 and J11 must be set to the desired position, and then the board must bepower-cycled or have the PROGRAM button pushed.
Jumper JP8 selects whether the power supply to the TSW1200EVM is to be supplied by the external 6-Vpower module through power jack J7 or by an external 6-V bench power supply through the red bananajack J15.
A low drop-out linear power regulator on the TSW1200EVM generates a clean, low-noise 5-V supply fromthe 6-V power that is input to the TSW1200EVM. The jumper J22 can be used to connect this onboardregulated 5 V to the red banana jack J15 as an output. This option is a convenience for use with ADCEVMs that require a single 5-V supply input. In this way, the TSW1200EVM and ADC EVM combinationcan be powered completely from the laptop-style 6-V external power supply.
CAUTION
It is possible to select the red banana jack J15 as an input to be connected to a6-V bench supply and at the same time install jumper J22 to connect theregulated 5 V to the red banana jack as an output. This, however, over timecauses the 5-V regulator on the TSW1200 to fail.
Jumper J16 is used at the factory to program the small EEPROM for the USB port. The default position forthis jumper is to be installed, and in normal operation, J16 is left installed.
6TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008Submit Documentation Feedback

TSW1200
+6 V
Input
Ground
PROGRAM
RESET
PROM RESET
SW2 SW3
SW5
J17
J10
J11
J16
JP8
J22
open
USB EEPROM
(Default Shorted)
JTAG TDI =>TDO
Selects FPGA bit file
from EEPROM
(Default CFG1 for
Parallel DDR format)
(Default Shorted)
6 V I/O
J1
J12
SW4
www.ti.com Hardware Configuration
Jumper J17 can be used to disable the 1.2-V power regulator for the FPGA core logic. The defaultposition for this jumper is to be left uninstalled or open, and in normal operation, this jumper is leftuninstalled.
Jumpers J1 and J12 form part of a JTAG chain through the FPGA and the FPGA EEPROM. A chain ofJTAG devices form a loop, with the TDO from one JTAG device connected to the TDI of the next JTAGdevice. The normal setting of the JTAG jumpers is to connect the TDI of the JTAG connector to the TDIpin of the FPGA EEPROM through jumper J12 pins 2-4. Then, the TDO of the FPGA EEPROM connectsto the TDI of the FPGA through jumper J12 pins 1-3 and jumper J1 pins 2-4. The TDO of the FPGAconnects to the JTAG connector pin TDO through jumper J1 pins 1-2. If it desired to remove either thePFGA or the FPGA EEPROM from the JTAG chain, the jumpers J1 or J12 can be turned 90 degrees toconnect pins 1-2 and 3-4. See the TSW1200EVM schematics and layout sections for illustration of thisoption.
Figure 2. Position of Switches and Jumpers
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PRGM LOAD
CFG3
CFG4
CFG2
CFG1
J10 J11
LO LO
LO
LO
HI
HI
HI
HI
3.3 LEDs
Hardware Configuration www.ti.com
Figure 3. EEPROM Configuration Options
Six LEDs are on the TSW1200EVM to indicate the presence of power and the state of the FPGA. SeeFigure 4. LED D16 illuminates to indicate the presence of a 6-V power supply to the board. On power up,the FPGA loads its programming bit file from the FPGA EEPROM. Once the programming bit file hascompleted loading, the LED D7 illuminates to indicate that the FPGA is operational.
Once the FPGA has loaded its bit file, it internally resets the clock circuitry that locks to a 200-MHz clocksignal from a 200-MHz oscillator on the TSW1200 board. Once the internal reset is complete, LED D1(labeled ADC on the TSW1200 silkscreen) illuminates to indicate that the TSW1200EVM is ready to usewith an ADC EVM.
LED D4 flashes when the onboard 200-MHz oscillator is running. The 200-MHz oscillator clock ismultiplied up to 250 MHz within the FPGA. The pattern of the flashing is of the formflash-flash-pause-pause. That is, the LED illuminates for a time, then turns off for the same time, thenilluminates for the same time, then turns off 5 times. The internal time is derived from a division of the250-MHz reference clock derived from the onboard oscillator.
LED D2 (labeled DCM on the TSW1200 silkscreen, which is an abbreviation for the digital clock managerblock of logic in the FPGA) flashes when an LVDS clock from the ADC is present. The DCM clock flashesin the same flash-flash-pause-pause pattern, using the same clock division parameters as were used forthe 250-MHz reference clock LED. In this manner, the DCM LED can be used to see that the clock fromthe ADC is present and approximately the right frequency by comparing it to the 250-MHz LED. That is, ifthe sample rate clock to the ADC is 250 MHz, then the DCM LED and the 250-MHz LED flash at the samerate. If the sample clock to the ADC is 125 MHz, then the DCM LED flashes at half the rate of LED D4. Ifthe DCM LED is not flashing at all, then no clock is detected from the ADC. Common reasons for an ADCclock not to be detected are that the EVM is not powered on, or that the clock from the ADC is a CMOSclock instead of an LVDS clock due to an improper jumper setting.
LED D3 (labeled USB on the TSW1200EVM silkscreen) illuminates whenever the TSW1200 user interfacesoftware is accessing the FPGA by way of the USB connection. For longer FFT record lengths and lowerUART baud rates, the USB LED illuminates longer than for shorter FFT record lengths or higher UARTbaud rates.
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TSW1200
6 V InputGround
D 7
ADC D1
D16
D4
D3
D2
DCM
USB
Lit when 6V
present
Lit after FPGA
reset completed
Flashes when clock
from ADC present
Lit during
USB access
Flashes while
200 MHz osc present
Lit when FPGA
finishes loading bit file
6 V I/O
3.4 Input Connections
3.4.1 Samtec LVDS Connector
www.ti.com Hardware Configuration
Figure 4. Position of LEDs
Figure 5 illustrates the position of the various input and output connections on the TSW1200EVM.
The connection between the TSW1200EVM and the ADC EVM to be tested is through a 120-pin Samtecconnector. Fourteen LVDS data pairs plus two LVDS clock pairs have a defined position in the connectorpinout that is common between the TSW1200EVM and many TI ADC EVMs. For the parallel LVDS DDRdata format, the bit clock runs at the same rate as the sample clock to the ADC. For the serial LVDS dataformat, the bit clock runs at a higher multiple of the ADC sample clock and is used to strobe the serialdata into the TSW1200EVM and then deserialize the data. For the serial LVDS data format, a secondclock is provided, called the frame clock or FCLK, that runs at the sample rate and is used to delineate the
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3.4.2 JTAG Connector
Hardware Configuration www.ti.com
sample boundaries in the serial data stream. The frame clock line is unused in the parallel LVDS DDRformat. In addition, 14 extra LVDS pairs are defined in the connector and routed to the TSW1200EVMFPGA for future expansion for larger parallel bus widths needed for faster data converters. The datadirection for the LVDS data pairs is always defined as the ADC EVM driving the signal through theconnector to the TSW1200EVM FPGA, with integrated 100- Ωtermination in the FPGA.
For one-channel parallel DDR bit-wise data formats, eight of the LVDS data pairs are used to support upto 16-bit-resolution ADCs at up to 250-MHz sampling rates. For one-channel parallel DDR sample-wisedata formats, 14 of the LVDS data pairs are used to support up to 14-bit-resolution ADCs at up to500-MHz sampling rates. For two-channel parallel DDR bit-wise data formats, 14 of the LVDS data pairsare used to support two channels of 14-bit resolution at up to 250-MHz sampling rate.
For serial data formats, eight of the LVDS data pairs support up to eight channels of one-wire serial ADCsat up to 65-MHz sampling rate or four channels of two-wire serial ADCs at up to 125-MHz sampling rates.All other LVDS pairs are ignored for this release.
Five extra CMOS single-ended signals are defined in the Samtec connector that are sourced from theFPGA through the connector to the ADC EVM. These signals are optionally defined to allow the FPGA(under control of the TSW1200 user interface software) control the SPI serial programming of the ADC forthose ADC EVMs that support this feature. For those ADC EVMs that support this feature, the SPI signalsSEN (SPI Enable), SCLK (SPI Clk), and SDATA (SPI Data) are sourced by the TSW1200EVM FPGA toallow the TSW1200 user Interface to configure the operational mode of the ADC under evaluation. ThereSPI signals are by default not connected on the ADC EVM until a 0- Ωresistor is installed on the EVM toenable control of the SPI port from the TSW1200 user Interface software. Two additional signals, SPIReset and SPI Power Down, are defined for possible future use.
The Samtec connectors snap together with no screws or other mechanism to hold the TSW1200EVM andthe ADC EVM together. The TSW1200EVM comes with standoff posts for setting the TSW1200EVM flaton a bench or table. The ADC EVM has shorter standoff posts so that the TSW1200EVM and ADC EVMwill lay flat on a bench or table and stay snapped together during use.
The TSW1200EVM includes an industry-standard JTAG connector that loops the JTAG ports of the FPGAand the FPGA EEPROM. Jumpers on the TSW1200EVM allow for either the FPGA or the FPGAEEPROM to be removed from the JTAG chain. The most frequent use for the JTAG connector is toprogram the TSW1200EVM FPGA. An FPGA programming pod can be purchased inexpensively fromXilinx™ to program the FPGA or the FPGA EEPROM.
The FPGA programming pod can be used to load a programming bit file directly into the FPGA for debugand development. However, once the FPGA is power-cycled or programmed by the PROGRAMpushbutton, this loaded FPGA bit file will be lost and the FPGA will revert to the bit file that is stored in theFPGA EEPROM. The FPGA programming pod also can be used to store a new FPGA programming bitfile in the FPGA EEPROM so that the TSW1200 can be upgraded as new revisions of FPGA firmwarebecome available.
The part number of the Xilinx Platform Cable USB programming pod that can be used to program orupgrade the TSW1200EVM is DLC9G. The programming pod operates from a USB port of a PC andconnects directly with the TSW1200 JTAG connector through a ribbon cable supplied with theprogramming pod.
10 TSW1200EVM: High-Speed LVDS Deserializer and Analysis System SLAU212A – April 2007 – Revised August 2008Submit Documentation Feedback