Texas Instruments BQ25892EVM User manual

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Datasheet of BQ25892EVM-664 - EVAL MOD BQ25892 COMPLETE CHARGR
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BQ25892EVM-664
BQ25892EVM-664
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1
SLUUBA2B–March 2015–Revised November 2015
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bq25890EVM, bq25892EVM, bq25895EVM, bq25896EVM and
bq25895MEVM(PWR664)
Microsoft, Windows are registered trademarks of Microsoft Corporation.
User's Guide
SLUUBA2B–March 2015–Revised November 2015
bq25890EVM, bq25892EVM, bq25895EVM, bq25896EVM
and bq25895MEVM(PWR664)
This user's guide provides detailed testing instructions for the PWR664 evaluation modules (EVM) using
the bq25890, bq25892, bq25895, bq25896 or bq25895M (bq2589x) devices. Also included are
descriptions of the necessary equipment, equipment setup, and procedures. The reference documentation
contains the printed-circuit board layouts, schematics, and the bill of materials (BOM).
Contents
1 Introduction ................................................................................................................... 2
1.1 EVM Features....................................................................................................... 2
1.2 I/O Descriptions..................................................................................................... 2
2 Test Summary................................................................................................................ 4
2.1 Equipment ........................................................................................................... 4
2.2 Equipment Setup.................................................................................................... 5
2.3 Procedure............................................................................................................ 9
3 PCB Layout Guideline ..................................................................................................... 11
4 Board Layout, Schematic, and Bill of Materials ........................................................................ 12
4.1 PWR664 PCB Layouts ........................................................................................... 12
4.2 Schematics......................................................................................................... 16
4.3 Bill of Materials .................................................................................................... 21
List of Figures
1 Verify Windows 7 Properties ............................................................................................... 4
2 Connections of the EV2300 ................................................................................................ 5
3 Original Test Setup for PWR664 (bq2589x EVM)....................................................................... 5
4 Start Window of the bq2589x Evaluation Software...................................................................... 6
5 Part Select Window of the bq2589x Evaluation Software.............................................................. 6
6 Communications Adapter Error ............................................................................................ 7
7 Acknowledge Error .......................................................................................................... 7
8 DashBoard Status Tab...................................................................................................... 7
9 Select Field View ............................................................................................................ 8
10 Main Window of the bq2589x Evaluation Software ..................................................................... 8
11 Top Assembly............................................................................................................... 12
12 Top Layer ................................................................................................................... 13
13 Mid-Layer 1 ................................................................................................................. 13
14 Mid-Layer 2 ................................................................................................................. 14
15 Bottom Layer................................................................................................................ 14
16 Bottom Solder............................................................................................................... 15
17 Bottom Assembly .......................................................................................................... 15
18 bq25890 EVM Schematic ................................................................................................. 16
19 bq25892 EVM Schematic ................................................................................................. 17
20 bq25895 EVM Schematic ................................................................................................. 18
21 bq25895M EVM Schematic............................................................................................... 19
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22 bq25896 EVM Schematic ................................................................................................. 20
List of Tables
1 Device Data Sheets ......................................................................................................... 2
2 EVM Connections............................................................................................................ 2
3 Jumper Connections ........................................................................................................ 3
4 Recommended Operating Conditions..................................................................................... 3
5 bq25890EVM-664 Bill of Materials....................................................................................... 21
6 bq25892EVM-664 Bill of Materials....................................................................................... 23
7 bq25895EVM-664 Bill of Materials....................................................................................... 25
8 bq25895MEVM-664 Bill of Materials..................................................................................... 27
9 bq25896EVM-664 Bill of Materials....................................................................................... 29
1 Introduction
1.1 EVM Features
For detailed features and operation, refer to Table 1 for a list of devices and their data sheets.
Table 1. Device Data Sheets
Device Document
bq25890/bq25892 SLUSBU7
bq25895 SLUSC74
bq25895M SLUSCB5
bq25896 SLUSCF7
The bq2589x evaluation module (EVM) is a complete charger modules for evaluating an I2C-controlled
single NVDC-1 charge using the bq2589x device.
This EVM doesn’t include the USB-to-GPIO interface board. To evaluate the EVM, a USB-to-GPIO
interface board must be ordered separately.
1.2 I/O Descriptions
Table 2 lists the jumper connections available on this EVM.
Table 2. EVM Connections
Jack Description
J1–VBUS Input: positive terminal
J1–GND Input: negative terminal (ground terminal)
J2–PMID PMID pin connection/Power bank output
J2–GND Ground/Power bank output negative terminal
J3–SYS Connected to system
J3–GND Ground
J4–BAT+ Connected to battery pack
J4–GND Ground
J5 Input mini-USB port
J6 Output mini-USB port
J7 USB-to-GPIO connector
J8 I2C 4-pin connector
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Table 3 lists the EVM jumper connections.
Table 3. Jumper Connections
Jack Description Factory Setting
JP1 For bq25892/6 input current setting: Low: adaptor port; High: USB
input bq25890/5/5M: Not installed; bq25892/6: short PSEL to LOW
JP2 D–/PG pin selection bq25890/5/5M: short to D–; bq25892/6: short to PG
JP3 Pin 24 selection: to DSEL, PG, or NC bq25890/5/5M_DSEL: short to DSEL; bq25892/6:
not installed
JP4 STAT, PG, CE, INT, OTG pins internal pullup source (VSYS or BAT) Short to VSYS
JP5 D+/D– connections for input current limit setting bq25890/5/5M: installed; bq25892/6: Not installed
JP6 USB current limit selection pin during buck mode and PSEL is high/
Enable pin during boost mode Not installed
JP7 CE pin setting: pull low to enable the charge Not Installed
JP8 TS pin to GND Not Installed
JP9 TS resistor divider pullup source (REGN) connection Installed
JP10 Internal 10 k to GND to TS pin Installed
Table 4 lists the recommended operating conditions for this EVM.
Table 4. Recommended Operating Conditions
Symbol Description MIN TYP MAX Unit
Supply voltage, VIN
bq25890/2/5/5M/6 Input voltage from AC adapter 3.9 14 V
Battery voltage, VBAT 0 3.7 4.4 V Voltage applied at VBAT terminal 0 4.5 V
IBAT Fast charging current 5 A
Discharging current through internal MOSFET 9 A
Supply current, IIN Maximum input current from AC adapter input 0 3.25 A
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2 Test Summary
2.1 Equipment
This section includes a list of supplies required to perform tests on this EVM.
1. Power Supplies
Power supply #1 (PS#1): a power supply capable of supplying 5 V at 1 A is required. While this part
can handle larger voltage and current, it is not necessary for this procedure.
2. Load #1 (4-Quadrant Supply, Constant Voltage < 4.5 V)
A 0–20 V/0–5 A, > 30-W system, DC electronic load and setting as constant voltage load mode.
Or:
Kepco load: BOP 20–5M, DC 0 to ±20 V, 0 to ±5 A (or higher).
3. Load #2 – Use with Boost Mode
PMID to GND load, 10 Ω, 5 W or greater.
4. Meters
Six Fluke 75 multimeters, (equivalent or better).
Or:
Four equivalent voltage meters and two equivalent current meters. The current meters must be
capable of measuring 5 A+ current.
5. Computer
A computer with at least one USB port and a USB cable. The bq2589xEVM evaluation software must
be properly installed.
6. USB-to-GPIO Communication Kit (EV2300 USB-Based PC Interface Board)
7. Software
Double click the “BatteryManagementStudio-1.3.35_Build2-windows-installer” installation file, follow the
installation steps. The software supports the Microsoft®Windows®XP and Windows 7 operating
systems.
Install EV2300 Software
For Windows 7 64-bit users:
http://e2e.ti.com/support/power_management/battery_management/m/videos__files/458983.aspx.
Verify the computer Windows 7 settings by right clicking on computer and selecting properties:
Figure 1. Verify Windows 7 Properties
Windows XP or Windows 7 32-bit users must access the following: http://www.ti.com/litv/zip/slec003a.
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VIN
J1
J2
BAT
GN
C
I
N
SY
G
N
D
M
P
O
U
T
3
V
3
S
D
A
S
C
L
APPLICATION CIRCUIT
PWR583
bq24780EVM TP1
U
V
V
I
Powe
supply #1
VIN
J1
GND
J 3
BAT
GND
SYS
Application Circuit
PWR664
bq2589xMEVM TP1
U1
V
USB
V
EV2300
Power
Supply #1 J4 V
V
GND
J8
V
I
Load
Ibat
I
Iin
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2.2 Equipment Setup
1. Set PS#1 for 5-V DC, 1-A current limit and then turn off the supply.
2. Connect the output of PS#1 in series with a current meter (multimeter) to J1 (VBUS and GND).
3. Connect a voltage meter across TP3 (VBUS) and TP6 (PGND).
4. Turn on the Load, set to constant voltage mode and output to 2.5 V. Turn off (disable) Load. Connect
Load in series with a current meter (multimeter), ground side, to J4 (BAT+ and GND) as shown in
Figure 3.
5. Connect a voltage meter across J4 (BAT+ and GND).
6. Connect the EV2300 USB interface board to the computer with a USB cable and from I2C port to J8
with the 4-pin cable. The connections are shown in Figure 2.
7. Remove jumper (if installed) from JP5.
Figure 2. Connections of the EV2300
8. Install shunts as shown in Table 3.
Figure 3. Original Test Setup for PWR664 (bq2589x EVM)
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9. Turn on the computer. Launch the bq2589x evaluation software, choose Charger as shown in
Figure 4, then choose the appropriate .bqz file as shown in Figure 5.
Figure 4. Start Window of the bq2589x Evaluation Software
Figure 5 illustrates the following part selection options:
• Select the Charger_1_00-bq25890-895.bqz file, if evaluating the bq25890 or bq25895
• Select Charger_1_00-bq25892-896.bqz, if evaluating the bq25892
Figure 5. Part Select Window of the bq2589x Evaluation Software
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10. If an error pops up stating the communications adapter was not found (Figure 6), click OK to proceed.
Next, unplug and re-plug the adapter.
Figure 6. Communications Adapter Error
If an error pops up stating there is no acknowledge from the device (Figure 7), click OK to proceed and
then pick the appropirate I2C address from the drop-down menu in the GUI (see the Procedure
section).
Figure 7. Acknowledge Error
Check the connection status of the EV2300 in bqStudio by going to View →DashBoard. A panel on
the left-hand side should appear, with the status of the EV2300 at the top (Figure 8).
Figure 8. DashBoard Status Tab
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11. Choose Field View, as shown in Figure 9. The main window of the bq2589x software is shown in
Figure 10.
Figure 9. Select Field View
Figure 10. Main Window of the bq2589x Evaluation Software
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2.3 Procedure
2.3.1 Communication Verification
1. In the EVM software, specify device “I2C Address” as D6 for bq25892/6, and D4 for bq25890/5.
2. Enable Load#1 from Section 2.2, step 4. Click the Read button
3. In the EVM GUI software (see example screen shot below) , make the following changes as
necessary:
• Select “Disabled” for the “Watchdog Timer”
• Select "Force VINDPM"
• Set “Input Voltage Limit” to 4.2
• Set “Input Current Limit” to 500 mA
• Set “Charge Voltage Limit” to 4.208 V
• Set “Fast Charge Current” ICHG to 960 mA
• Set "Minimum System Voltage" to 3.5V
• Set “Pre-Charge Current” to 256 mA
• Select "Charge Enable"
• Deselect "Enable ILIM pin"
• Deselect "Enable ICD"
• Deselect “Enable Termination”
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2.3.2 Charger Mode Verification
1. Turn on PS#1, click the Read button twice:
•Observe →Everything Normal at Fault box
•Observe →D3 (STAT) is on
•Observe →D4 (PG) is on (bq25892/6)
2. Measure the voltage across J3 and J4 as follows:
•Measure →V(TP4(SYS), TP7(GND)) = 3.65 V ±300 mV
•Measure →V(TP5(BAT), TP7(GND)) = 2.5 V ±200 mV
3. Change load to 3.7 V
•Measure →I(BAT) = 625 mA ± 100 mA
•Measure →V(TP5(BAT), TP7(GND)) = 3.7 V ±200 mV
•Measure →I(VBUS) = 500 mA ± 200mA
2.3.3 Boost Mode Verification
1. Turn off and disconnect PS#1
2. If the constant voltage load connected from BAT+ to GND is not a four-quadrant supply (sources
current), remove the load and use the power source disconnected in step one, set to 3.7-V and 2-A
current limit and connect between BAT+ and GND
3. Check the OTG configurations option in the GUI
4. Apply 10 Ω(5 W or greater) across J2 (PMID(+) to GND(–))
•Measure: V: (TP2 (PMID) and TP6 (GND)) = 5.0 V ±200 mV
2.3.4 Helpful Hints
1. The leads/cables to the various power supplies, batteries and loads have resistance. The current
meters also have series resistance. The charger dynamically reduces charge current depending on the
voltage sensed at its VBUS pin (using the VINDPM feature), BAT pin (as part of normal termination)
and TS pin (through its battery temperature monitoring feature via battery thermistor). Therefore, you
must use voltmeters to measure the voltage as close to the IC pins as possible instead of relying on
the power supply's digital readouts. If a battery thermistor is not available, either disable the TS
function or replace with an appropriately sized (typically) 10 kΩresistor.
2. When using a sourcemeter that can source and sink current as your battery simulator, it is highly
recommended to add a large (1000 µF+) capacitor at the EVM BAT and GND connectors in order to
prevent oscillations at the BAT pin due to mismatched impedances of the charger output and
sourcemeter input within their respective regulation loop bandwidths. Configuring the sourcemeter for
4-wire sensing eliminates the need for a separate voltmeter to measure the voltage at the BAT pin.
When using 4-wire sensing, always ensure that the sensing leads are connected in order to prevent
accidental overvoltage by the power leads.
3. For precise measurements of charge current and battery regulation near termination, the current meter
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in series with the battery or battery simulator should not be set to auto-range and may need be
removed entirely. An alternate method for measuring charge current is to either use an oscilloscope
with hall effect current probe or place a 1% or better, thermally capable (for example, 0.010 Ωin 1210
or larger footprint) resistor in series between the BAT pin and battery and measure the voltage across
that resistor.
3 PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID and GND pin connections and use the
shortest possible copper trace connection or GND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or GND plane.
4. Route analog ground separately from power ground. Connect analog ground and connect power
ground separately. Connect analog ground and power ground together using power pad as the single
ground connection point or use a 0-Ωresistor to tie analog ground to power ground.
5. Use a single ground connection to tie the charger power ground to the charger analog ground just
beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise
coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, refer to Quad Flatpack No-Lead Logic Packages (SCBA017) and QFN/SON PCB
Attachment (SLUA271).
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4 Board Layout, Schematic, and Bill of Materials
This section contains the board layouts,schematics, and BOM.
4.1 PWR664 PCB Layouts
Figure 11 through Figure 17 show the PCB layouts for the PWR664 EVM.
Figure 11. Top Assembly
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Figure 12. Top Layer
Figure 13. Mid-Layer 1
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Figure 14. Mid-Layer 2
Figure 15. Bottom Layer
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Figure 16. Bottom Solder
Figure 17. Bottom Assembly
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PGND
VBUS
VBUS
GND
PMID
GND
System
GND
Battery
GND
Vbus: 3.9V to 14V
J3
VBUS 1
D- 2
D+ 3
ID 4
GND 5
6 7 8
11 10 9
J5
J2
J1
1000pF
C8
DNP
PGND
PMID
0
R13
10.0k
R14
10.0k
R15
10.0k
R5
0.047µF
C4
AGND
REGN
1000pF
C17
DNP
PGND
SYS
PGND
J4
1000pF
C20
DNP
BAT
PGND
1 2
3 4
5 6
7 8
9 10
J7
D+/PSEL
D-/PG
JP6
1
2
3
JP2
STAT
SCL
SDA
PULL-UP
PULL-UP
INT
OTG
CE
AGND
10.0k
R6
PULL-UP
10.0k
R7
DNP
JP7
AGND
768
R18
ILIM
TS
Green
D3
Green
D4
2.21k
R21
2.21k
R22
PULL-UP
STAT PG
AGND
D-
PG
10µF
C13
DNP
30.1k
R3
5.23k
R2
VBUS
200
R9
200
R11
200
R12
CE
SDA
SCL
JP9
REGN
JP8
10.0k
R8
JP10
AGND
TS
GND
TP2
TP3
TP10
TP4
TP5
D-/PG
OTG
TP11
TP16
REGN
STAT
CE
TP17
TP18
TP12
SCL
SDA TS
TP14
TP19
TP20
INT
TP13
TP15
10µF
C12
DNP
10µF
C11
DNP
TP6
PGND
TP8
AGND
TP7
QON
PG
D-
1
2
3
JP1
D+/PSEL
AGND
REGN
PSEL
HI
LOW
TEST POINTS
10.0k
R4
PGND
PGND
130
R1
D1
DNP
TS
AGND
1D+ 1
1D- 2
2D+ 3
2D- 4
GND
5
OE 6
D-
7
D+
8
S9
VCC 10
U3
TS3USB221ARSER
1000pF
C9
DNP
PGND
VIN
1
GND 2
ON/OFF
3
BYPASS
4
VOUT 5
U2
LP2985AIM5-3.3/NOPB
JP5
D-
D+/PSEL
1µF
C23
2.2µF
C24
0.01µF
C22
100k
R10
VBUS 3.3V
PGND
VBUS
1
D-
2
D+
3
ID
4
GND
5
6 7 8
11 10 9
J6
ID ID
10.0k
R20
DSEL
3.3V
PGND
VBUS
PGND
PGND
4
1
2
3
J8
PGND
SCL
SDA
1
2
3
JP3
DSEL
PG
PG
DSEL
10k
R19
4.7µF
C3
1 4
S2A
2 3
S2B
QON
0
R16
0.01µF
C21
DNP
CE
4.7k
R23
AGND
S1
10µF
C2
1uH
L1
1.00
R17
DNP
0.1µF
C14
DNP
1µF
C18
DNP
1
2
3
JP4
10µF
C5
10µF
C6
10µF
C15
DNP
10µF
C16
DNP
10µF
C7
10µF
C19
DNP
10.0k
R24
1.5µH
L2
DNP
1µF
C1
DSEL
TP9
D+/PSEL
ILIM
TP21
D5
DNP
D2
DNP
22µF
C10
DNP
NT1
Net-Tie
VSYS: 3.5V to 4 .75V
ICHG: 0 ~ 5A
VBUS
1
D+
2
D-
3
STAT
4
SCL
5
SDA
6BAT 13
BAT 14
SYS 15
SYS 16
PGND 17
PGND 18
INT
7
OTG/IUSB
8
CE
9
ILIM
10
TS
11
QON
12 SW 19
SW 20
BTST 21
REGN 22
PMID 23
DSEL 24
PAD 25
U1
BQ25890RTWR
Board Layout, Schematic, and Bill of Materials www.ti.com
16 SLUUBA2B–March 2015–Revised November 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
bq25890EVM, bq25892EVM, bq25895EVM, bq25896EVM and
bq25895MEVM(PWR664)
4.2 Schematics
The bq25890EVM (Figure 18), bq25892EVM (Figure 19), bq25895EVM (Figure 21), bq25896EVM (Figure 22) and bq25895MEVM (Figure 21)
schematics are provided for reference.
Figure 18. bq25890 EVM Schematic
17 / 37
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Distributor of Texas Instruments: Excellent Integrated System Limited
Datasheet of BQ25892EVM-664 - EVAL MOD BQ25892 COMPLETE CHARGR
Contact us: [email protected] Website: www.integrated-circuit.com
PGND
VBUS
VBUS
GND
PMID
GND
System
GND
Battery
GND
Vbus: 3.9V to 14V
J3
VBUS 1
D- 2
D+ 3
ID 4
GND 5
6 7 8
11 10 9
J5
J2
J1
1000pF
C8
DNP
PGND
PMID
0
R13
10.0k
R14
10.0k
R15
10.0k
R5
0.047µF
C4
AGND
REGN
1000pF
C17
DNP
PGND
SYS
PGND
J4
1000pF
C20
DNP
BAT
PGND
1 2
3 4
5 6
7 8
9 10
J7
D+/PSEL
D-/PG
JP6
1
2
3
JP2
STAT
SCL
SDA
PULL-UP
PULL-UP
INT
OTG
CE
AGND
10.0k
R6
PULL-UP
10.0k
R7
DNP
JP7
AGND
768
R18
ILIM
TS
Green
D3
Green
D4
2.21k
R21
2.21k
R22
PULL-UP
STAT PG
AGND
D-
PG
10µF
C13
DNP
30.1k
R3
5.23k
R2
VBUS
200
R9
200
R11
200
R12
CE
SDA
SCL
JP9
REGN
JP8
10.0k
R8
JP10
AGND
TS
GND
TP2
TP3
TP10
TP4
TP5
D-/PG
OTG
TP11
TP16
REGN
STAT
CE
TP17
TP18
TP12
SCL
SDA TS
TP14
TP19
TP20
INT
TP13
TP15
10µF
C12
DNP
10µF
C11
DNP
TP6
PGND
TP8
AGND
TP7
QON
PG
D-
1
2
3
JP1
D+/PSEL
AGND
REGN
PSEL
HI
LOW
TEST POINTS
10.0k
R4
PGND
PGND
130
R1
D1
DNP
TS
AGND
1D+ 1
1D- 2
2D+ 3
2D- 4
GND
5
OE 6
D-
7
D+
8
S9
VCC 10
U3
TS3USB221ARSER
1000pF
C9
DNP
PGND
VIN
1
GND 2
ON/OFF
3
BYPASS
4
VOUT 5
U2
LP2985AIM5-3.3/NOPB
JP5
D-
D+/PSEL
1µF
C23
2.2µF
C24
0.01µF
C22
100k
R10
VBUS 3.3V
PGND
VBUS
1
D-
2
D+
3
ID
4
GND
5
6 7 8
11 10 9
J6
ID ID
10.0k
R20
DSEL
3.3V
PGND
VBUS
PGND
PGND
4
1
2
3
J8
PGND
SCL
SDA
1
2
3
JP3
DSEL
PG
PG
DSEL
10k
R19
4.7µF
C3
1 4
S2A
2 3
S2B
QON
0
R16
DNP
0.01µF
C21
DNP
CE
4.7k
R23
AGND
S1
10µF
C2
1uH
L1
1.00
R17
DNP
0.1µF
C14
DNP
1µF
C18
DNP
1
2
3
JP4
10µF
C5
10µF
C6
10µF
C15
DNP
10µF
C16
DNP
10µF
C7
10µF
C19
DNP
10.0k
R24
1.5µH
L2
DNP
1µF
C1
DSEL
TP9
D+/PSEL
ILIM
TP21
D5
DNP
D2
DNP
22µF
C10
DNP
NT1
Net-Tie
VSYS: 3.5V to 4 .75V
ICHG: 0 ~ 5A
VBUS
1
PSEL
2
PG
3
STAT
4
SCL
5
SDA
6
PAD 25
INT
7
OTG/IUSB
8
CE
9
ILIM
10
TS
11
QON
12
BAT 13
BAT 14
SYS 15
SYS 16
PGND 17
PGND 18
SW 19 SW 20
BTST 21
REGN 22
PMID 23
NC 24
U1
BQ25892RTWR
www.ti.com Board Layout, Schematic, and Bill of Materials
17
SLUUBA2B–March 2015–Revised November 2015
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
bq25890EVM, bq25892EVM, bq25895EVM, bq25896EVM and
bq25895MEVM(PWR664)
Figure 19. bq25892 EVM Schematic
18 / 37
18 / 37

Distributor of Texas Instruments: Excellent Integrated System Limited
Datasheet of BQ25892EVM-664 - EVAL MOD BQ25892 COMPLETE CHARGR
Contact us: [email protected] Website: www.integrated-circuit.com
PGND
VBUS
VBUS
GND
PMID
GND
System
GND
Battery
GND
Vbus: 3.9V to 14V
J3
VBUS 1
D- 2
D+ 3
ID 4
GND 5
6 7 8
11 10 9
J5
J2
J1
1000pF
C8
DNP
PGND
PMID
0
R13
10.0k
R14
10.0k
R15
10.0k
R5
0.047µF
C4
AGND
REGN
1000pF
C17
DNP
PGND
SYS
PGND
J4
1000pF
C20
DNP
BAT
PGND
1 2
3 4
5 6
7 8
9 10
J7
D+/PSEL
D-/PG
JP6
1
2
3
JP2
STAT
SCL
SDA
PULL-UP
PULL-UP
INT
OTG
CE
AGND
10.0k
R6
PULL-UP
10.0k
R7
DNP
JP7
AGND
768
R18
ILIM
TS
Green
D3
Green
D4
2.21k
R21
2.21k
R22
PULL-UP
STAT PG
AGND
D-
PG
10µF
C13
30.1k
R3
5.23k
R2
VBUS
200
R9
200
R11
200
R12
CE
SDA
SCL
JP9
REGN
JP8
10.0k
R8
JP10
AGND
TS
GND
TP2
TP3
TP10
TP4
TP5
D-/PG
OTG
TP11
TP16
REGN
STAT
CE
TP17
TP18
TP12
SCL
SDA TS
TP14
TP19
TP20
INT
TP13
TP15
10µF
C12
10µF
C11
TP6
PGND
TP8
AGND
TP7
QON
PG
D-
1
2
3
JP1
D+/PSEL
AGND
REGN
PSEL
HI
LOW
TEST POINTS
10.0k
R4
PGND
PGND
130
R1
D1
DNP
TS
AGND
1D+ 1
1D- 2
2D+ 3
2D- 4
GND
5
OE 6
D-
7
D+
8
S9
VCC 10
U3
TS3USB221ARSER
1000pF
C9
DNP
PGND
VIN
1
GND 2
ON/OFF
3
BYPASS
4
VOUT 5
U2
LP2985AIM5-3.3/NOPB
JP5
D-
D+/PSEL
1µF
C23
2.2µF
C24
0.01µF
C22
100k
R10
VBUS 3.3V
PGND
VBUS
1
D-
2
D+
3
ID
4
GND
5
6 7 8
11 10 9
J6
ID ID
10.0k
R20
DSEL
3.3V
PGND
VBUS
PGND
PGND
4
1
2
3
J8
PGND
SCL
SDA
1
2
3
JP3
DSEL
PG
PG
DSEL
10k
R19
4.7µF
C3
1 4
S2A
2 3
S2B
QON
0
R16
0.01µF
C21
DNP
CE
4.7k
R23
AGND
S1
10µF
C2
2.2uH
L1
1.00
R17
DNP
0.1µF
C14
DNP
1µF
C18
DNP
1
2
3
JP4
10µF
C5
10µF
C6
10µF
C15
DNP
10µF
C16
DNP
10µF
C7
10µF
C19
DNP
10.0k
R24
1.5µH
L2
DNP
1µF
C1
DSEL
TP9
D+/PSEL
ILIM
TP21
D5
DNP
D2
22µF
C10
NT1
Net-Tie
VSYS: 3.5V to 4 .75V
ICHG: 0 ~ 5A
VBUS
1
D+
2
D-
3
STAT
4
SCL
5
SDA
6
INT
7
OTG
8
CE
9
ILIM
10
TS
11
QON
12
BAT 13
BAT 14
SYS 15
SYS 16
PGND 17
PGND 18
SW 19 SW 20
BTST 21
REGN 22
PMID 23
DSEL 24
PAD 25
U1
BQ25895RTWR
Board Layout, Schematic, and Bill of Materials www.ti.com
18 SLUUBA2B–March 2015–Revised November 2015
Submit Documentation Feedback
Copyright © 2015, Texas Instruments Incorporated
bq25890EVM, bq25892EVM, bq25895EVM, bq25896EVM and
bq25895MEVM(PWR664)
Figure 20. bq25895 EVM Schematic
19 / 37
19 / 37

Distributor of Texas Instruments: Excellent Integrated System Limited
Datasheet of BQ25892EVM-664 - EVAL MOD BQ25892 COMPLETE CHARGR
Contact us: [email protected] Website: www.integrated-circuit.com
PGND
VBUS
VBUS
GND
PMID
GND
System
GND
Battery
GND
Vbus: 3.9V to 14V
J3
VBUS 1
D- 2
D+ 3
ID 4
GND 5
6 7 8
11 10 9
J5
J2
J1
1000pF
C8
DNP
PGND
PMID
0
R13
10.0k
R14
10.0k
R15
10.0k
R5
0.047µF
C4
AGND
REGN
1000pF
C17
DNP
PGND
SYS
PGND
J4
1000pF
C20
DNP
BAT
PGND
1 2
3 4
5 6
7 8
9 10
J7
D+/PSEL
D-/PG
JP6
1
2
3
JP2
STAT
SCL
SDA
PULL-UP
PULL-UP
INT
OTG
CE
AGND
10.0k
R6
PULL-UP
10.0k
R7
DNP
JP7
AGND
768
R18
ILIM
TS
Green
D3
Green
D4
2.21k
R21
2.21k
R22
PULL-UP
STAT PG
AGND
D-
PG
10µF
C13
30.1k
R3
5.23k
R2
VBUS
200
R9
200
R11
200
R12
CE
SDA
SCL
JP9
REGN
JP8
10.0k
R8
JP10
AGND
TS
GND
TP2
TP3
TP10
TP4
TP5
D-/PG
OTG
TP11
TP16
REGN
STAT
CE
TP17
TP18
TP12
SCL
SDA TS
TP14
TP19
TP20
INT
TP13
TP15
10µF
C12
10µF
C11
TP6
PGND
TP8
AGND
TP7
QON
PG
D-
1
2
3
JP1
D+/PSEL
AGND
REGN
PSEL
HI
LOW
TEST POINTS
10.0k
R4
PGND
PGND
130
R1
D1
DNP
TS
AGND
1D+ 1
1D- 2
2D+ 3
2D- 4
GND
5
OE 6
D-
7
D+
8
S9
VCC 10
U3
TS3USB221ARSER
1000pF
C9
DNP
PGND
VIN
1
GND 2
ON/OFF
3
BYPASS
4
VOUT 5
U2
LP2985AIM5-3.3/NOPB
JP5
D-
D+/PSEL
1µF
C23
2.2µF
C24
0.01µF
C22
100k
R10
VBUS 3.3V
PGND
VBUS
1
D-
2
D+
3
ID
4
GND
5
6 7 8
11 10 9
J6
ID ID
10.0k
R20
DSEL
3.3V
PGND
VBUS
PGND
PGND
4
1
2
3
J8
PGND
SCL
SDA
1
2
3
JP3
DSEL
PG
PG
DSEL
10k
R19
4.7µF
C3
1 4
S2A
2 3
S2B
QON
0
R16
0.01µF
C21
DNP
CE
4.7k
R23
AGND
S1
10µF
C2
2.2uH
L1
1.00
R17
DNP
0.1µF
C14
DNP
1µF
C18
DNP
1
2
3
JP4
10µF
C5
10µF
C6
10µF
C15
DNP
10µF
C16
DNP
10µF
C7
10µF
C19
DNP
10.0k
R24
1.5µH
L2
DNP
1µF
C1
DSEL
TP9
D+/PSEL
ILIM
TP21
D5
DNP
D2
22µF
C10
NT1
Net-Tie
VSYS: 3.5V to 4 .75V
ICHG: 0 ~ 5A
VBUS
1
D+
2
D-
3
STAT
4
SCL
5
SDA
6BAT 13
BAT 14
SYS 15
SYS 16
PGND 17
PGND 18
INT
7
OTG/IUSB
8
CE
9
ILIM
10
TS
11
QON
12 SW 19
SW 20
BTST 21
REGN 22
PMID 23
DSEL 24
PAD 25
U1
BQ25895MRTWR
www.ti.com Board Layout, Schematic, and Bill of Materials
19
SLUUBA2B–March 2015–Revised November 2015
Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
bq25890EVM, bq25892EVM, bq25895EVM, bq25896EVM and
bq25895MEVM(PWR664)
Figure 21. bq25895M EVM Schematic
20 / 37
20 / 37