Texas Instruments TA 5 42EVM-K Series User manual

EVM User's Guide: TAA5242EVM-K TAD5242EVM-K TAC5142EVM-K
TAC5242EVM-K
TAx5x42EVM-K Hardware Control Evaluation Module
Description
The TAx5x42EVM-K evaluation module (EVM)
allows the user to test the capabilities of Texas
Instruments’ TAC5242; a two-channel hardware
control high-performance Codec, TAC5142 a two-
channel hardware control Codec, TAA5242 a two-
channel hardware control high-performance ADC
or TAD5242 a two-channel hardware control high-
performance DAC. The evaluation module is paired
with the AC-MB, a flexible motherboard which
provides power, control and digital audio data to
the evaluation module. Other variants listed are also
supported where the user replaces the U1 unit with
the device of interest.
Get Started
1. Order the EVM from TAx5x1x product folder.
2. Download the latest TAx5x1x data sheet.
Features
• High performance Mono/Stereo Codec with
dynamic range: 120 dB DAC and 115 dB ADC
• Standard performance Mono/Stereo Codec with
dynamic range: 106 dB DAC and 102 dB ADC
• On-board microphones provided for voice
recording testing
• Direct access to digital audio signals and control
interface for simple end-system integration
• USB connection to PC provides power, control,
and streaming audio data for easy evaluation
Applications
• AV receivers
•Video conference systems
•IP network camera
• Speakers
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1 Evaluation Module Overview
1.1 Introduction
The TAx5x42EVM is an evaluation module (EVM) designed to demonstrate the performance and functionality
of the TAx5x42 family of devices. This family includes the devices shown in Table 1-1 with differences in
performance and function noted.
Table 1-1. TAx5x42 Hardware Control Family
Device ADC DR (dB) DAC DR (dB) Feature
TAC5242 115 120 Stereo CODEC
TAC5142 102 106 Stereo CODEC
TAA5242 115 NA Stereo ADC
TAD5242 NA 120 Stereo DAC
TAD5142 NA 106 Stereo DAC
This user's guide describes the functionality of TAC5242EVM-K, TAC5142EVM-K, TAA5242EVM-K or
TAD5242EVM-K evaluation kit obtainable from ti.com.
1.2 Kit Contents
• TAC5242, TAC5142, TAA5242, TAD5242 or TAD5142 device
• TAx5x42 EVM/daughterboard
• AC-MB Controller/motherboard
1.3 Specification
The TAx5x42EVM-K evaluation module (EVM) paired with the AC-MB, a flexible motherboard which provides
power, control and digital audio data to the evaluation module allows user to record and playback audio signal.
The configuration for the TAC5242, TAC5142, TAA5242, TAD5242 or TAD5142 device is done through the
various Multi-Function pins (MD0 - MD6).
1.4 Device Information
• TAC5242, a hardware control low power stereo audio codec with 115 dB dynamic range ADC, 120 dB
dynamic range DAC.
• TAC5142, a hardware control low power stereo audio codec with 102 dB dynamic range ADC, 106 dB
dynamic range DAC.
• TAA5242, a hardware control low-power stereo audio ADC with 115 dB dynamic range.
• TAD5242, a hardware control low-power stereo audio DAC with 120 dB dynamic range.
• TAD5142, a hardware control low-power stereo audio DAC with 106 dB dynamic range.
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2 Hardware
2.1 Setup
The evaluation kit consists of the TAx5x42EVM daughterboard and the AC-MB controller board. The controller
board is used to provide power, control, and digital audio signals to the evaluation module. The daughterboard
contains the TAx5x42 device and the input output connections.
USB Power
Selection
+5 V
USB Data
USB Vbus
S/PDIF Out
S/PDIF IN
VINL/R
XMOS ASI
9211 ASI
External
Power
+5-V Input
Level
Translator
Buffer
Mux AC-MB ASI EVM ASI
+3.3 V
+1.8 V
+1 V
Power-On Reset
JTAG
IOVDD
Selection
IOVDD
/POR
/RESET_SW
/RESET
EVM
IOVDD
+5 V
MCLK
BCLK
FSYNC
DIN 1-4
DOUT 1-4
/RESET
XMOS
Interface
PCM9211
Interface
Optical Input
Optical Output
Analog Input
USB
XTAG
Power-On Reset
TAC5XXX
4x4
IC ASI
MD0/ADDR
LDO
+3.3 V
INX
+5 V
IOVDD
+1.2 V
AVDD
Selection
+1.8 V
AC_MB EVM
Power Rails
Main
Rest
External ASI
Connector
Digital Audio
Selection Switch
AUDIO INPUT
CONNECTION
AUDIO OUTPUT
CONNECTION
IOVDD
AVDD
OUTX
Master/Slave
Selection
Audio
Configuration 1
Audio
Configuration 2
HPF/Slot Data
Selection
MD1
MD2
MD3
Input Channel
Configuration 2
Input Channel
Configuration 1
Figure 2-1. TAx5x42 EVM Block Diagram
2.2 AC-MB Settings
2.2.1 Audio Serial Interface Settings
The AC-MB provides the digital audio signals to the evaluation module from the universal serial bus (USB),
optical, stereo jack, and external audio serial interface (ASI) header. Figure 2-2 shows a block diagram of the
ASI routing on the AC-MB.
Figure 2-2. AC-MB Audio Interface Block Diagram
Switch SW2 on the AC-MB selects the audio serial bus that interfaces with the PCM6xx0EVM. Next to switch
SW2, the AC-MB has a quick reference table to identify the audio serial interface source options and switch
settings. The AC-MB acts as the Controller for the audio serial interface, with three different modes of operation:
USB, optical or analog, or external ASI.
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The serial interface clocks and data are provided from the USB interface. The sampling rate and format are
determined by the USB audio class driver on the operating system. The default settings for the USB audio
interface are 32-bit frame size, 48-kHz sampling rate, BCLK and FSYNC ratio is 256, and the format is
timedivision multiplexing (TDM).
2.2.1.1 USB Mode
The AC-MB is detected by the OS as an audio device with the name TI USB Audio UAC2.0. Figure 2-3 shows
the AC-MB audio setting for the USB mode of operation.
Figure 2-3. AC-MB USB Audio Setting
2.2.1.2 Optical or Auxiliary Analog Audio Input Mode
Serial interface signals are provided from the PCM9211 digital transceiver, which is capable of sending digital
data to the EVM from an analog input or optical input. Meanwhile, the data from the EVM can be streamed
through the optical output.
Figure 2-4 shows the AC-MB audio setting for the optical and analog mode of operation.
Figure 2-4. AC-MB Optical or Auxiliary Analog Audio Input Setting
The optical output of the AC-MB streams the data captured on the EVM with the format determined by the input
source used. When there is an optical input connected, the LOCK LED must be ON, and the PCM9211 streams
the audio serial interface clocks with the format determined by the optical input frame. The digital data from the
optical input is streamed to the evaluation module. If the optical input is not connected, the PCM9211 captures
the input signal provided through the analog input, and streams the signal to the evaluation module. This feature
can be useful when a digital input digital-to-analog converter (DAC) is connected to the AC-MB, providing an
analog input for quick evaluation. In auxiliary analog audio mode, the audio serial interface format is fixed to a
24-bit, 48-kHz, I2S mode.
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2.2.1.3 External Audio Interface Mode
In this mode, the audio serial interface clocks for the evaluation board are provided through connector J7 from
an external source. This architecture allows an external system to be used for communication with the evaluation
board, such as a different host processor or test equipment (Audio Precision®). The clocks generated from the
USB interface and PCM9211 are isolated with this setting. Figure 2-5 shows the AC-MB audio setting for the
external mode of operation.
Figure 2-5. AC-MB External Audio Interface Setting
Figure 2-6 shows how to connect the external audio interface. Odd numbered pins are signal carrying, and even
numbered pins are connected to ground.
Figure 2-6. AC-MB Connection with External Audio Serial Interface
2.2.2 AC-MB Power Supply
The complete EVM system is powered from a single 5-V power supply. However, the motherboard has different
low-dropout regulators (LDOs) integrated that provide the required power supplies to the different blocks of the
board. Figure 2-7 shows a block diagram depicting the power structure of the AC-MB.
USB Power
Selection
+5 V
USB Vbus
External
Power
+5-V Input
+3.3 V
+1.8 V
+1 V
Power-On Reset
IOVDD
Selection
IOVDD IOVDD
+5 V
USB
+1.2 V
Power Rails
TO EVM
J9 J3
J4
J1
J5
Figure 2-7. Power-Supply Distribution of the AC-MB
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The AC-MB can be powered from the host computer by using the USB 5-V power supply (VBUS) by shorting
header J5, USB POWER. Additionally, the AC-MB can be powered from an external power supply connected to
terminal J4, EXTERNAL POWER. Header J5 must be open for external supply operation. The IOVDD voltage
for the digital signals that is provided to the evaluation module is generated on the motherboard from the main
power supply (USB or external).
The voltage levels available are 1.2V, 1.8 V and 3.3 V, and can be selected via the J9, J3 header IOVDD. For
1.2-V operation, short pin 1 of header J9 and pin 2 of header J3, for 1.8-V operation, short pins 2 and 3 of
header J3; for 3.3-V operation, short pins 1 and 2 of header J3. When the motherboard is fully powered and the
power supplies from the onboard LDOs are correct, the green POWER LED (D3) turns ON. The USB READY
LED indicates that a successful USB communication is established between the AC-MB and the host computer.
2.3 TAx5x42EVM-K Hardware Settings
2.3.1 TAx5x42 EVM Input Hardware Settings
The TAx5x42 evaluation module has several input configuration options and offers extensive flexibility to allow
the user to evaluate the device across multiple operation modes. The different operation modes are highlighted
in this section.
Figure 2-8. TAC5242/TAC5142/TAA5242 EVM Input Architecture for Channel 1 and 2
The IN1 and IN2 input architecture allows these two channels to be quickly configured to support any of
the supported operation modes. The INxP and INxM pins of the TAx5x42 can optionally connect to onboard
microphones for quick evaluation of a microphone in AC- or DC-coupled modes. Jumper configuration details
can be found in Table 2-1.
For TAD5242 or TAD5142, IN1 and IN2 components are not populated.
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Table 2-1. Input Jumper Configuration
Input Terminal Input Mode Installed
Jumpers Uninstalled Jumper Input Swing Topology
IN1 LINE-IN Differential, AC-
coupled J8 J4, J5, J6, J11, J12, J15, J16, J20, J21 2 VRMS
LINE-IN Single-ended, AC-
coupled J6, J8, J12 (2-3) J4, J5, J11, J15, J16, J20, J21 1 VRMS
LINE-IN Differential, DC-
coupled J15, J16
J4, J5, J6, J11, J12,
J20, J21, J8 (DUT
MICBIAS is not used)
2 VRMS
LINE-IN Single-ended, DC-
coupled
J6, J12 (2-3),
J15, J16
J4, J5, J11, J20, J21,
J8 (DUT MICBIAS is not
used)
1 VRMS
On-board Electret
Condenser Microphone
(ECM) Differential, AC-
coupled
J4, J5, J8, J11,
J12 (1-2) J6, J15, J16, J20, J21
Refer to
Microphone data
sheet
On-board Electret
Condenser Microphone
(ECM) Single-ended, AC-
coupled
J4, J5, J8, J11,
J12 (2-3) J6, J15, J16, J20, J21
Refer to
Microphone data
sheet
On-board Electret
Condenser Microphone
(ECM) Differential, DC-
coupled
J4, J5, J8, J11,
J12 (1-2), J15,
J16
J6, J20, J21
Refer to
Microphone data
sheet
On-board Electret
Condenser Microphone
(ECM) Single-ended, DC-
coupled
J4, J5, J8, J11,
J12 (2-3), J15,
J16
J6, J20, J21
Refer to
Microphone data
sheet
IN2 LINE-IN Differential, AC-
coupled J8 J7, J9, J13, J14, J17, J18, J22, J23, J46 2 VRMS
LINE-IN Single-ended, AC-
coupled J7, J8, J14 (2-3) J9, J13, J17, J18, J22, J23, J46 1 VRMS
LINE-IN Differential, DC-
coupled J17, J18
J7, J9, J13, J14, J22,
J23, J46, J8 (DUT
MICBIAS is not used)
2 VRMS
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Table 2-1. Input Jumper Configuration (continued)
Input Terminal Input Mode Installed
Jumpers Uninstalled Jumper Input Swing Topology
LINE-IN Single-ended, DC-
coupled
J7, J14 (2-3),
J17, J18
J9, J13, J22, J23, J46,
J8 (DUT MICBIAS is not
used)
1 VRMS
On-board Analog MEMS
microphone, AC-coupled J8, J9, J46 J7, J13, J14, J17, J18, J22, J23
Refer to
Microphone data
sheet
On-board Analog MEMS
microphone, DC-coupled J9, J17, J18, J46
J7, J13, J14, J22, J23,
J8 (DUT MICBIAS is not
used)
Refer to
Microphone data
sheet
2.3.1.1 Line Inputs
For the line input configuration shown in Figure 2-8, the TAx5x42 captures the audio signal provided through
RCA terminals J2 (IN1), J3 (IN2) or header J47 or J48. The RCA white connector is connected to the INxP and
RCA red connector is connected to the INxM. Depending on differential or single-ended configuration, populate
J6 or J7 jumper as described in the Input Jumper Configuration table above accordingly. The input accepted in
AC/DC-Coupled mode is a differential 2-VRMS full-scale audio signal and if a single-ended source is used, the
1-VRMS signal is supported.
2.3.1.2 On-board Microphone Input
For the on-board microphone input configuration shown in Figure 2-8, the TAx5x42 records the audio captured
from the microphones MK1 (ECM) or U5 (Analog MEMS), which is located on the bottom of the board. Electret
Microphone (MK1) is connected to IN1P/M, and MICBIAS is used to power the on-board microphone, so header
J8 must be installed. For MEMS microphone (U5), this can be configured as either a single ended or differential
input and is connected to IN2P/M. There must not be any connections to J2 or J3 while the on-board microphone
is used to preserve the performance of the microphone. A possibility that the gain adjustment can be needed in
the device depends on the microphone sensitivity.
2.3.2 TAx5x42 EVM Output Hardware Settings
The TAx5x42 evaluation module has several output configuration options and offers flexibility to allow the user to
evaluate the device with different load conditions and configurations. The different configurations are highlighted
in this section.
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2.3.2.1 TAx5x42 Analog Audio Output
The EVM analog audio output port provides option for AC/DC-Coupled, filter/filter-less path for easy evaluation.
By default the filter components are not populated.
Figure 2-9. TAC5242/TAC5142/TAD5242/TAD5142 EVM Output Architecture
OUT1 and OUT2 audio output pins have connection options with external load or the on-board load selections. A
pair of RCA connectors, white from OUTP and red from OUTM allow users to connect to external device either
as differential or single ended. Jumper header J36 or J37 needs to be populated if single-ended is desired or
removed otherwise for differential configuration.
Switch SW1 allows users to select respective load for each output pair for 16 Ohm, 604 Ohm or 10K Ohm if
needed. These resistors are for quick evaluation and can be bypassed for actual load. SW1 and the output RCA
connectors are located on the top left hand side shown in co below.
Table 2-2. SW1 Pin
SW1 pin Load Configuration Resistor Rating
1, 4, 7, 10 16 Ohm 0.5 W
2, 5, 8, 11 604 Ohm 0.125 W
3, 6, 9, 12 10 KOhm 0.4 W
Figure 2-10. TAC5242/TAC5142/TAD5242/TAD5142 Analog Output Connections
For TAA5242, OUT1 and OUT2 components are not populated.
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2.3.3 Multi-Function Hardware Configurations
These hardware-control device configurations are set through the Multi-Function Device Pins, MD0 to MD6
setting which is described in the following sections.
MD0
MD1
MD2
MD4
1
2
3
J71
1
2
3
J72
1
2
3
J74
IOVDD
IOVDD
IOVDD
GND
GND
GND
1 2
3 4
5 6
7 8
9 10
J70
TSW-105-07-G-D
GND GND
MD5
1
2
3
J75
IOVDD
GND
AVDD
22kR71
4.70kR70
AVDD
4.70kR72
AVDD
1 2
3 4
5 6
J73
TSW-103-08-G-D
CCLK
GND
IOVDD
MD3
Figure 2-11. Multi-Function Pin Setting
2.3.3.1 MD0 Hardware Configurations
MD0 sets the codec mode as well as the different audio format as shown in the table below for all the device
variants.
Table 2-3. MD0 Setting
Setting Audio Mode & Format
Short to AVDD Supply Controller I2S
Short to Ground Target I2S
Short to AVDD with 4.7KOhm Controller TDM
Short to AVDD with 22KOhm Target LJ
Short to Ground with 4.7KOhm Target TDM
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2.3.3.2 MD1 and MD2 Hardware Configurations
MD1 and MD2 settings provide the following configuration for these devices as shown in the table below.
Table 2-4. MD1 and MD2 Setting
MD1,MD2
TAC5242 TAC5142 TAA5242 (ADC only variant) TAD5242/TAD5142 (DAC
only variant)
Target Mode Controller
Mode Target Mode Controller Mode Target Mode Controller Mode Target Mode Controller Mode
2'b00
AVDD=3.3V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/256,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128Fs
(up to 96K),
BCLK=64Fs
for higher
Rates for
Controller
TDM
AVDD=3.3V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/256,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128Fs
(up to 96K),
BCLK=64Fs
for higher
Rates for
Controller
TDM
AVDD=3.3V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/256,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=256Fs(
up to 48K Fs),
BCLK=128Fs
(up to 96K),
BCLK=64Fs
for higher
Rates for
Controller
TDM
AVDD=3.3V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/256,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=256Fs(
up to 48K Fs),
BCLK=128Fs
(up to 96K),
BCLK=64Fs
for higher
Rates for
Controller
TDM
2'b01
AVDD=1.8V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/128,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128Fs
(up to 96K),
BCLK=64Fs
for higher
Rates for
Controller
TDM
AVDD=1.8V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/128,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128Fs
(up to 96K),
BCLK=64Fs
for higher
Rates for
Controller
TDM
AVDD=1.8V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/128,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=256Fs(
up to 48K Fs),
BCLK=128Fs
(up to 96K
Fs),
BCLK=64Fs
for higher
Rates for
Controller
TDM
AVDD=1.8V,
Word Length=
32, Linear
Phase
Decimation/
Interpolation
Frame Rate=
MCLK/128,
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=256Fs(
up to 48K Fs),
BCLK=128Fs
(up to 96K
Fs),
BCLK=64Fs
for higher
Rates for
Controller
TDM
2'b10
AVDD=3.3V,
Word Length=
24, Linear
Phase
Decimation/
Interpolation
Frame
Rate=96/88.2
KSPS Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128FS
for Controller
TDM
AVDD=3.3V,
Word Length=
24, Linear
Phase
Decimation/
Interpolation
Frame
Rate=96/88.2
KSPS Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128FS
for Controller
TDM
AVDD=3.3V,
Word Length=
24, Linear
Phase
Decimation/
Interpolation
Frame
Rate=96/88.2
KSPS Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128FS
for Controller
TDM
AVDD=3.3V,
Word Length=
24, Linear
Phase
Decimation/
Interpolation
Frame
Rate=96/88.2
KSPS Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128FS
for Controller
TDM
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Table 2-4. MD1 and MD2 Setting (continued)
MD1,MD2
TAC5242 TAC5142 TAA5242 (ADC only variant) TAD5242/TAD5142 (DAC
only variant)
Target Mode Controller
Mode Target Mode Controller Mode Target Mode Controller Mode Target Mode Controller Mode
2'b11
AVDD=3.3V,
Word Length=
16, Linear
Phase
Decimation/
Interpolation
Frame Rate =
48/44.1 KSPS
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128FS
for Controller
TDM
AVDD=3.3V,
Word Length=
16, Linear
Phase
Decimation/
Interpolation
Frame Rate =
48/44.1 KSPS
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=128FS
for Controller
TDM
AVDD=3.3V,
Word Length=
16, Linear
Phase
Decimation/
Interpolation
Frame Rate =
48/44.1 KSPS
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=256FS
for Controller
TDM
AVDD=3.3V,
Word Length=
16, Linear
Phase
Decimation/
Interpolation
Frame Rate =
48/44.1 KSPS
Word
Length=32,
BCLK=64Fs
for Controller
I2S,
BCLK=256FS
for Controller
TDM
2.3.3.3 MD3 Hardware Configurations
MD3 setting provides the following configuration for these devices as shown in the table below.
Table 2-5. MD3 Setting
MD3
TAC5242 TAC5142 TAA5242 (ADC only variant) TAD5242/TAD5142 (DAC
only variant)
Target Mode Controller
Mode Target Mode Controller Mode Target Mode Controller Mode Target Mode Controller Mode
1'b0
I2S/LJ Mode--
>
HPF=1Hz@48
KHz, Quick
Charge =50ms
TDM Mode-->
Slot 0 and 1 is
data,
HPF=1Hz@48
KHz and
Quick
Charge=50ms
MCLK Input,
HPF=1Hz@48
KHz, Quick
Charge=50ms
I2S/LJ Mode--
>
HPF=1Hz@48
KHz, Quick
Charge =50ms
TDM Mode-->
Slot 0 and 1 is
data,
HPF=1Hz@48
KHz and
Quick
Charge=50ms
MCLK Input,
HPF=1Hz@48
KHz, Quick
Charge=50ms
I2S/LJ Mode--
>
HPF=1Hz@48
KHz, Quick
Charge =50ms
TDM Mode-->
Daisy chain
disable,
HPF=1Hz@48
KHz and
Quick
Charge=50ms
MCLK Input,
HPF=1Hz@48
KHz, Quick
Charge=50ms
Output Quick
Charge
Enabled
MCLK Input
1'b1
I2S/LJ Mode --
>
HPF=12Hz@4
8KHz, Quick
Charge
=12.5ms TDM
Mode --> Slot
2 and 3 is
data,
HPF=1Hz@48
KHz and
Quick
Charge=50ms
MCLK Input,
HPF=1Hz@48
KHz, Quick
Charge=50ms
I2S/LJ Mode --
>
HPF=12Hz@4
8KHz, Quick
Charge
=12.5ms TDM
Mode --> Slot
2 and 3 is
data,
HPF=1Hz@48
KHz and
Quick
Charge=50ms
MCLK Input,
HPF=1Hz@48
KHz, Quick
Charge=50ms
I2S/LJ Mode --
>
HPF=12Hz@4
8KHz, Quick
Charge
=12.5ms TDM
Mode -->
Daisy chain
Enable,
HPF=1Hz@48
KHz and
Quick
Charge=50ms
MCLK Input,
HPF=1Hz@48
KHz, Quick
Charge=50ms
Output Quick
Charge
Disabled
MCLK Input
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2.3.3.4 MD4 and MD5 Hardware Configurations
MD4 and MD5 settings provide the following configuration for these devices as shown in the table below.
Table 2-6. MD4-MD5 Setting
MD4, MD5 TAC5242 TAC5142 TAA5242 (ADC only variant) TAD5242/TAD5142 (DAC
only variant)
Target/Controller Mode Target/Controller Mode Target/Controller Mode Target/Controller Mode
2'b00
ADC Diff(AC Coupled with 50
mV CM Tolerance), DAC Diff
LO (Highest Performance)
ADC Diff(AC Coupled with 50
mV CM Tolerance), DAC Diff
LO (Highest Performance)
ADC Diff(AC Coupled with 50
mV CM Tolerance)
DAC Diff LO (Highest
Performance)
2'b01
ADC Diff (AC/DC Coupled,
Rail to Rail CM Tolerance),
DAC Diff (High Drive Load)
ADC Diff (AC/DC Coupled,
Rail to Rail CM Tolerance),
DAC Diff (High Drive Load)
ADC Diff (AC/DC Coupled,
Rail to Rail CM Tolerance) DAC Diff (High Drive Load)
2'b10 ADC SE, DAC SE LO ADC SE, DAC SE LO ADC SE DAC SE LO
2'b11 ADC SE , DAC Pseudo Diff
HP
ADC SE , DAC Pseudo Diff
HP
ADC Diff (Low Power Mode,
AC/DC Coupled, Rail to Rail
CM Tolerance)
DAC Pseudo Diff HP
2.3.3.5 MD6 (DIN/DOUT) Hardware Configuration
MD6 is designated to either an ADC or a DAC variant device only through the DIN and DOUT configuration as
shown in the table below.
Connect DIN for ADC device to either GND or IOVDD to configure a stereo or mono ADC.
Connect DOUT for DAC device to either GND or IOVDD to configure a stereo or mono DAC.
For E1 EVM, the connection is made through blue-wire based on either an ADC or a DAC is populated on the
board.
Table 2-7. MD6 (DIN/DOUT)
ADC only variant (TAA5242/TAA5142) DAC only variant (TAD5242/TAD5142)
Function target mode Controller mode Function target mode Controller mode
DIN/DOUT
TDM mode--> DIN=DAISY_DIN
I2S/LJ mode-->
DIN=GND -> Stereo ADC
DIN=IOVDD -> Mono Left ADC
TDM mode-->DOUT=Daisy_DOUT
I2S/LJ mode-->
DOUT_IN=GND -> Stereo DAC
DOUT_IN=IOVDD -> Mono Left DAC
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3 Software
3.1 System Overview
Audio Input
Audio Output
Multi Function
Figure 3-1. System Overview
3.2 Configuration Example
Below is an example of configuring this hardware control device for record or playback.
Table 3-1. Configuration Example
Configuration MD0 MD1 MD2 MD3 MD4 MD5 MD6 (DIN/
DOUT)
Record
Path
(TAA5242)
Target I2S, 32-bit, DIFF
AC-coupled, STEREO GND GND GND GND GND GND DIN = GND
Playback
Path
(TAD5242)
Target I2S, 32-bit, DIFF
Line-Out, STEREO GND GND GND GND GND GND DOUT = GND
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4 Hardware Design Files
This section provides the schematics, layout example and bill of materials (BOM) for each TAx5x42 EVM variant.
4.1 Schematics
TAC5242 EVM Schematic
Figure 4-1. TAC5242 EVM Main DUT Schematic
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Figure 4-2. TAC5242 EVM Connectors and Supporting Circuitry Schematic
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TAC5142 EVM Schematic
Figure 4-3. TAC5142 EVM Main DUT Schematic
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Figure 4-4. TAC5142 EVM Connectors and Supporting Circuitry Schematic
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TAA5242 EVM Schematic
Figure 4-5. TAA5242 EVM Main DUT Schematic
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Figure 4-6. TAA5242 EVM Connectors and Supporting Circuitry Schematic
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