Texas Instruments ADS7809 User manual

1 Introduction
1.1 Features
User's GuideSLAU140 – November 2004
ADS78/8509 EVM User's Guide
Contents1 Introduction .......................................................................................... 12 Analog Interface .................................................................................... 23 Digital Interface ..................................................................................... 34 Power Supplies ..................................................................................... 35 EVM Operation ...................................................................................... 46 EVM Bill of Materials and Schematic ............................................................ 57 Related Documentation from Texas Instruments ............................................... 6
List of Tables
1 Pinout of the Analog Input Connector, J1 ....................................................... 22 Input Range Selection ............................................................................. 23 Pinout of J3 .......................................................................................... 34 Factory Default Jumper Locations ................................................................ 55 Bill of Materials ...................................................................................... 56 EVM Compatible Device Data Sheets, Users Guides and Additional Resources ......... 6
The ADS7809 and ADS8509 are complete 16-bit analog-to-digital (A/D) using state-of-the-art CMOSstructures. They contain a complete 16-bit, capacitor-based, successive approximation register (SAR) A/Dwith sample-and-hold, reference, clock, and a serial data interface. Data can be output using the internalclock or can be synchronized to an external data clock. The ADS7809 and ADS8509 also provide anoutput synchronization pulse for ease of use with standard DSP processors.
The EVM is available with either the ADS7809 or ADS8509 installed. The EVM can also accommodatethe 12-bit ADS7808 simply removing and replacing the installed device. Samples of the ADS7808 can beobtained through the sample program at Texas Instruments. See the ADS7808 Product Folder for details.
•Full-Featured Evaluation Board for the ADS7808, ADS7809 or ADS8509, serial Analog to DigitalConverters
•4 V, 5 V, 10 V, ±3.3 V, ±5 V and ±10 V Analog Input Ranges•Built in reference•High-Speed Serial Interface•Compatible with the 5-6K Interface Board for use with a variety of DSP Starter Kits as well as theHPA449 from SoftBaugh, Inc. (www.softbaugh.com).•Field Programmable Gate Array (FPGA) users can evaluate the ADS78/8509 EVM by obtaining theTexas Instruments Analog Adapter Kit from Avnet Design Services (www.em.avnet.com).
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2 Analog Interface
2.1 Analog Input Range Selection
2.2 Optional Amplifier Input
Analog Interface
For maximum flexibility, the ADS78/8509 EVM is designed for easy interfacing to multiple analog sources.Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient ten-pin dualrow header/socket combination at J1. This header/socket provides access to the analog input pins of theADC. Please consult Samtec at www.samtec.com or call 1-800-SAMTEC-9 for a variety of matingconnector options. Table 1 shows the pin out of the analog input connector, J1.
Table 1. Pinout of the Analog Input Connector, J1
Pin Number Signal Description
J1.2 thru Analog To accommodate EVM Stacking using the TAG feature of the data converter, jumper W12 can be usedJ1.16 (even) Input in combination with J1 to choose one of eight analog input channels to the evaluation module.J1.20 REF(+)J External reference source input, accessible through W6.J1.15 REFOUT Optional connection via W6. Provides external AFE circuitry with REFOUT bias voltage.J1.1- J1.19 AGND Analog ground connections. Note J1.15 is used for REFOUT connections to external AFE circuitry.(odd)
The analog front-end (AFE) circuitry found on the EVM consists of a simple RC filter. When used incombination with the 5-6K Interface Board, the circuits found on both DAP Signal Conditioning Boards(see SLAU105 ) provide the level shifting and amplifier configurations to realize single ended or bi-polarmode operation of the analog-to-digital converter installed on the EVM.
Jumpers W1 through W5 provide a convenient way to choose the analog input range. W1 controls theinput connection to pin 1 (R1IN), W2 controls the connection to pin 3 (R2IN) and W3 controls the inputs onpins 4 and 5 (R3IN and CAP). Jumpers W4 and W5 provide connections to 33.2K resistors wired to theCAP pin and TRIM adjustment pot R6 (via W5). Table 2 is representative of the input range selection.
Table 2. Input Range Selection
(1)
Range Without Trim With Trim
W1 W2 W3 W4 W5 W1 W2 W3 W4 W5
0–10 V 5–6 1–2 5–6 1–2 2–3 5–6 1–2 5–6 1–2 1–20–5 V 5–6 5–6 1–2 1–2 2–3 5–6 5–6 1–2 1–2 1–20–4 V 1–2 5–6 1–2 2–3 2–3 1–2 5–6 1–2 2–3 1–2±10 V 5–6 5–6 3–4 2–3 2–3 5–6 5–6 3–4 2–3 1–2±5 V 1–2 1–2 3–4 1–2 2–3 1–2 1–2 3–4 1–2 1–2±5 V 1–2 1–2 3–4 2–3 2–3 1–2 1–2 3–4 2–3 1–2
(1)
For Offset Adjustment, close W6 pins 5–6 and adjust R8 before trimming.
Jumper W7 provides access to an optional amplifier/buffer circuit on the front end of the data converter.Component U2 can be installed at the user's option with any standard 8 pin SOIC single amplifiercomponent. The amplifier circuit is connected to the ±VA terminals for split supply operation. If singlesupply amplifiers are used, the –VA (J3 pin 2) can be tied to analog ground (J3 pin 6). The footprint forcommon 4mm trim pots (see component R11) is provided as an offset adjustment pot for single supplyamplifiers. When used in conjunction with the 5-6K Interface Board, please be aware that the –VA supplyis common to all power connectors (JP1 through JP6). Shorting the –VA supply to ground on theADS78/8509 EVM is possible only if it is not used elsewhere on the interface board.
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3 Digital Interface
3.1 Using TAG Features via W8, W9, and W10
3.2 Additional Digital Control and Monitoring
4 Power Supplies
Digital Interface
The ADS78/8509 EVM is designed for easy interfacing to multiple control platforms. Jumper options areprovided on the EVM to allow direct control over the serial clock source as well as the data output andTAG features.
The active low CS0 pin is connected to J2 pin 1. This pin can be controlled through GPIO functions on the5–6K Interface Board or the HPA449. For standalone operation, a shunt jumper can be placed betweenJ2T pins 1 and 2 to tie CS to ground.
The DATA output from the EVM is applied to W9. When the supplied shunt is on pins 1-2 (default state),the DATA output is fed to J2B (bottom side) pin 11. This is required when operating in the internal dataclock mode, where the ADC supplies an SPI master clock to the host processor. Data is input to the SIMOpin of the host in this case. W13 is provided as a means to return the ADC generated SPI clock to DSPhost processors using the 5-6K Interface Board.
W8 controls the TAG function of the ADC. With the supplied shunt in position 1-2 (default state), TAG isgrounded and the EVM is to be considered as either the only converter in the system, or the LASTconverter in the data chain (see SBAA007 for additional details). When the shunt on W8 is moved toposition 2–3, data input to the TAG pin is fed from J2T (top side) pin 13. W8 and W9 must be in position1-2 for the last converter in the chain and position 2–3 for all other devices when using the TAG feature.The TAG feature also requires the use of an external data clock. W10 sets the EXT/INT pin high (externalclock) when the pins are open (no shunt installed). The external data clock can be applied to J2 pin 3 (topor bottom side).
As mentioned previously, W10 controls the selection of the internal or external data clock. When W10 isclosed (default) the ADC generates a low dwelling burst mode clock that allows the user to read valid dataon either the rising or falling edge. Removing the shunt from W10 requires an external data clock appliedto J2 pin 3 (top or bottom side) to produce a data output stream. W11 controls the data format; whenclosed (default) the DATA output pin provides a Binary Twos Complement data stream. Opening W11provides a straight binary output of the conversion results. W14 controls the device power down function.Opening W14 applies a logic high to the PWRD pin, shutting down the ADC. W14 can be wired to GPIOoutput J2 pin 19 for use with the HPA449 board.
Test points TP4 and TP6 provide access to the SYNC and BUSY signals respectively. These can bemonitored by referencing an oscilloscope to TP5, digital ground (labeled DGND). The applied digitalvoltage can be monitored at TP3. Analog signals and the applied VANA voltage can be monitored at TP2(+5V) referenced to TP1 (AGND).
The ADS78/8509 EVM board requires +5V DC for both the analog and digital sections of the ADC. Powerto the ADC is sourced from J3 pin 3 and pin 10 (+5VA and +5VD - see table below).
Note:
VDIG must be less than or equal to VANA.
The following table shows the pin out of J3:
Table 3. Pinout of J3
Signal Pin Number Signal
+VA 1 2 -VA
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4.1 Reference Voltage control via W6
5 EVM Operation
EVM Operation
Table 3. Pinout of J3 (continued)
Signal Pin Number Signal
+5VA 3 4 UnusedDGND 5 6 AGNDUnused 7 8 UnusedUnused 9 10 +5VD
For stand alone operation, power sources can be applied via various test points located on the EVM(VANA to TP2 and VDIG to TP3). Refer to the schematic at the end of this document for details.
The option amplifier located at position U2 (user supplied) can be powered through J3 pins 1 and 2. Seethe earlier discussion about the power supply restrictions in section 1.2 of this manual.
Note:
While filters are provided for all power supply inputs, optimal performance of the EVMrequires a clean, well-regulated power source.
The ADS78/8509 is normally configured to use its internal reference. Jumper W6 provides various optionsto allow the EVM user to send the converter's reference voltage off board to external amplifier circuits (W6pins 3-4, default state). An external reference sourceapplied to J1 pin 20 can be sent to the ADC bymoving the shunt at W6 to pins 1-2. An on board trim pot is provided at R8, and can be used with a shuntjumper placed on W6 pins 5–6.
The max analog input swing is +/-10Vpp. The input range can be adjusted directly on the EVM byconfiguring jumpers W1 through W5, with offset trim capability using W6. The EVM is set for the 0-10Vinput range by default with the serial data stream supplied by the internal clock. Offset trim can beaccomplished on board via R8 or through an external input through J1. Single amplifier U2 in an industrystandard SOIC 8 package can be installed to do on board signal conditioning if necessary. Please refer toSection 12 of Op Amps for Everyone (Doc. No. SLOD006) for information on various circuit applications.
Once power is applied to the EVM, the analog input source can be connected directly to J1 (top or bottomside) or through optional amplifier and signal conditioning modules using the 5-6K Interface Board orHPA449. Jumper W12 allows the EVM user to choose which analog signal applied to J1 is directed to theinput of the ADC, providing the ability to stack up to eight ADS78/8509 EVM's using the TAG features ofthe device. When using the TAG feature, be sure to set the jumpers according to section 2.1 of this UsersGuide.
The digital control signals can be applied directly to J2 (top or bottom side). The ADS78/8509 EVM canalso be connected directly to the 5-6K Interface Board for use with a variety of C5000 and C6000 seriesDSP Starter Kits (DSK). The analog and digital input connectors are designed to allow pattern generatorsand/or logic analyzers to be connected to the EVM using standard ribbon type cables on 0.1" centers.
No specific evaluation software is provided with this EVM, however, various code examples are availablethat show how to use this EVM with a variety of digital signal processors from Texas InstrumentsIncorporated. Check the product folders or send e-mail to [email protected] for a listing ofavailable code examples. The EVM Gerber files are available on request.
Table 4 shows the factory default jumper locations for the ADS78/8509 EVM:
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6 EVM Bill of Materials and Schematic
EVM Bill of Materials and Schematic
Table 4. Factory Default Jumper Locations
Jumper Function Default Condition
W1 Controls application of the applied analog signal to R1IN 5–6W2 Controls application of the applied analog signal to R2IN 1–2W3 Controls application of the applied analog signal to R3IN 5–6W4 Controls connection of 33.2 k Ωresistors to the CAP pin and TRIM pot 1–2W5 Controls connection of 33.2 k Ωresistors to the CAP pin and TRIM pot 2–3W6 Controls the application of the reference voltage 3–4W7 Controls the application of optional signal conditioning circuitry 1–2W8 Controls the TAG feature 1–2W9 Controls the application of the DOUT data stream 1–2W10 Controls the EXT/INT clock pin CLOSEDW11 Controls the SB/BTC data format pin CLOSEDW12 Used to select an analog input channel when used with DAP Signal Conditioning Boards 1–2W13 Controls the application of clock return for DSP receiver operations CLOSEDW14 Controls the PWRD function CLOSED
Table 5 contains a complete Bill of Materials for the ADS78/8509EVM. The schematic diagram is alsoprovided for reference.
Table 5. Bill of Materials
Designators Description Manufacturer Mfg. Part Number
C1 2.2 nF, 0805, X7R, 50V Panasonic ECJ-2VB1H222KC2 C9 2.2 µF, 0805, X5R, 10V TDK C2012X5R1A225K/0.85C3 C4 10 µF 0805, X5R, 10V Murata GRM21BR61A106KE19LC5 C7 10 µF Tant., A case, 10V Panasonic ECS-T1AY106RC6 C12 0.1µF, X7R, 25V TDK C2012X7R1E104KC8 C10 C11 C13 0.01 µF, X7R, 25V Panasonic ECJ-2VB1H103KJ1 J2 (top side) 10 pin, dual row, SMTheader Samtec TSM-110-01-T-DV-P(20 pos.)J1 J2 (bottom side) 10 pin, dual row, SMT socket Samtec SSW-110-22-F-D-VS-K(20 pos.)J3 (top side) 5 pin, dual row, SMT header Samtec TSM-105-01-T-DV-P(10 Pos.)J3 (bottom side) 5 pin, dual row, SMT socket Samtec SSW-105-22-F-D-VS-K(10 Pos.)L1 L2 15 µH inductor, SMT, 1608 Inductors, Inc. CTDS1608C-153seriesR1 R4 100 Ω, 0805, 1% Yageo America 9C08052A1000FKHFTR2 576 k Ω, 0805, 1% Yageo America 9C08052A5763FKHFTR3 R5 33.2 k Ω, 0805, 1% Yageo America 9C08052A3322FKHFTR6 R8 50 k Ω, SMT Trim Pot, 4mm Bourns 3214W-1-503ER7 200 Ω, 0805, 1% Yageo America 9C08052A1002JLHFTR12 R13 R14 10 k Ω, 0805, 5% Yageo America 9C08052A1002JLHFTR15 33 Ω, 0805, 5% Yageo America 9C08052A33R0JLHFTR9 0 Ω, 0805, 5% Yageo America 9C08052A0R00JLHFTR10, R11, R16, R17 Not Installed
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7 Related Documentation from Texas Instruments
Related Documentation from Texas Instruments
Table 5. Bill of Materials (continued)
Designators Description Manufacturer Mfg. Part Number
TP2 TP3 Red test point loop Keystone 5000TP1 TP5 TP4 TP6 Black test point loop Keystone 5001U1 ADS7809 or ADS8509 TI ADS7809U or ADS8509UU2 Not Installed TI Single Op Amp - SOICW1 W2 W3 W6 3 pin, dual row, TH header (6 Samtec TSW-103-07-L-Dpos.)W4 W5 W7 W8 W9 3 pin , 0.1" header Samtec TSW-103-07-L-SW10 W11 W13 W14 2 pin , 0.1" header Samtec TSW-102-07-L-SW12 8 pin , dual row, 2mm header Samtec TMM-108-02-L-D(16 pos)
Table 6. EVM Compatible Device Data Sheets, Users Guides and Additional Resources
Data Sheet Literature Number
ADS7808 SBAS018ADS7809 SBAS017ADS8509 SLAS324
Users Guides Literatuare Number
5-6K Interface Board SLAU104DAP Signal Conditioning Boards SLAU105
Additional Resources Literature Number
Op Amps for Everyone SLOD006ADS7809 TAG Features SBAA007
ADS78/8509 EVM User's Guide6 SLAU140 – November 2004

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12500 TI Blvd. Dallas, Texas 75243
Title:
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SIZE: DATE: REV:
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Revision History
REV ECN Number Approved
Drawn By:
Engineer:
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11 12
13 14
15 16
17 18
19 20
J1 12
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11 12
13 14
15 16
17 18
19 20
J2B
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J3
+5VA
EXT_REFIN
TP3
TP2
TP1
L2
15uF
5Vd
AGNDDGND
Tom Hendrick
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ADS7809/8509 Evaluation Module
Schematic
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11EDGE #6465121
1 Prototype TH
+
C7
L1
15uH
+
C5
5Va
R1IN
1
R2IN
3
R3IN
4
REF
6
CAP
5
SB/BTC 8
EXT/INT 9
AGND1
2
AGND2
7DGND 10
/BUSY 17
Vana
19
PWRD 18
/CS 16
DATACLK 12
SYNC 11
DATA 13
R/C 15
TAG 14
VDIG 20
U1
REFOUT
W8
W10
R12
10K
5Vd
W11
R13
10K
5Vd
W14
R14
10K
5Vd
+5VD
C12
0.1uF
C2
2.2uF
C13
0.01uF
5Va
C8
0.01uF
C6
0.1uF
5Vd
C9
2.2uF
R4
100 ohm
R7
200 ohm
W4
R5
33.2K
R3
33.2K
R8
50K
C4
10uF
5Va R2
576K
ADJ_REFIN
R6
50K
C3
10uF
5Va
W5
W1
W2
W3
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11 12
13 14
15 16
W12
W7
EVM_IN_0
EVM_IN_1
EVM_IN_2
EVM_IN_3
EVM_IN_4
EVM_IN_5
EVM_IN_6
EVM_IN_7
EVM_IN_0
EVM_IN_1
EVM_IN_2
EVM_IN_3
EVM_IN_4
EVM_IN_5
EVM_IN_6
EVM_IN_7
ADC_ANALOG_IN
C1
2.2nF
R1
100 ohm
+VA
-VA
+VA -VA
R11
C10
10nF
C11
10nF
R9
0 Ohm
12
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13 14
15 16
17 18
19 20
J2T
/CS
/CS
/CS
SCLK
SCLK
SCLK
CLKR
FSX
FSX
FSX
FSRFSR
DATA /INT
/INT
TOUT
TOUT
GPIO
GPIO
TAG
TAG
W13
CLKR
R15
33
W9
SIMO SIMO
DR
DR
TP4
TP6
Operating Modes:
Internal Clock(SPI Master)-W10 Closed, W81-2, W91-2
External Clock(No TAG) -W10 Open, W81-2, W92-3
External Clock(W/ TAG) -W10 Open, W82-3 (1-2Last Board), W92-3
RANGE W/O TRIM W/TRIM
0-10V
0-5V
0-4V
+/-10V
+/-5V
+/-3V
W1 W2 W3 W4 W5 W1 W2 W3 W4 W5
5-6 1-2 5-6 1-2 2-3 5-6 1-2 5-6 1-2 1-2
5-6 5-6 1-2 1-2 2-3 5-6 5-6 1-2 1-2 1-2
1-2 5-6 1-2 2-3 2-3 1-2 5-6 1-2 2-3 1-2
1-2 5-6 3-4 2-3 1-21-2 5-6 3-4 2-3 2-3
5-6 1-2 3-4 1-2 2-3 5-6 1-2 3-4 1-2 1-2
1-2 1-2 3-4 2-3 1-21-2 1-2 3-4 2-3 2-3
FOR OFFSET ADJUST, MOVE W6 to position 5-6
3
2
6
7
4
U2
R16
R17
R10
+VA
TP5
W6
A Initial Release TH

FCC Warnings
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequencyenergy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules,which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in otherenvironments may cause interference with radio communications, in which case the user at his own expense will be required totake whatever measures may be required to correct this interference.
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLYand is not considered by TI to be fit for commercial use. As such, the goods being provided may not be complete in terms ofrequired design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typicallyfound in the end product incorporating the goods. As a prototype, this product does not fall within the scope of the European Uniondirective on electromagnetic compatibility and therefore may not meet the technical requirements of the directive.Should this evaluation kit not meet the specifications indicated in the EVM User's Guide, the kit may be returned within 30 daysfrom the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLERTO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANYWARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from allclaims arising from the handling or use of the goods. Please be aware that the products received may not be regulatory compliantor agency certified (FCC, UL, CE, etc.). Due to the open construction of the product, it is the user's responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE Liable to the other FORANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.TI assumes no liability for applications assistance, customer product design, software performance, or infringement ofpatents or services described herein.
Please read the EVM User's Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM User's Guide prior tohandling the product. This notice contains important safety information about temperatures and voltages. For further safetyconcerns, please contact the TI application engineer.Persons handling the product must have electronics training and observe good laboratory practice standards.No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.

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Related Documentation from Texas Instruments
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 V to 15 V and the output voltage range of 0 V to 5 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there arequestions concerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to theEVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the loadspecification, please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 30 C. The EVM is designed tooperate properly with certain components above 60 C as long as the input and output ranges are maintained. These componentsinclude but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types ofdevices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes nearthese devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2004, Texas Instruments Incorporated
ADS78/8509 EVM User's Guide8 SLAU140 – November 2004

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