Texas Instruments DAC5686 EVM User manual

DAC5686 EVM
User's Guide
March 2007 Wireless Infrastructure Products
SLWU006E

2 SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

Contents
1 Overview .................................................................................................................... 51.1 Purpose............................................................................................................ 51.2 EVM Basic Functions ............................................................................................ 51.3 Power Requirements ............................................................................................ 51.4 Software Installation ............................................................................................. 61.5 Hardware Configuration ......................................................................................... 62 DAC5686 EVM Operational Procedure ........................................................................... 72.1 Starting the Serial Interface Program ........................................................................ 102.2 DAC5686 EVM Initial Setup Tests ........................................................................... 112.3 DAC5686 GUI Register Descriptions ........................................................................ 133 Physical Description .................................................................................................. 153.1 PCB Layout ...................................................................................................... 153.2 Parts List ......................................................................................................... 194 Circuit Description ..................................................................................................... 214.1 Input Clocks ..................................................................................................... 214.2 Input Data ........................................................................................................ 214.3 Output Data ..................................................................................................... 224.4 Control Inputs ................................................................................................... 234.5 Internal Reference Operation ................................................................................. 244.6 External Reference Operation ................................................................................ 245 Schematic ................................................................................................................ 25
Important Notices ............................................................................................................... 31
SLWU006E – December 2004 – Revised March 2007 Table of Contents 3Submit Documentation Feedback

List of Figures
1 Serial Interface GUI ........................................................................................................ 102 DAC5686 Setup for X4 Interpolation, Single Sideband Mode and Tone at Fdac/4 ............................... 113 Spectrum with CLK2 = 500 MHz, X4 Interpolation, Single Sideband Mode, NCO Off ............................ 124 Spectrum with CLK2 = 320 MHz, X4 Interpolation, Single Sideband Mode and NCO Frequency =536870912 .................................................................................................................. 135 Top Layer 1 ................................................................................................................. 166 Layer 2, Ground Plane .................................................................................................... 177 Layer 3, Power Plane ...................................................................................................... 188 Bottom Layer ................................................................................................................ 199 Schematic - Page 1 ........................................................................................................ 2610 Schematic - Page 2 ........................................................................................................ 2711 Schematic - Page 3 ........................................................................................................ 2812 Schematic - Page 4 ........................................................................................................ 2913 Schematic - Page 5 ........................................................................................................ 30
4List of Figures SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

1 Overview
1.1 Purpose
1.2 EVM Basic Functions
1.3 Power Requirements
1.3.1 Voltage Limits
User's GuideSLWU006E – December 2004 – Revised March 2007
DAC5686 EVM
This user's guide document gives a general overview of the DAC5686 evaluation module (EVM) andprovides a general description of the features and functions to be considered while using this module.
The DAC5686 EVM provides a platform for evaluating the DAC5686 digital-to-analog converter (DAC)under various signal, reference, and supply conditions. This document should be used in combination withthe EVM schematic diagram supplied.
Digital inputs to the DAC can be provided with CMOS level signals up to 160 MSPS through two 34-pinheaders. This enables the user to provide high-speed digital data to the DAC5686 device.
The analog outputs from the DAC are available via SMA connectors. Because of its flexible design theanalog output of the DAC5686 device can be configured to drive a doubly terminated 50- Ωcable using a4:1 or 1:1 impedance ratio transformer, or single-ended referred to AVDD.
The EVM allows for different clock configurations. The user can input a single-ended, differentialECL/PECL or TTL/CMOS level signal, to be used to generate a single-ended or differential clock source.See Section 4.1 for proper configuration and operation.
Power connections to the EVM are via banana jack sockets.
In addition to the internal bandgap reference provided by the DAC5686 device, options on the EVM allowan external reference to be provided to the DAC.
The DAC5686 EVM allows the user to program the DAC5686 internal registers with the supplied computerparallel port cable and serial interface software. The interface allows read and write access to all registersthat define the operation mode of the DAC5686 device.
The demonstration board requires a minimum of two power supplies. For non-PLL and 3.3-V I/Ooperation, connect 3.3 Vdc to banana jack J7 with the return connected to J9. Connect 1.8 Vdc to bananajack J8 and the return to J10. Jumper W2 selects the digital I/O voltage level and jumper W3 enables thePLL.
Exceeding the maximum input voltages can damage EVM components. Undervoltage may causeimproper operation of some or all of the EVM components.
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 5Submit Documentation Feedback

www.ti.com
1.4 Software Installation
1.5 Hardware Configuration
Overview
All necessary software to operate the serial interface is provided on the enclosed CD-ROM.1. Insert the CD-ROM into the computer to be used to operate the serial interface.2. Unzip the contents of the DAC5686SPI_Installv1p1.zip into the C:\temp directory on the PC.3. Run the file called setup.exe in the C:\temp\Installer directory.4. The software will install the appropriate files to the C:\Program Files\TI.fdr directory.5. Once the installation is complete, the computer should be rebooted. The software is launched byrunning
C:\ProgramFiles\TI.fdr\DAC5686_SPI\DAC5686_SPI.exe.
A shortcut for that program can be created and placed on the desktop or any other relevant location. SeeSection 2 ,DAC5686 EVM Operational Procedure, for instructions on operating the serial interfacesoftware.
The DAC5686 EVM can be set up in a variety of configurations to accommodate a specific mode ofoperation. Before starting evaluation, the user should decide on the configuration and make theappropriate connections or changes. The demonstration board comes with the following factory-setconfiguration:
•Differential clock mode using transformers T3 and T4. Input single-ended clocks are required at J3 andJ4.•Transformer-coupled outputs using transformers T1 and T2.•The converter is set to operate with internal reference. Jumper W1 is installed between pins 2 and 3.•Full-scale output current set to 20 mA through RBIAS resistor R1.•The DAC5686 output is enabled (sleep mode disabled).•TXENABLE is set high to enable the DAC5686 device to process data.•Internal PLL disabled. Jumper W3 is installed between pins 2 and 3.•Input data level is set to +3.3VDC. Jumper W2 is installed between pins 1 and 2.
To prepare the DAC5686 EVM for evaluation, connect the following:1. 3.3 V to J7 and the return to J9.2. 1.8 V to J8 and the return to J10.3. Provide a single-ended, 300-mV
PP
, 0-V offset sine-wave signal to SMA connector J3 (CLK1) if theinternal PLL is to be used. Connect this signal to SMA connector J4 (CLK2) if the PLL is disabled. Asecond sine-wave source is required only for dual clock mode. In this mode, the signal on CLK1 isused to clock data into the DAC5686 and the signal on CLK2 is used to clock the internal DAC. CLK1and CLK2 must be phase-aligned for this option to work properly. In order to preserve the specifiedperformance of the DAC5686 converter, the clock sources must feature very low jitter. Using a clockwith a 50% duty cycle gives optimum dynamic performance.4. Use a digital test pattern generator with 50- Ωoutputs to provide 3.3-V CMOS logic level inputs toconnectors J13 and J14. Adjust the digital inputs to provide the proper setup and hold times at theDAC5686 inputs. See the DAC5686 data sheet (SLWS147 ) for timing information.5. Connect one end of the supplied serial interface cable to the parallel port of a PC. Connect the otherend of the cable to J1 on the EVM.6. The DAC5686 outputs can be monitored using SMA connector J5 for IOUTA and SMA connector J19for IOUTB.
DAC5686 EVM6 SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

www.ti.com
2 DAC5686 EVM Operational Procedure
DAC5686 EVM Operational Procedure
This chapter describes the serial interface GUI.
To prepare the DAC5686 EVM for operation, follow these steps:1. Parallel Port Interface: Connect one end of the supplied serial interface cable to the parallel port of aPC and the other end of the cable to J1 on the EVM and skip steps 2 to 7.2. USB Interface: Connect the provided USB to SPI adapter board to the parallel port connector on theEVM and to a spare USB port on the host PC using the supplied USB cable. The Windows Found NewHardware Wizard should open; if this is not the case make sure the cable is connected properly. Select“No, not this time” from the options available and then click “Next” to proceed with the installation.
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 7Submit Documentation Feedback

www.ti.com
DAC5686 EVM Operational Procedure
3. Select "Install the software automatically (recommended)" as shown below and then click "Next".
4. If Windows is not able to find the appropriate USB drivers press “Back” and select “Install from a list orspecific location (advanced)”. Click “Next”.5. Select "Search for the best driver in these locations" and browse for the folder where the DAC5686program was installed (the default location is C:\Program Files\Texas Instruments\DAC5686). Once thefile path has been selected, click “Next” to proceed.
8DAC5686 EVM SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

www.ti.com
DAC5686 EVM Operational Procedure
6. If Windows XP is configured to warn when unsigned (non-WHQL certified) drivers are about to beinstalled, the following screen is displayed unless installing a Microsoft WHQL certified driver. Click on"Continue Anyway" to continue with the installation. If Windows XP is configured to ignore file signaturewarnings, no message will appear.
7. Windows should then display a message indicating that the installation was successful. Click "Finish"to complete the installation.
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 9Submit Documentation Feedback

www.ti.com
2.1 Starting the Serial Interface Program
DAC5686 EVM Operational Procedure
Power up the EVM. After power up, depress switch S1 to reset the DAC5686. Start the software byrunning DAC5686_SPI.exe. If the EVM is powered on with the parallel port connected properly, then theGUI shown in Figure 1 is displayed with the default settings read from the device. If there is a problemwith the communication, such as the EVM is not powered on or the parallel port cable is not connected, anerror message will be displayed instructing the user to correct the problem. Once corrected, hit the ReadAll button to read the default settings of the device.
For normal operation, the user needs only to select values and switches as desired. The values areautomatically sent to the device and read back to verify their configuration.
Figure 1. Serial Interface GUI
DAC5686 EVM10 SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

www.ti.com
2.2 DAC5686 EVM Initial Setup Tests
DAC5686 EVM Operational Procedure
There are several initial tests with the DAC5686 that can be done without any input data. The followingsetup steps are suggested to familiarize the user with the DAC5686 and EVM software and verify that theDAC5686 is functioning properly.1. Provide a CLK2 input and disable the internal PLL (W3 between pins 2 and 3). Do not provide parallelinput data.2. Power up the EVM with 1.8 V DVDD and 3.3 V AVDD3. Start the DAC5686_SPI software.4. Turn "Full Bypass" off, change Interpolation to "x4", set Mode to "Single Sideband" and the CoarseGain for both DACs to 15. The GUI should now look as shown in Figure 2 .
Figure 2. DAC5686 Setup for X4 Interpolation, Single Sideband Mode and Tone at Fdac/4
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 11Submit Documentation Feedback

www.ti.com
Ref 10 dBm Att 35 dB
*
*
1AP
CLRWR
A
RBW 3 kHz
VBW 10 kHz
SWT 28 s
Center 125 MHz Span 250 MH z
25 M
*
Hz/
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10 1
Marker 1 [T1 ]
4. 56 d Bm
12 5.0000000 00 M Hz
DAC5686 EVM Operational Procedure
A tone at a frequency of CLK2/4 should now be present at connectors J5 (IOUTA) and J19 (IOUTB). Inthe case of CLK2 = 500 MHz, the output spectrum should be similar to Figure 3 , with a tone at 125MHz.
This tone is being generated by the DAC5686 Fdac/4 Coarse Mixer as with no input data provided toconnectors J13 and J14, the Channel A and B data bus inputs will all be zeros, or a full scale negativevalue in the default offset binary format.
Figure 3. Spectrum with CLK2 = 500 MHz, X4 Interpolation, Single Sideband Mode, NCO Off
12 DAC5686 EVM SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

www.ti.com
Ref 10 dBm Att 35 dB
*
*
1AP
CLRWR
A
RBW 3 kHz
VBW 10 kHz
SWT 18 s
Center 80 MHz Span 160 MH z
16 M
*
Hz/
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10 1
Marker 1 [T1 ]
2. 71 d Bm
4 0.0000000 00 M Hz
2.3 DAC5686 GUI Register Descriptions
2.3.1 Register Controls
DAC5686 EVM Operational Procedure
5. Reduce the CLK2 frequency to less than 320MHz. Enable the NCO and change the NCO DDS to536870912. Doing this will generate a tone at Fdac/8. For CLK2 = 320 MHz, the tone corresponds to40 MHz. The output spectrum should be similar to the one in Figure 4 .
Figure 4. Spectrum with CLK2 = 320 MHz, X4 Interpolation, Single Sideband Mode and NCO Frequency =536870912
6. Changing the NCO DDS to 268435456 (232 ? 20/320) will now result at an output tone at 20 MHz.
The following section provides a brief description of each control:
•Load Regs: Loads register values from a saved file to the DAC5686 and updates the GUI.•Save Regs: Saves current GUI registers settings to a text file for future use.•Read All: Reads the current registers of the DAC5686. This is used to verify settings on the frontpanel.
•Send All: Sends the current front panel registers to the device. This is generally only used when theEVM power has recycled or the device has been reset and the user wants to load the displayedsettings to the device.
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 13Submit Documentation Feedback

www.ti.com
2.3.2 Configuration Controls
DAC5686 EVM Operational Procedure
•Full Bypass: When set, all interpolation and NCO functions are bypassed. User can only useCLK2/CLK2C inputs in this mode.•Counter: Uses an input counter ramp as the input data to the DAC. See the DAC5686 data sheet formore information.
•2's Comp: When set, input data is interpreted as 2's complement. When cleared, input data isinterpreted as offset binary.•Sync_Phstr: Enables the PHSTR input as a sync input to the clock dividers in external single clockmode. For example, in external single clock mode (PLLVDD = 0), with 16x interpolation, theCLK2/CLK2C signal is divided by 16 and output on the PLLLOCK pin. If this bit is set, a rising edge onthe PHSTR pin will be sampled by the CLK2/CLK2C clock, and used to restart the divide by 16 circuit.•Dither: Enables dithering in the PLL.•Rev B Bus: When cleared, DB input data MSB to LSB order is DB(15)= MSB and DB(0)=LSB. Whenset, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.•qflag: Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator wheninterleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timingrelationship.
•Rev. Spect: When asserted the sin term is negated before being used in mixing. This gives thereverse spectrum in single sideband mode.•Interleave: When set, interleaved input data mode is enabled; both A and B data streams are input atthe DA(15:0) input pins. The TXENABLE or QFLAG pin is used to identify the I/Q sequence dependingon the value the "Qflag Interleave" bit (see the following)•Inverse Sinc: Enables inverse sinc correction filter.•Dual Clk: Only used when the PLL is disabled. When set, two differential clocks are used to input thedata to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is usedas the DAC sample clock.•NCO: When set, enables NCO in Single Sideband or Quad Mod modes. The NCO is operational up to350 MHz DAC update clock. When cleared, Single Sideband and Quad Mod modes use a fixed fs/4mix frequency.
•Sif: Sets sif_4pin bit. The 4 pin serial interface mode is enabled when on, 3 pin mode when off. TheDAC5686 EVM is configured for a 3 pin serial interface, so setting to a 4 bit serial interface makesreading registers impossible with the GUI.•Single Sideband: When set, the data to DACB is inverted to generate upper side band output.•Mode: Used to select the DAC mixer mode.– Dual DAC - runs the device in dual DAC mode; no mixing between the A and B datapaths.– Quad Mod - runs the device as a quadrature modulator. The DACA circuit is shut off and the outputis on the DACB outputs.– Single Sideband - The device generates a hilbert transform pair on the DACA and DACB outputssuitable for connection to an analog quadrature modulator.•PLL Divider: Sets PLL VCO divider to div by 1, 2, 4, or 8. Only valid when the PLL is enabled byproviding +3.3 V to PLLVDD (W3 between pins 1 and 2). The VCO works best (low phase noise) whenbiased in the 250 to 500 MHz range. If the device is to be run with a DAC update rate below 250 MHz,set the PLL divider to 2. This allows the user to run the VCO at the 250 to 500 MHz range since theoutput is divided by 2.•Interpolation: Sets FIR Interpolation factor: {×2, ×4, ×8, ×16}.•Gain Dig/Analog: Sets the gain of the DDS to ensure that the overall gain is less than or equal to 1(i.e. no clipping). See the DAC5686 data sheet for more information.•PLLVCO Boost: Increases the Vtol current of the PLL VCO from nominal to 45% in 15% increments.
DAC5686 EVM14 SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

www.ti.com
2.3.3 DAC A(B) Gain
2.3.4 NCO
2.3.5 Additional Control/Monitor Registers
3 Physical Description
3.1 PCB Layout
3.1.1 PCB Layout Recommendations
Physical Description
•DAC Coarse Gain: Sets coarse gain of DAC A(B) full scale current. Range is 0 to 15. See theDAC5686 data sheet for full scale gain equation.•DAC Fine Gain: Sets fine gain of DAC A(B) full scale current. Range is -128 to 127. See the DAC5686data sheet for full scale gain equation.•DAC DCOffset: Sets DAC A(B) DC offset register. Range is -1024 to 1023.•Sleep: DAC A(B) sleeps when set, operational when cleared.
•NCO DDS: Sets NCO DDS registers. See the DAC5686 data sheet for the formula.•NCO Phase: Sets initial NCO phase registers. See the DAC5686 data sheet for more information.
•Pll Port Config: Selection of this button will bring up a separate window that shows the parallel portconfiguration of the software. The EVMMenu should be loaded with "DAC EVM".•Quit: Quits the operation of the DAC5686 software.•Version: Displays the version of the silicon. If a version of 0 is read then the communication is notfunctioning and an error message will be displayed.
This chapter describes the physical characteristics and PCB layout of the EVM and lists the componentsused on the module.
The EVM is constructed on a 4-layer, 6.5-inch x 4.7-inch, 0.055-inch thick PCB using FR-4 material.Figure 5 through Figure 8 show the PCB layout for the EVM.
The DAC5686 clock is sensitive to fast transitions of input data on pins 34, 35, and 36 (DA15, DA14, andDA13) due to coupling to DVDD pin 32. The noise-like spectral energy of the data line couples into theDAC clock circuit power pin, resulting in increased jitter. To minimize the jitter, a 10- Ωseries resistor alongwith a 10-pF capacitor to ground has been added to DVDD pin 32 on the EVM. Pin 32 only draws around2 mA of current and the 0.02-V voltage drop across the resistor is acceptable for DVDD voltages withinthe MINIMUM and MAXIMUM specifications. It is also recommended that the transition rate of the datainput lines be slowed by inserting series resistors near the data source. The optimized value of the seriesresistor depends on the capacitance of the trace between the series resistor and the DAC5686 input pin.For a 2-3 inch trace, a 22- Ωto 47- Ωresistor are recommended.
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 15Submit Documentation Feedback

www.ti.com
Physical Description
Figure 5. Top Layer 1
16 DAC5686 EVM SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

www.ti.com
Physical Description
Figure 6. Layer 2, Ground Plane
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 17Submit Documentation Feedback

www.ti.com
Physical Description
Figure 7. Layer 3, Power Plane
18 DAC5686 EVM SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback

www.ti.com
3.2 Parts List
Physical Description
Figure 8. Bottom Layer
Table 1 lists the parts used in constructing the EVM.
SLWU006E – December 2004 – Revised March 2007 DAC5686 EVM 19Submit Documentation Feedback

www.ti.com
Physical Description
Table 1. DAC5686 EVM Parts List
Bill Of Material For DAC5686
Value QTY Part Number Vendor Ref Des Not Installed
CAPACITORS
47 µF, tantalum, 20%, 10 V 6 ECS-T1AD476R Panasonic C53–C5810 µF, 10 V, 20% capacitor 12 ECS-T1AX106R Panasonic C24, C26–C28, C30–C32,C35, C37–C39, C411µF, 16 V, 10% capacitor 6 ECJ-3YB1C105K Panasonic C36, C42–C460.1 µF, 16 V, 10% capacitor 1 ECJ-2VB1C104K Panasonic C210.01 µF, 50 V, 10% capacitor 6 ECJ-2VB1H103K Panasonic C47-C52120 pf, 50 V, 5% Capacitor 1 ECJ-1VC1H121J Panasonic C330.01 µF, 16 V, 10% capacitor 2 ECJ-1VB1C103K Panasonic C19, C200.1 µF, 16 V, 10% capacitor 3 ECJ-1VB1C104K Panasonic C25, C60, C610.1 µF, 16 V, +80%, -20% capacitor 21 ECJ-0EF1C104Z Panasonic C1, C2, C4–C13,
C15–C18, C29, C59,C84–C8610 pF, 50 V, ±0.5 pF Capacitor 1 ECU- Panasonic C3E1H100DCQ15000 pF, 16 V, 10% capacitor 1 ECJ-0EB1C153K Panasonic C340.01 µF, 25 V, 10% capacitor 1 ECJ-0EF1E103Z Panasonic C14120 pF, 50 V, 5% capacitor 1 ECU-V1H121JCV Panasonic C33
RESISTORS
10-k Ωresistor 1/16 W, 1% 4 ERJ-6ENF1002V Panasonic R34–R3710- Ωresistor 1/16 W, 1% 1 ERJ-6ENF10R0V Panasonic R3 R150- Ωresistor, 1/16 W, 1% 2 ERJ-3GEY0R00V Panasonic R23, R26 R24, R27–R3349.9- Ωresistor, 1/16 W, 1% 3 ERJ-3EKF49R9V Panasonic R12, R13, R39 R40127- Ωresistor, 1/16 W, 1% 1 ERJ-3EKF1270V Panasonic R25200- Ωresistor, 1/16 W, 1% 2 ERJ-3EKF2000V Panasonic R11, R141-k Ωresistor, 1/16 W, 1% 2 ERJ-3EKF1001V Panasonic R1, R4110- Ωresistor, 1/10 W, 1% 0 ERA-3EKF110V Panasonic R18221- Ωresistor, 1/10 W, 1% 0 ERA-3EKF221V Panasonic R1722.1- Ωresistor, 1/10 W, 1% 2 ERJ-3EKF22R1V Panasonic R16, R3810- Ωresistor, 1/16 W, 1% 1 ERJ-2RFK10R0X Panasonic R43100- Ωresistor, 1/10 W, 1% 4 ERA-3EKF100V Panasonic R5, R10, R19, R20 R21, R22Surface Mount Socket strips 1 310-93-164-41- Mill-Max See Note 810500051- Ωresistor pack 4 CTS See Note 7 RP5, RP6, RP9,RP1022- Ωresistor pack 4 4816P-001-220 BOURNS RP1–RP4
FERRITE BEADS, CONNECTORS, JUMPERS, JACKS, ICs, etc.
MBRB2515L 2 MBRB2515LT4 On- D1, D2Semiconduct
orFerrite bead 6 EXC-ML32A680U FB1–FB6SMA connectors 8 16F3627 Newark J2–J6, J11, J18, J19Black test point 4 5001K Keystone TP2–TP53POS_header 3 HTSW-150-07-L- Samtec W1–W3S30-pin header 1 HTSW-110-07-L-T Samtec J1534-pin header 2 TSW-117-01-S- Samtec J13, J14DV-LCRed banana jacks 2 ST-351A Allied J7, J8
20 DAC5686 EVM SLWU006E – December 2004 – Revised March 2007Submit Documentation Feedback