Texas Instruments UCD90240EVM-704 User manual

User's Guide
SLVUAF3A–March 2015–Revised March 2015
UCD90240EVM-704 24-Rail Sequencer Development Board
The UCD90240 is a 24-rail PMBus power sequencer and system manager. This UCD90240EVM-704
user's guide describes features, typical applications, electrical specifications, and an overview of the EVM
board. Also included are test setup and procedures, software setup, printed-circuit board layouts, a bill of
materials (BOM), and the EVM schematics.
Contents
1 Introduction ................................................................................................................... 2
2 Description.................................................................................................................... 2
2.1 Typical Applications ................................................................................................ 2
2.2 Features.............................................................................................................. 2
3 Electrical Performance Specifications..................................................................................... 3
4 Board Overview.............................................................................................................. 4
5 Test Setup .................................................................................................................... 5
5.1 Test Equipment ..................................................................................................... 5
5.2 Recommended Test Setup........................................................................................ 5
5.3 List of Connectors and Functions................................................................................. 6
5.4 Test Points ......................................................................................................... 13
6 Software Setup ............................................................................................................. 13
6.1 Fusion Digital Power Designer Software (Fusion GUI) Installation......................................... 13
7 Test Procedure ............................................................................................................. 14
7.1 Voltage Monitoring Example..................................................................................... 14
7.2 Rail Enable Example.............................................................................................. 14
7.3 Fault Log Example (Including Blackbox Log).................................................................. 14
7.4 Command GPO Example ........................................................................................ 14
7.5 Configurable Pullup/Pulldown Signals.......................................................................... 14
7.6 GPI and Logic GPO Example ................................................................................... 14
7.7 Margin Example ................................................................................................... 15
7.8 Cascading Example............................................................................................... 15
8 EVM Assembly Drawing and PCB Layout .............................................................................. 16
9 Bill of Materials (BOM)..................................................................................................... 24
10 UCD90240EVM-704 Schematics ........................................................................................ 26
List of Figures
1 UCD90240EVM-704 Board Overview..................................................................................... 4
2 UCD90240EVM-704 Recommended Test Setup........................................................................ 5
3 UCD90240EVM-704 Top Assembly Drawing........................................................................... 16
4 UCD90240EVM-704 Bottom Assembly Drawing....................................................................... 16
5 UCD90240EVM-704 Fabrication Drawing .............................................................................. 17
6 UCD90240EVM-704 Top Overlay........................................................................................ 18
7 UCD90240EVM-704 Top Solder Mask.................................................................................. 18
8 UCD90240EVM-704 Top Layer .......................................................................................... 19
9 UCD90240EVM-704 Midlayer 1.......................................................................................... 19
10 UCD90240EVM-704 Midlayer 2.......................................................................................... 20
11 UCD90240EVM-704 Midlayer 3.......................................................................................... 20
SWIFT is a trademark of Texas Instruments.
Microsoft, Windows are registered trademarks of Microsoft Corporation.
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12 UCD90240EVM-704 Midlayer 4.......................................................................................... 21
13 UCD90240EVM-704 Bottom Layer ...................................................................................... 21
14 UCD90240EVM-704 Bottom Solder Mask.............................................................................. 22
15 UCD90240EVM-704 Bottom Overlay.................................................................................... 22
16 UCD90240EVM-704 Drill Drawing....................................................................................... 23
17 UCD90240EVM-704 Board Dimensions ................................................................................ 23
18 UCD90240EVM Schematic (1 of 6)...................................................................................... 26
19 UCD90240EVM Schematic (2 of 6)...................................................................................... 27
20 UCD90240EVM Schematic (3 of 6)...................................................................................... 28
21 UCD90240EVM Schematic (4 of 6)...................................................................................... 29
22 UCD90240EVM Schematic (5 of 6)...................................................................................... 30
23 UCD90240EVM Schematic (6 of 6)...................................................................................... 31
List of Tables
1 UCD90240EVM-704 Electrical Performance Specifications ........................................................... 3
2 Connector Definition......................................................................................................... 6
3 Test Point Functions....................................................................................................... 13
4 UCD90240EVM-704 Bill of Materials.................................................................................... 24
1 Introduction
This user’s guide describes the UCD90240 Sequencer Development Board (UCD90240EVM-704). The
UCD90240 is a 24-rail PMBus power sequencer and system manager. The UCD90240 can sequence,
monitor and margin 24 voltage rails, monitor and respond to user-defined faults such as OV, UV, OC, UC,
temperature, time-out, and GPI-triggered faults; provide flexible configurations such as sequence-on/off
dependencies, delay time, and Boolean logic; store fault logs into nonvolatile memory; and integrate
value-added features such as watchdog, system reset, cascading and sync clock.
2 Description
The UCD90240EVM-704 contains a UCD90240 sequencer device and a step-down power stage using the
TPS54678 synchronous step-down switcher with integrated FET (SWIFT™). Access to all of the I/O pins
is provided via strip connectors for integration into complex systems using clip-type jumper wires. The
UCD90240EVM provides a PMBus (power management bus) communication port. Microsoft®Windows®
based host computers can monitor, control and configure the UCD90240 device using a USB interface
adapter EVM (HPA172) and TI fusion digital power designer graphical user interface (GUI). The power
stage using the TPS54678 synchronous step-down switcher (5-V input, 1.2-V output) is provided to assist
evaluation of the UCD90240’s margining function.
2.1 Typical Applications
• Industrial / ATE
• Telecom / Networking equipment
• Servers and storage systems
• Any system requiring sequencing and monitoring of multiple power rails
2.2 Features
• Powered by single 5-V supply
• Status LEDs on all digital I/O pins
• Strip connector I/O access
• Headers with pullup/pulldown configurability
• PMBus interface for configuration and monitoring
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3 Electrical Performance Specifications
Table 1. UCD90240EVM-704 Electrical Performance Specifications
Parameter Test Conditions MIN TYP MAX UNIT
Input Power
Input voltage range 4.5 5 5.5 V
Input current All LEDs on, no external load current on I/O pins or step-down 135 mA
converter
Step-Down Converter
Output voltage Normal operation, not in margin mode 1.2 V
Output current 6 A
Analog Input
Analog input voltage range Use internal reference 0 – 3.3 V
Analog input voltage range Use external reference 0 – 3 V
Digital Inputs and Outputs
I/O high-level input voltage(1) 2.15 – 5.5 V
I/O low-level input voltage 0 – 1.15 V
I/O input hysteresis 0.2 – – V
I/O high-level output voltage Load current (source) = –4 mA 2.4 – – V
I/O low-level output voltage Load current (sink) = 4 mA – – 0.4 V
(1) Maximum input voltage for PMBUS_CNTRL, PMBALERT#, MARGIN19 and MARGIN20 pins are V33D +0.3 V
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4 Board Overview
Figure 1 illustrates the UCD90240EVM-704 board.
Figure 1. UCD90240EVM-704 Board Overview
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5 Test Setup
5.1 Test Equipment
Voltage Source: One 5-volt power supply with at least 0.5-A sourcing capability. (Optional) One DC
power supply with adjustable voltage from 0 V to 3.3 V.
Multimeters: One voltmeter
Output Load: Optional
Oscilloscope: Optional
Fan: None
Recommended Wire Gauge:AWG 24, or thicker
To Test Configuration, Monitoring and Control Functionality
Recommended PC platform: Windows 7, 64-bit with 8-GB RAM
USB Interface Adapter EVM (USB-to-GPIO): HPA172
The latest version Fusion Digital Power Designer software can be downloaded at the following link
to the Texas Instruments website:
http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html
5.2 Recommended Test Setup
Figure 2 illustrates the recommended test setup.
Figure 2. UCD90240EVM-704 Recommended Test Setup
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5.3 List of Connectors and Functions
Table 2 lists the EVM connectors and functions.
Table 2. Connector Definition
Connectors Pins Name Description
J1 1 MARGIN1 Margin PWM output
2 MARGIN2 Margin PWM output
3 MARGIN3 Margin PWM output
4 MARGIN4 Margin PWM output
5 MARGIN5 Margin PWM output
6 MARGIN6 Margin PWM output
7 MARGIN7 Margin PWM output
8 MARGIN8 Margin PWM output
J2 1 MARGIN9 Margin PWM output
2 MARGIN10 Margin PWM output
3 MARGIN11 Margin PWM output
4 MARGIN12 Margin PWM output
5 MARGIN13 Margin PWM output
6 MARGIN14 Margin PWM output
7 MARGIN15 Margin PWM output
8 MARGIN16 Margin PWM output
J3 1 MARGIN17 Margin PWM output
2 MARGIN18 Margin PWM output
3 MARGIN19 Margin PWM output
4 MARGIN20 Margin PWM output
5 MARGIN21 Margin PWM output
6 MARGIN22 Margin PWM output
7 MARGIN23 Margin PWM output
8 MARGIN24 Margin PWM output
J4 1 EN1 Rail enable output
2 EN2 Rail enable output
3 EN3 Rail enable output
4 EN4 Rail enable output
5 EN5 Rail enable output
6 EN6 Rail enable output
7 EN7 Rail enable output
8 EN8 Rail enable output
J5 1 EN9 Rail enable output
2 EN10 Rail enable output
3 EN11 Rail enable output
4 EN12 Rail enable output
5 EN13 Rail enable output
6 EN14 Rail enable output
7 EN15 Rail enable output
8 EN16 Rail enable output
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Table 2. Connector Definition (continued)
Connectors Pins Name Description
J6 1 EN17 Rail enable output
2 EN18 Rail enable output
3 EN19 Rail enable output
4 EN20 Rail enable output
5 EN21 Rail enable output
6 EN22 Rail enable output
7 EN23 Rail enable output
8 EN24 Rail enable output
J7 1 LGPO1 Logic GPO output
2 LGPO2 Logic GPO output
3 LGPO3 Logic GPO output
4 LGPO4 Logic GPO output
5 LGPO5 Logic GPO output
6 LGPO6 Logic GPO output
7 LGPO7 Logic GPO output
8 LGPO8 Logic GPO output
J8 1 LGPO9 Logic GPO output
2 LGPO10 Logic GPO output
3 LGPO11 Logic GPO output
4 LGPO12 Logic GPO output
5 GPIO1 General Purpose I/O
6 GPIO2 General Purpose I/O
7 GPIO3 General Purpose I/O
8 GPIO4 General Purpose I/O
J9 1 PMBUS_ADDR0 PMBus address pin
2 PMBUS_ADDR1 PMBus address pin
3 PMBUS_ADDR2 PMBus address pin
4 SYNC_CLOCK Sync Clock pin
5 GPIO21 General Purpose I/O
6 GPIO22 General Purpose I/O
7 GPIO23 General Purpose I/O
8 GPIO24 General Purpose I/O
J10 1 GPIO13 General Purpose I/O
2 GPIO14 General Purpose I/O
3 GPIO15 General Purpose I/O
4 GPIO16 General Purpose I/O
5 GPIO17 General Purpose I/O
6 GPIO18 General Purpose I/O
7 GPIO19 General Purpose I/O
8 GPIO20 General Purpose I/O
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Table 2. Connector Definition (continued)
Connectors Pins Name Description
J11 1 GPIO5 General Purpose I/O
2 GPIO6 General Purpose I/O
3 GPIO7 General Purpose I/O
4 GPIO8 General Purpose I/O
5 GPIO9 General Purpose I/O
6 GPIO10 General Purpose I/O
7 GPIO11 General Purpose I/O
8 GPIO12 General Purpose I/O
J12 1 No connection
2 No connection
3 No connection
4 No connection
5 +3V3_USB 3.3-V power provided by USB Interface Adapter EVM
6 GND PMBus GND
7 PMB_CTRL PMBus CONTROL line
8 PMB_ALERT PMBus ALERT# line
9 PMB_SCL PMBus Clock
10 PMB_SDA PMBus Data
J13 1 JTAG_TMS JTAG TMS
2 JTAG nTRST (unused)
3 JTAG_TDI JTAG TDI
4 JTAG TDIS (unused)
5 JTAG VTRef (unused)
6 JTAG KEY
7 JTAG_TDO JTAG TDO
8 GND JTAG GND
9 JTAG RTCK (unused)
10 GND JTAG GND
11 JTAG_TCK JTAG TCK
12 GND JTAG GND
13 JTAG EMU0 (unused)
14 JTAG EMU1 (unused)
J14 1 MON1 Analog monitor input
2 MON2 Analog monitor input
3 MON3 Analog monitor input
4 MON4 Analog monitor input
5 MON5 Analog monitor input
6 MON6 Analog monitor input
7 MON7 Analog monitor input
8 MON8 Analog monitor input
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Table 2. Connector Definition (continued)
Connectors Pins Name Description
J15 1 MON9 Analog monitor input
2 MON10 Analog monitor input
3 MON11 Analog monitor input
4 MON12 Analog monitor input
5 MON13 Analog monitor input
6 MON14 Analog monitor input
7 MON15 Analog monitor input
8 MON16 Analog monitor input
J16 1 MON17 Analog monitor input
2 MON18 Analog monitor input
3 MON19 Analog monitor input
4 MON20 Analog monitor input
5 MON21 Analog monitor input
6 MON22 Analog monitor input
7 MON23 Analog monitor input
8 MON24 Analog monitor input
J17 1 Pullup/pulldown signal (can be used as GPI input)
2 Pullup/pulldown signal (can be used as GPI input)
3 Pullup/pulldown signal (can be used as GPI input)
4 Pullup/pulldown signal (can be used as GPI input)
5 Pullup/pulldown signal (can be used as GPI input)
6 Pullup/pulldown signal (can be used as GPI input)
7 Pullup/pulldown signal (can be used as GPI input)
8 Pullup/pulldown signal (can be used as GPI input)
J18 1 Pullup/pulldown signal (can be used as GPI input)
2 Pullup/pulldown signal (can be used as GPI input)
3 Pullup/pulldown signal (can be used as GPI input)
4 Pullup/pulldown signal (can be used as GPI input)
5 Pullup/pulldown signal (can be used as GPI input)
6 Pullup/pulldown signal (can be used as GPI input)
7 Pullup/pulldown signal (can be used as GPI input)
8 Pullup/pulldown signal (can be used as GPI input)
J19 1 Pullup/pulldown signal (can be used as GPI input)
2 Pullup/pulldown signal (can be used as GPI input)
3 Pullup/pulldown signal (can be used as GPI input)
4 Pullup/pulldown signal (can be used as GPI input)
5 Pullup/pulldown signal (can be used as GPI input)
6 Pullup/pulldown signal (can be used as GPI input)
7 Pullup/pulldown signal (can be used as GPI input)
8 Pullup/pulldown signal (can be used as GPI input)
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Table 2. Connector Definition (continued)
Connectors Pins Name Description
J20 1 Pullup/pulldown signal (can be used as GPI input)
2 Pullup/pulldown signal (can be used as GPI input)
3 Pullup/pulldown signal (can be used as GPI input)
4 Pullup/pulldown signal (can be used as GPI input)
5 Pullup/pulldown signal (can be used as GPI input)
6 Pullup/pulldown signal (can be used as GPI input)
7 Pullup/pulldown signal (can be used as GPI input)
8 Pullup/pulldown signal (can be used as GPI input)
J21 1 VDD VDD (connect to Pin2 to pullup)
2 Floating pin connected to PMBUS_ADDR0 through 1-kΩresistor
3 GND GND (connect to Pin2 to pulldown)
J22 1 VDD VDD (connect to Pin2 to pullup)
2 Floating pin connected to PMBUS_ADDR1 through 1-kΩresistor
3 GND GND (connect to Pin2 to pulldown)
J23 1 VDD VDD (connect to Pin2 to pullup)
2 Floating pin connected to PMBUS_ADDR2 through 1-kΩresistor
3 GND GND (connect to Pin2 to pulldown)
J24 1 +3V3_USB 3.3-V power provided by USB Interface Adapter EVM
2 +3V3 3.3V rail to power VDD
J25 1 5V_VIN 5-V input power positive terminal
2 GND 5-V input power negative terminal
J26 1 5V_VIN 5-V input power positive terminal
2 GND 5-V input power negative terminal
J27 1 POL_Margin Connect this pin to a MARGIN pin to test margining function.
J28 1 +3V3 +3V3 rail (connect to Pin2 to pullup)
2 POL_EN POL enable
3 Input from J29 (connect to Pin2 to control POL enable)
J29 1 Connect this pin to an EN pin to test enable function.
J30 1 POL_VOUT Connect this pin to a MON pin to test margining function.
J31 1 +3V3 Connect to Pin2 to pullup
2 DIO_01 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J32 1 +3V3 Connect to Pin2 to pullup
2 DIO_02 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J33 1 +3V3 Connect to Pin2 to pullup
2 DIO_03 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J34 1 +3V3 Connect to Pin2 to pullup
2 DIO_04 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J35 1 +3V3 Connect to Pin2 to pullup
2 DIO_05 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
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Table 2. Connector Definition (continued)
Connectors Pins Name Description
J36 1 +3V3 Connect to Pin2 to pullup
2 DIO_06 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J37 1 +3V3 Connect to Pin2 to pullup
2 DIO_07 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J38 1 +3V3 Connect to Pin2 to pullup
2 DIO_08 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J39 1 +3V3 Connect to Pin2 to pullup
2 DIO_09 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J40 1 +3V3 Connect to Pin2 to pullup
2 DIO_10 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J41 1 +3V3 Connect to Pin2 to pullup
2 DIO_11 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J42 1 +3V3 Connect to Pin2 to pullup
2 DIO_12 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J43 1 +3V3 Connect to Pin2 to pullup
2 DIO_13 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J44 1 +3V3 Connect to Pin2 to pullup
2 DIO_14 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J45 1 +3V3 Connect to Pin2 to pullup
2 DIO_15 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J46 1 +3V3 Connect to Pin2 to pullup
2 DIO_16 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J47 1 +3V3 Connect to Pin2 to pullup
2 DIO_17 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J48 1 +3V3 Connect to Pin2 to pullup
2 DIO_18 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J49 1 +3V3 Connect to Pin2 to pullup
2 DIO_19 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J50 1 +3V3 Connect to Pin2 to pullup
2 DIO_20 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
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Table 2. Connector Definition (continued)
Connectors Pins Name Description
J51 1 +3V3 Connect to Pin2 to pullup
2 DIO_21 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J52 1 +3V3 Connect to Pin2 to pullup
2 DIO_22 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J53 1 +3V3 Connect to Pin2 to pullup
2 DIO_23 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J54 1 +3V3 Connect to Pin2 to pullup
2 DIO_24 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J55 1 +3V3 Connect to Pin2 to pullup
2 DIO_25 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J56 1 +3V3 Connect to Pin2 to pullup
2 DIO_26 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J57 1 +3V3 Connect to Pin2 to pullup
2 DIO_27 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J58 1 +3V3 Connect to Pin2 to pullup
2 DIO_28 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J59 1 +3V3 Connect to Pin2 to pullup
2 DIO_29 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J60 1 +3V3 Connect to Pin2 to pullup
2 DIO_30 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J61 1 +3V3 Connect to Pin2 to pullup
2 DIO_31 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
J62 1 +3V3 Connect to Pin2 to pullup
2 DIO_32 Floating pin to create a digital signal (high or low)
3 GND Connect to Pin2 to pulldown
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5.4 Test Points
Table 3. Test Point Functions
Test Points Name Description
TP1 GND Ground
TP2 GND Ground
TP3 GND Ground
TP4 GND Ground
TP5 GND Ground
TP6 GND Ground
TP7 GND Ground
TP8 POL_VOUT POL output voltage
TP9 GND Ground
TP10 PMB_SDA PMBus Data
TP11 PMB_CTRL PMBus CONTROL line
TP12 PMB_SCL PMBus Clock
TP13 PMB_ALERT PMBus ALERT# line
TP14 RESET UCD90240 reset pin signal
6 Software Setup
Accessing the UCD90240EVM-704’s configuration, control, and monitoring capabilities with the Fusion
Digital Power Designer software tool requires a onetime software setup per host system.
6.1 Fusion Digital Power Designer Software (Fusion GUI) Installation
Place the Fusion Digital Power Designer Software (Fusion GUI) Installer executable file in a known
location on the host computer to be used for EVM configuration/test.
Double click the TI-Fusion-Digital-Power-Designer-2.0.xxx.exe file and proceed through the installation by
accepting the installer prompts and the license agreement. Use the Fusion GUI installer’s suggested
default installation locations to complete the install.
When the Fusion GUI installation reaches the finished window, uncheck the Launch Application check box
and close the window.
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7 Test Procedure
The UCD90240EVM-704_Default_Configuration.xml file is found in the SLVC613 zip file on the TI website
and is provided to allow the user to return the EVM to its originally configured state.
Connect the EVM as shown in Figure 2: UCD90240 Recommended Test Setup. Apply the input voltage to
the test setup. Open the Fusion Digital Power Designer GUI by navigating to the Start →Texas
Instruments Fusion Digital Power Designer →Fusion Digital Power Designer (not the offline version which
would have monitoring disabled). At the default Configuration Screen select the File →Import Project and
the Project Open Wizard window will open. Open the default configuration file (UCD90240EVM-
704_Default_Configuration.xml) and click Next. Follow the prompt to download the configuration file.
7.1 Voltage Monitoring Example
In the default configuration file, all MON pins are assigned to corresponding rails. Apply an external
voltage within the specification in Table 1 to a MON pin. The voltage applied on the MON pin will be
displayed in the Fusion GUI →Monitor page.
7.2 Rail Enable Example
In the default configuration file, all EN pins are assigned to corresponding rails, and all rails are controlled
by CONTROL pin. The pin assignments are shown in Fusion GUI →Configure page→Pin Assignment
tab. The CONTROL pin status can be controlled in Fusion GUI →Monitor page. Turn on the CONTROL
Line in the Monitor page. Observe that all LEDs attached to EN pins are lit.
7.3 Fault Log Example (Including Blackbox Log)
Make sure the EN pin of a rail is asserted. Adjust the external voltage applied to the rail’s MON pin such
that the voltage is above Power Good On threshold and below OV Warn/Fault thresholds. In the Status
page, click the Clear Faults button, Clear Logged Faults button, and Clear Blackbox Log button.
Adjust the external voltage applied to the MON pin such that the voltage is above OV fault threshold. In
the Status page →Status Registers tab, observe that the Vout OV Fault of the corresponding rail is
raised. In the Logged Faults tab, observe that the Vout OV Fault of the corresponding rail is also raised. In
the Blackbox Info tab, click Refresh Blackbox Log button. Observe that the fault information and all the
GPI/GPO/Rail statuses when the fault occurred were recorded in the Blackbox Log.
7.4 Command GPO Example
In the default configuration file, 12 GPIO pins are configured as command GPO. In the Configure page →
Pin Assignment tab, change the Command GPO states and then click the Write to Hardware button.
Observe the LED of the corresponding GPO pin changes state.
7.5 Configurable Pullup/Pulldown Signals
The UCD90240EVM-704 provides 32 configurable pullup/pulldown signals. The output pins of the
pullup/pulldown signals are located in J17, J18, J19, and J20. Each pin is connected to 3.3 V or GND
through a 680-Ωresistor. The state of each pin can be configured by a 3-pin header next to it. The
pullup/pulldown signals can be used as GPI pin input signals and pull up for open-drain GPO pins.
7.6 GPI and Logic GPO Example
In the default configuration file, 12 GPIO pins are configured as GPI pin with GPI Fault feature enabled.
Each of the 12 LGPO pins is configured to follow a corresponding GPI signal with a 960-ms time delay.
The pin assignments are shown in the Configure page →Pin Assignment tab.
Connect a logic input signal to a GPI pin. Observe that the LED of the corresponding LGPO pin is lit after
960 ms. Also observe that the corresponding GPI Fault is logged in the Status page. Disconnect the logic
input signal from the GPI pin. Observe that the LED of the corresponding LGPO pin is out after 960 ms.
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7.7 Margin Example
In the default configuration file, all 24 rails are configured with the margining function. The pin assignments
are shown in the Configure page→Pin Assignment tab. Connect the onboard POL output voltage (J30) to
a rail’s MON pin using a jumper wire. Then connect the rail’s MARGIN pin to the onboard POL’s margin
input (J27) to close the margin loop. Connect the rail’s EN pin to J29 which controls the onboard POL’s
enable signal. Connect J28’s Pin 2 and Pin 3 using a shunt jumper. In the Fusion GUI →Monitor page,
turn on the CONTROL line. Observe that the rail’s EN pin LED is lit, and the onboard POL is enabled. The
POL’s output voltage is monitored in the Monitor page, which should be at 1.2 V.
In the Fusion GUI →Monitor page, click to change the margin status to Low. Observe that the POL output
voltage is regulated at Margin Low level defined in the Configure page→Vout Config tab. Click to change
the margin status to High. Observe that the POL output voltage is regulated at Margin High level.
7.8 Cascading Example
7.8.1 Sync Clock
Sync Clock can synchronize multiple UCD90240 devices such that they respond to the same GPI event
synchronously and the same GPI event has the same time stamp in all synchronized UCD90240 devices.
The Sync Clock I/O pin is located in J9. Implementing the Sync Clock feature requires two or more
UCD90240EVM-704 boards.
In the Fusion GUI →Configure page →Other Config tab, configure one EVM board as Sync Clock
master, and all other boards as slaves. Connect the multiple EVM boards to the same ground. Connect all
Sync Clock pins to the same node. Observe that the synchronized UCD90240 devices respond to the
same GPI event synchronously.
When the Sync Clock pin is not used, configure the UCD90240 device as Sync Clock master.
7.8.2 Fault Pin
Multiple UCD90240 devices can be acknowledged on the same rail fault and react accordingly, even if the
rail is monitored by only one UCD90240 device. This is achieved by the Fault Pin feature.
In each UCD90240 device, up to 4 GPI pins can be configured as Fault Pins. Each Fault Pin is connected
to a Fault Bus. Each Fault Bus is pulled up to 3.3 V by a 10-kΩresistor. When there is no fault on a Fault
Bus, the Fault Pins are GPI pins and listen to the Fault Bus. When a rail fault is detected by a UCD90240
device, the corresponding Fault Pin is turned into active driven low state, pulling down the Fault Bus and
informing all other UCD90240 devices of the corresponding fault. Refer to the UCD90240 datasheet for
configuration and connection examples.
The Fault Pin feature and the Sync Clock feature can work together to achieve better synchronized fault-
response performance.
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EVM Assembly Drawing and PCB Layout www.ti.com
8 EVM Assembly Drawing and PCB Layout
Figure 3 and Figure 4 illustrate the EVM assembly drawings and PCB layouts.
Figure 3. UCD90240EVM-704 Top Assembly Drawing
Figure 4. UCD90240EVM-704 Bottom Assembly Drawing
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Figure 5 illustrates the UCD90240EVM-704 fabrication drawing.
Figure 5. UCD90240EVM-704 Fabrication Drawing
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Figure 6 through Figure 17 illustrate the UCD90240EVM-704 PCB drawings.
Figure 6. UCD90240EVM-704 Top Overlay
Figure 7. UCD90240EVM-704 Top Solder Mask
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Figure 8. UCD90240EVM-704 Top Layer
Figure 9. UCD90240EVM-704 Midlayer 1
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Figure 10. UCD90240EVM-704 Midlayer 2
Figure 11. UCD90240EVM-704 Midlayer 3
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