Texas Instruments TPS25984 User manual

User's Guide
TPS25984 Evaluation Module (EVM)
ABSTRACT
This user’s guide describes the evaluation module (EVM) for the TPS25984 eFuse. The TPS25984 device is
a 4.5-V to 16-V and 70-A (peak) stackable eFuse with accurate and fast current monitor. This device supports
parallel connection of multiple eFuses for higher current designs by actively synchronizing the device states
and sharing the loads during start-up and steady-state. The TPS25984 eFuse has an integrated FET with
ultra-low ON resistance of 0.8 mΩ, adjustable and robust overcurrent and short-circuit protections, precise load
current monitoring, fast overvoltage protection (fixed 16.7-V threshold), adjustable output slew rate control for
inrush-current protection, and overtemperature protection to verify FET SOA. The TPS25984 eFuse also has
adjustable overcurrent transient blanking timer to support load transients, adjustable undervoltage protection,
integrated FET health monitoring and reporting, analog die temperature monitor output, and dedicated fault and
power good indication pins.
Caution
Caution Hot Surface.
Contact may cause burns.
Do not touch !
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 EVM Features.................................................................................................................................................................... 3
1.2 EVM Applications............................................................................................................................................................... 3
2 Description.............................................................................................................................................................................. 3
3 Schematic................................................................................................................................................................................4
4 General Configurations..........................................................................................................................................................6
4.1 Physical Access................................................................................................................................................................. 6
4.2 Test Equipment.................................................................................................................................................................. 7
5 Test Setup and Procedures....................................................................................................................................................8
5.1 Hot Plug............................................................................................................................................................................. 9
5.2 Start-Up With Enable......................................................................................................................................................... 9
5.3 Difference Between Current Limit and DVDT Based Start-Up Mechanisms....................................................................10
5.4 Power Up Into Short......................................................................................................................................................... 11
5.5 Overvoltage Lockout........................................................................................................................................................ 12
5.6 Transient Overload Performance..................................................................................................................................... 13
5.7 Overcurrent Event............................................................................................................................................................ 14
5.8 Provision to Apply Load Transient and Overcurrent Event Using an Onboard Switching Circuit.....................................14
5.9 Output Hot Short.............................................................................................................................................................. 16
5.10 Quick Output Discharge (QOD)..................................................................................................................................... 17
5.11 Thermal Performance of TPS25984EVM....................................................................................................................... 17
6 EVAL Board Assembly Drawings and Layout Guidelines................................................................................................ 19
6.1 PCB Drawings..................................................................................................................................................................19
7 Bill of Materials (BOM)..........................................................................................................................................................22
8 Revision History................................................................................................................................................................... 26
List of Figures
Figure 3-1. TPS25984EVM eFuse Evaluation Board Schematic (Page 1)..................................................................................4
Figure 3-2. TPS25984EVM eFuse Evaluation Board Schematic (Page 2)..................................................................................5
www.ti.com Table of Contents
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 1
Copyright © 2023 Texas Instruments Incorporated

Figure 5-1. TPS25984EVM Setup With Test Equipment............................................................................................................. 8
Figure 5-2. TPS25984 eFuse Hot Plug Profile-1......................................................................................................................... 9
Figure 5-3. TPS25984 eFuse Hot Plug Profile-2......................................................................................................................... 9
Figure 5-4. TPS25984 eFuse Start-Up Profile With ENABLE................................................................................................... 10
Figure 5-5. Start-Up Profile With ENABLE: Current Sharing Between Two (2) TPS25984 eFuses.......................................... 10
Figure 5-6. Start-Up With Current Limit Response of TPS25984 eFuse................................................................................... 11
Figure 5-7. Start-Up With Output Slew Rate Control (Only) Response of TPS25984 eFuse.................................................... 11
Figure 5-8. Power Up Into Output Short Response of TPS25984 eFuse.................................................................................. 12
Figure 5-9. Power Up Into Output Short Response in TPS25984EVM: Current Sharing Between Two (2) eFuses................. 12
Figure 5-10. Overvoltage Lockout Response of TPS25984 eFuse........................................................................................... 12
Figure 5-11. Transient Overload Performance of TPS25984 eFuse..........................................................................................13
Figure 5-12. Transient Overload Performance in TPS25984EVM: Current Sharing Between Two (2) eFuses.........................13
Figure 5-13. Overcurrent Performance of TPS25984 eFuse-1..................................................................................................14
Figure 5-14. Overcurrent Performance of TPS25984 eFuse-2..................................................................................................14
Figure 5-15. Transient Overload Performance in TPS25984EVM Using the Onboard Switching Circuit.................................. 15
Figure 5-16. Persistent Overload Performance in TPS25984EVM Using the Onboard Switching Circuit.................................15
Figure 5-17. Output Hot Short Response of TPS25984 eFuse................................................................................................. 16
Figure 5-18. QOD Enabled on TPS25984 eFuse...................................................................................................................... 17
Figure 5-19. QOD Disabled on TPS25984 eFuse..................................................................................................................... 17
Figure 5-20. Thermal Performance of TPS25984EVM..............................................................................................................18
Figure 6-1. TPS25984EVM Board: Top Assembly.....................................................................................................................19
Figure 6-2. TPS25984EVM Board: Bottom Assembly............................................................................................................... 19
Figure 6-3. TPS25984EVM Board: Top Layer........................................................................................................................... 19
Figure 6-4. TPS25984EVM Board: Bottom Layer......................................................................................................................19
Figure 6-5. TPS25984EVM Board: Layer 2 (Power)................................................................................................................. 20
Figure 6-6. TPS25984EVM Board: Layer 3 (Power)................................................................................................................. 20
Figure 6-7. TPS25984EVM Board: Layer 4 (Signal)..................................................................................................................20
Figure 6-8. TPS25984EVM Board: Layer 5 (Signal)..................................................................................................................20
Figure 6-9. TPS25984EVM Board: Layer 6 (Power)................................................................................................................. 21
Figure 6-10. TPS25984EVM Board: Layer 7 (Power)............................................................................................................... 21
List of Tables
Table 2-1. TPS25984EVM eFuse Evaluation Board Options and Setting................................................................................... 3
Table 4-1. Input and Output Connector Functionality.................................................................................................................. 6
Table 4-2. Test Points Description............................................................................................................................................... 6
Table 4-3. Jumper Descriptions and Default Positions................................................................................................................ 7
Table 4-4. LED Descriptions........................................................................................................................................................ 7
Table 5-1. Default Jumper Setting for TPS25984EVM eFuse Evaluation Board......................................................................... 8
Table 7-1. TPS25984EVM Bill of Materials................................................................................................................................22
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
2TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

1 Introduction
The TPS25984EVM eFuse evaluation board allows reference circuit evaluation of Texas Instruments (TI)
TPS25984 eFuse. The TPS25984 device is a 4.5-V to 16-V and 70-A (peak) stack-able eFuse with accurate and
fast current monitor. This device supports parallel connection of multiple eFuses for higher current designs by
actively synchronizing the device states and sharing the loads during start-up and steady-state. The TPS25984
eFuse has an integrated FET with ultra-low ON resistance of 0.8 mΩ, adjustable and robust overcurrent and
short-circuit protections, precise load current monitoring, fast overvoltage protection (fixed 16.7-V threshold),
adjustable output slew rate control for inrush current protection, and over-temperature protection to verify FET
SOA. The TPS25984 eFuse also has adjustable overcurrent transient blanking timer to support load transients,
adjustable undervoltage protection, integrated FET health monitoring and reporting, analog die temperature
monitor output, and dedicated fault and power good indication pins.
1.1 EVM Features
TPS25984EVM comes with two (2) TPS25984 eFuses connected in parallel to evaluate a 12-V (typical) and
110-A (steady-state) design. TPS25984EVM eFuse evaluation board features include:
• 5-V to 16-V (typical) operation
• 14-A to 120-A programmable circuit breaker threshold using onboard jumpers
• Adjustable reference voltage for overcurrent protection and active current sharing blocks
• Adjustable output voltage slew rate control
• Adjustable transient current blanking timer
• Adjustable current limit during start-up and active current sharing threshold using onboard jumpers
• TVS diode for input and Schottky diode for output transient protections
• LED status for power good and fault indications
• Options to engage the power cycle and the quick output discharge (QOD)
• Option to apply custom load transients using onboard MOSFETs, gate drive circuit, and load resistors
1.2 EVM Applications
This EVM can be used on the following applications:
• Input hotswap and hotplug
•Server and high performance computing
•Network interface cards
•Graphics and hardware accelerator cards
•Datacenter switches and routers
• Fan trays
• Switches/routers
2 Description
The TPS25984EVM enables the evaluation of TPS259840x and TPS259841x eFuses from TPS25984 family.
This EVM has two (2) TPS259840x eFuses connected in parallel. The input power is applied across the
connectors T1 and T3, while T2 and T3 provide the output connection for the EVM; refer to the schematic in
Figure 3-1 and EVM test setup in Figure 5-1. TVS diodes D1 and D2 provide the input protection from transient
overvoltages. Schottky diodes D3 and D4 protect the output by clamping the negative voltage excursion at the
OUT pins of TPS25984 eFuses within the minimum absolute rating.
SW1 allows to do power cycle and SW2 enables the quick output discharge (QOD). Power Good (PG) and fault
(FLTb and FLTb2) indicators are provided by LED DG1, DR1, and DR2 respectively.
Table 2-1. TPS25984EVM eFuse Evaluation Board Options and Setting
EVM Function VIN UVLO
Threshold
VIN OVLO
Threshold ITIMER Output Slew Rate (dv/dt) IMON ILIM ILIM2 IREF
Performance
evaluation of
TPS25984, 4.5-V to
16-V, 55-A (RMS)
eFuse
5 V 16.7 V
Selectable -
1.4 ms and
14 ms
Selectable -
1.2 V/ms, 1.8
V/ms, and 12
V/ms
Selectable -
120 A and
70 A with
VREF of 1 V
Selectable - 38 A and 22 A
of inrush current limit and 59
A and 35 A of active current
sharing threshold with VREF of
1 V
Selectable -
1 V and 0.8
V
www.ti.com Introduction
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 3
Copyright © 2023 Texas Instruments Incorporated

3 Schematic
Figure 3-1 illustrates the EVM schematic.
VIN VOUT
QGND
PGND
PGND
0
RZ1
QGND
PGND
QGND QGND QGNDQGNDQGNDQGND
QGND
VDD_Pullup
10.0k
R4
10.0k
R5
50V
3300pF
CD1
50V
2200pF
CT1
PGND
T4
T5
PGND
0.5%
40.2k
RF1
C9
2.2µF
1.0M
R2
0.5%
40.2k
RF3
0.5%
31.6k
RF2
1 2
3 4 5 6
J2
50V
3300pF
CD4
PGND
NT1
Net-Tie
S1_P NT2
Net-Tie
S1_NS1_P
S1_N
VINVOUT
VIN VOUT
0.1%
1.58k
RM5
TAP points from inner portion of #12 for VIN and #28 for VOUT of U1
2 1
D2
SMDJ12A
0.1%
576
RL5
0.1%
402
RL1
0.1%
1.58k
RM6
0
RM1
25V
4700uF
CO2
PGND
25V
470uF
CO1
35V
1µF
C6
C1
1µF 100nF
C2
100nF
50V
C4
1 4
2 3
SW1
1 4
2 3
SW2
2 1
D1
SMDJ12A
PGND
TP2TP1
QGND
121k
R9
QGND
QGND
VDD-PRI
FLTb
SWEN
TEMP
DVDT
MODE
PG
EN
ITIMER
IMON
ILIM
IREF
VDD-PRI
FLTb
SWEN
TEMP
DVDT
ITIMER
IMON
ILIM
IREF
MODE
PG
EN
9TP
2TP2
0TP2
9TP1
8TP1
7TP1
5TP1
4TP1
TP13
2TP1
1TP1
0TP1
VIN
QGND QGND
VIN VOUT
QGND
0
RZ4
QGND
PGND
PGND
35V
1µF
C16
35V
C17
1µF
35V
1µF
C18
PGND PGND
35V
C14
1µF
35V
C10
1µF 100nF
50V
C11
100nF
50V
C13
QGND QGND
0.1%
402
RL6
0
RM7
QGND
C19
2.2µF
ILIM2 ILIM2 TP16
1 3
NC
2
D5
1 3
J4A
PEC02DABN
2 4
J4B
PEC02DABN
1 3
J5A
PEC02DABN
2 4
J5B
PEC02DABN
1 3
J6A
PEC02DABN
2 4
J6B
PEC02DABN
1 3
J7A
PEC02DABN
2 4
J7B
PEC02DABN
1 3
J3A
PEC02DABN
2 4
J3B
PEC02DABN
2.2nF
CT3
QGND QGND
QGND QGND QGND QGND QGND QGND
0.1%
576
RL3
QGND QGND
100k
R1
47nF
C7
50V
33nF
CD3
22nF
50V
CD2
22nF
CT2
R8
R10
1
3
2
D3
SBR10U45SP5-13
1.1k
0.1%
RM2
1
2
3
J1
100k
R6
PGND
C3
1µF
PGND
35V
1µF
C12
VIN VOUT
VDD-PRI FLTb
SWEN
TEMP
DVDT
ITIMER
VIN
VDD-PRI
EN
PG
MODE
IREF
ILIM
IMON
FLTb PG
TEMP MODE DVDT ITIMER IMON ILIM IREF
ILIM2 MODE2
ILIM2IREFILIMIMONITIMERDVDT
SWEN
VIN
EN
VDD-SEC FLTb2
SWEN-SEC
TEMP-SEC
DVDT-SEC
VIN VOUT
VIN
VDD-SEC EN-SEC
PG-SEC
MODE2
IMON
1
T1
1
T2
1
T3
ITIMER
EN-SEC
0
RZ7 EN
QGND
SWEN-SEC
0
RZ5
QGND
SWEN TEMP-SEC
0
RZ6 TEMP
PG-SEC
0
RZ8 PG
10.0k
R11
10.0k
R12
MODE2
FLTb2 MODE2
FLTb2
TP7
TP8
50V
22pF
CTEMP1
5TP VIN 6TP VOUT
Secondary eFuse
Primary eFuse
35V
C5
2.2uF
35V
2.2uF
C15
330k
R7
DVDT-SEC
These components are not mandatory, but are there so that o nly the primary eFuse can be evaluated
by disconnecting the Secondary eFuse for a lower curr ent design. In an actual higher curr ent design,
where both the eFuses need to be in parallel, these five pins wo uld be directly connected.
0
RZ9 DVDT
1000pF
C8
50V
1000pF
CF1
PGND
1
3
2
D4
0
SBR10U45SP5-13
RZ3
0
RZ2
VDD_Pullup
10.0k
R3
FLTb2
VDD-SEC
3TP2 VDD-SEC
21 ITIMER
VIN
33
VIN
9
VIN
10
VIN
11
VIN
12
VIN
13
14 VIN
VIN
15
VIN
16
7VDD
PG 6
8
MODE
NC 17
1
VOUT 2
VOUT 25
26
VOUT
VOUT
VOUT 27
VOUT 28
VOUT 29
30
VOUT 31
32
VOUT
VOUT
IREF
24
ILIM
23
3
SWEN
5
FLT
IMON
22
4EN/UVLO
DVDT
19
18
TEMP
GND 20
TPS25984
U2
21 ITIMER
VIN
33
9VIN
VIN
10
11 VIN
VIN
12
VIN
13
14 VIN
VIN
15
16 VIN
7VDD
PG 6
8
MODE
NC 17
1
VOUT 2
VOUT
VOUT 25
VOUT 26
VOUT
VOUT
27
28
VOUT
VOUT
29
30
VOUT 31
32
VOUT
24 IREF
ILIM
23
3
SWEN
5
FLT
22 IMON
4EN/UVLO
DVDT
19
18
TEMP
GND 20
TP S25984
U1
I
REF
ILIM2
909
RM3
909
RM4
340
RL4 340
RL2
ITIMER2
ITIMER2
TP21 ITIMER2
NT3
Net-Tie
S2_P NT4
Net-Tie
S2_NS1_P
S1_N
VINVOUT
VIN VOUT
TP4
TAP points from inner portion of #13 for VIN and #29 for VOUT of U2
TP3
22pF
CM1
ITIMER:
2.2nF (5%) -> 1.4ms
22nF (10%) -> 14ms
VREF:
40.2k -> 1V
31.6k -> 0.8V
40.2k//31.6k = 15.97k
->0.4V
DVDT:
3.3nF -> 12V/ms
33nF -> 1.2V/ms
22nF -> 1.8V/ms
QOD is engaged
only when EN is in
between 0.8V and
1.1V [VSD < VEN <
VUVLO].
ILIM: [GILIM-> 1/55000.0],
[VREF -> 1 V]
340 -> 38A Start-up Current
Sharing Threshold,
Limit, 59A Active Current
576 -> 22A Start-up Current
Sharing Threshold,
Limit, 35A Active Current
IMON: [GIMON -> 1/55000.0]
909 -> 60A [1V VREF]
1580 -> 35A [1V VREF]
SW1 is for Power
Cycle. SW2 is for
QOD.[9.8V-13.5V
VIN only]
ILIM: [GILIM-> 1/55000.0], [VR E F
-> 1 V]
340 -> 38A Start-up Current Limit,
59A Active Current Sharing
Threshold,
576 -> 22A Start-up Current Limit,
35A Active Current Sharing
Threshold,
Figure 3-1. TPS25984EVM eFuse Evaluation Board Schematic (Page 1)
Schematic www.ti.com
4TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

QGND1
QGND
G1
D3082-05
QGND QGND
100nF
C21
100nF
C20
QGND
PG
VDD_Pullup
FLTb
QGND
470
R14
470
R15
FLTb2
QGND
470
R13
1VDD 2
OUTH
3
OUTL
4
GND
5IN-
6IN+
U4
UCC27511AQDBVRQ1
GD_IN
PGND
PGND PGND
4
7,8
1,2,3
Q4
5,6,
4
7,8
1,2,3
Q5
5,6,
4
7,8
1,2,3
Q6
5,6,
3 2 1
J9
A
A1
VCC
A2
B
B1
B2
REXT/CEXT
CLR
C1
C2
CEXT
GND D1
QD2
U5
SN74LVC1G123YZPR
R24 10k
10k
R25
100nF
16V
C26
QGND
QGND
VDD_Pullup
VDD_Pullup
10k
R29
100pF
C27
100pF
C23
100pF
C24
100pF
C25
G2
D3082-05
QGND QGND
21
DR1
21
DR2
Green
21
DG1
1 4
2 3
SW3
PGND
IN
21
OUT
3
GND
U3
TLV76050DBZR
VIN
QGND QGND
25V
1µF
C22
1
2 3
Q1
1
2 3
Q2
1
2 3
Q3
R34
R35
R36
3 2 1
J8
VDD_Pullup
VOUT
100nF
CT4
R22
10.0k
R23
20.0k
R26
49.9k
100k
R27
200k
R28
VDD_Pullup
GAT E1
GAT E1
GAT E2
GAT E2 GAT E3
GAT E3
R16 R17 R18 R19 R20 R21
PGND
TP24
VDD Pullup
VIN
+5V Reference
2
3
4
5
9
8
7
6
101 S1
76SB05ST
TP26
GD_EXT
TP25
VCC_EXT
VDD_Pullup
PGND
TP27
R22: 1 ms monoshot pulse,
R23: 2 ms monoshot pulse,
R26: 5 ms monoshot pulse,
R27: 10 ms monoshot pulse,
R28: 20 ms monoshot pulse,
Figure 3-2. TPS25984EVM eFuse Evaluation Board Schematic (Page 2)
Note
• To evaluate the performance of one TPS25984 eFuse at lower currents (< 55 A), RZ5, RZ6, RZ7, RZ8, and RZ9 resistors need to be
depopulated. Also R11 and R12 resistors must be populated to disable the secondary eFuse.
• The ground connections for the various components around the TPS25984 eFuses must be wired directly to each other and the GND pins
of respective eFuses. This must be followed by connecting them to the system ground at one point, as implemented using RZ1 and RZ4
resistors in the EVM schematic. Do not connect the various component grounds through the high current system ground line.
www.ti.com Schematic
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 5
Copyright © 2023 Texas Instruments Incorporated

4 General Configurations
4.1 Physical Access
Table 4-1 lists the TPS25984EVM eFuse Evaluation Board input and output connectors functionalities. Table 4-2
and Table 4-3 describe the availability of test points and the functionalities of the jumpers. Table 4-4 presents the
functions of the signal LEDs.
Table 4-1. Input and Output Connector Functionality
Connector Label Description
T1 VIN (+) Positive terminal for the input power to the EVM
T2 VOUT (+) Positive terminal for the output power from the EVM
T3 PGND (–) Negative terminal for the EVM (Common for both input and output)
Table 4-2. Test Points Description
Test Points Label Description
TP1 S1_P Kelvin sensing points to measure on-resistance: Primary Device (U1)
TP2 S1_N
TP3 S2_P Kelvin sensing points to measure on-resistance: Secondary Device
(U2)
TP4 S2_N
TP5 VIN Input Voltage
TP6 VOUT Output Voltage
TP7 MODE2 MODE selection: Secondary Device
TP8 FLTb2 Open-drain active low fault indication: Primary Device
TP9 VDD-PRI Controller input power: Primary Device
TP10 FLTb Open-drain active low fault indication: Primary Device
TP11 SWEN Open-drain signal to indicate and control power switch ON and OFF
status
TP12 TEMP Maximum device die temperature monitor analog voltage output with
two (2) TPS25984 eFuses in parallel
TP13 DVDT Start-up output slew rate control
TP14 ITIMER Overcurrent blanking timer: Primary Device
TP15 IMON Load current monitor and overcurrent and fast-trip thresholds during
steady state
TP16 ILIM2 Current limit and fast-trip threshold during start-up: Secondary Device
TP17 ILIM Current limit and fast-trip threshold during start-up: Primary Device
TP18 IREF Reference voltage for overcurrent and short-circuit protections, and
active current sharing blocks
TP19 MODE MODE selection: Primary Device
TP20 PG Open-drain active high power good indication
TP21 ITIMER2 Overcurrent blanking timer: Secondary Device
TP22 EN Active high enable input
TP23 VDD-SEC Controller input power: Secondary Device
TP24 VDD PULLUP 5 V pullup power supply generated using a LDO from VIN
TP25 VCC EXTERNAL External pullup power supply
TP26 GD EXTERNAL External gate signal for custom load transient
TP27 PGND Supply Ground
General Configurations www.ti.com
6TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

Table 4-2. Test Points Description (continued)
Test Points Label Description
QGND1 QGND
Device GroundG1 QGND
G2 QGND
Table 4-3. Jumper Descriptions and Default Positions
Jumper Label Description Default Jumper Position
J1 SWEN
1-2 Position: The SWEN pull-up supply is generated from VIN using
a Zener diode (RZ2 populated and RZ3 depopulated) or using a LDO
(RZ2 depopulated and RZ3 populated) 1-2
2-3 Position: The SWEN pin is connected to the ITIMER pin of the
Primary Device through a 100-kΩ resistor
J2 DVDT
1-2 Position sets the output slew rate to 1.8-V/ms
5-63-4 Position sets the output slew rate to 12-V/ms
5-6 Position sets the output slew rate to 1.2-V/ms
J3 ITIMER 1-2 Position sets the overcurrent blanking timer to 1.4-ms 3-4
3-4 Position sets the overcurrent blanking timer to 14-ms
J4 IMON 1-2 Position sets the circuit breaker threshold to 120-A with VIREF of 1-V 1-2
3-4 Position sets the circuit breaker threshold to 70-A with VIREF of 1-V
J5 ILIM
1-2 Position sets the inrush current limit to 38-A and the active current
sharing threshold to 59-A with VIREF of 1-V: Primary Device 1-2
3-4 Position sets the inrush current limit to 22-A and the active current
sharing threshold to 35-A with VIREF of 1-V: Primary Device
J6 IREF
1-2 Position sets the reference voltage for overcurrent, short-circuit
protection, and active current sharing blocks to 0.8-V 3-4
3-4 Position sets the reference voltage for overcurrent, short-circuit
protection, and active current sharing blocks to 1-V
J7 ILIM2
1-2 Position sets the inrush current limit to 38-A and the active current
sharing threshold to 59-A with VIREF of 1-V: Secondary Device 1-2
3-4 Position sets the inrush current limit to 22-A and the active current
sharing threshold to 35-A with VIREF of 1-V: Secondary Device
J8 VDD PULL-UP
POWER SUPPLY
1-2 Position provides the VDD pull-up supply from the external power
source 2-3
2-3 Position provides the VDD pull-up supply from the onboard 12-V to
5-V LDO
J9 EXTERNAL
GATE SIGNAL
1-2 Position provides the GATE signal to the MOSFETs (Q4 – Q6) from
the onboard mono-shot 1-2
2-3 Position provides the GATE signal to the MOSFETs (Q4 – Q6) from
the external signal generator
Table 4-4. LED Descriptions
LED Description
DG1 When ON, indicates that PG is asserted
DR1 When ON, indicates that FLTb is asserted
DR2 When ON, indicates that FLTb2 is asserted
4.2 Test Equipment
4.2.1 Power Supplies
One adjustable power supply with 0-V to 30-V output and 0-A to 200-A output current limit.
www.ti.com General Configurations
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 7
Copyright © 2023 Texas Instruments Incorporated

4.2.2 Meters
Minimum of a Digital Multi Meter (DMM) needed.
4.2.3 Oscilloscope
A DPO2024 or equivalent, three 10x voltage probes, and a DC current probe.
4.2.4 Loads
One resistive load or equivalent which can tolerate up to 200-A DC load at 24 V and capable of the output short.
5 Test Setup and Procedures
In this user's guide, the test procedure is described for TPS25984 eFuse. Make sure the evaluation board has
default jumper settings as shown in Table 5-1.
Table 5-1. Default Jumper Setting for TPS25984EVM eFuse Evaluation Board
J1 J2 J3 J4 J5 J6 J7 J8 J9
1-2 5-6 3-4 1-2 1-2 3-4 1-2 2-3 1-2
POWER
SUPPLY
Positive
Negative
LOAD
Positive Negative
Digital
Multimeter
PRINT
HELP
ALPHA
SHIFT
ENTER
RUN
D
GE RF I
A
JB KC L
7
M8 N9 O
D
GD GD G
D
G T 3 U
0
V. WXYZ
TAB
%UTILIZATION
HUB/MAU NIC
2
BNC
4Mb/s
Oscilloscope
Figure 5-1. TPS25984EVM Setup With Test Equipment
Follow these instructions before starting any test and repeat again before moving to the next test:
• Set the power supply output (VIN) to zero volts.
• Turn off the power supply.
• Adjust the jumper positions on EVM to the default configuration as shown in Table 5-1.
• Turn the power supply on and set the power supply output (VIN) to 12 V, 200 A, and keep the power supply
output disabled.
• Enable the power supply output so that the EVM gets the input power supply.
General Configurations www.ti.com
8TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

5.1 Hot Plug
Use the following instructions to measure the inrush current during hot plug event:
1. Configure the jumper J2 position to the desired slew rate mentioned in Table 4-3.
2. Configure the jumpers J5 and J7 positions to the desired current limits during start-up as mentioned in Table
4-3.
3. Configure the jumper J6 position to desired reference voltage for overcurrent protection and active current
sharing as specified in Table 4-3.
4. Connect a load of 1.2 Ω between VOUT (Connector T2) and PGND (Connector T3).
5. Connect the negative terminal of the power supply to connector T3.
6. Set the input supply voltage VIN to 12 V and current limit to 100 A. Enable the power supply.
7. Hot plug the positive terminal of the power supply at connector T1.
8. Observe the waveforms at VOUT (TP6) and input current using an oscilloscope to measure the slew rate
and rise time of the VOUT with a given input voltage of 12 V.
Figure 5-2 and Figure 5-3 show the examples of inrush current captured on the TPS25984EVM eFuse
evaluation board with two (2) devices in parallel during the hot plug event.
VIN
VOUT
ENABLE
Input
Current
VIN stepped up from 0 V to 12 V, COUT = 18.47 mF, CDVDT = 33
nF, and RLOAD = 1.2 Ω
Figure 5-2. TPS25984 eFuse Hot Plug Profile-1
VIN
VOUT
PG
Input
Current
VIN stepped up from 0 V to 12 V, COUT = 18.47 mF, CDVDT = 33
nF, and RLOAD = 0.37 Ω
Figure 5-3. TPS25984 eFuse Hot Plug Profile-2
5.2 Start-Up With Enable
Use the following instructions to power up the TPS25984 eFuse with ENABLE:
1. Configure the jumper J2 position to the desired slew rate mentioned in Table 4-3.
2. Configure the jumpers J5 and J7 positions to the desired current limits during start-up as mentioned in Table
4-3.
3. Configure the Jumper J6 position to desired reference voltage for overcurrent protection and active current
sharing as mentioned in Table 4-3.
4. Set the input supply voltage VIN to 12 V and current limit to 100 A.
5. Connect a load of 1.2 Ω between VOUT (Connector T2) and PGND (Connector T3).
6. Connect the input supply between VIN (Connector T1) and PGND (Connector T3).
7. Turn on the power supply by keeping the device disabled using the switch SW1.
8. Enable the eFuses by releasing the switch SW1.
9. Observe the waveform at VOUT (TP6) and input current using an oscilloscope to measure the slew rate and
rise time of the VOUT with a given input voltage of 12 V.
Figure 5-4 and Figure 5-5 show the start-up profile of TPS25984 eFuse with ENABLE using two (2) devices in
parallel.
www.ti.com Test Setup and Procedures
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 9
Copyright © 2023 Texas Instruments Incorporated

VIN
VOUT
ENABLE
Input
Current
VIN = 12 V, EN stepped up from 0 V to 3 V, COUT = 18.47 mF,
RLOAD = 1.2 Ω, and CDVDT = 33 nF
Figure 5-4. TPS25984 eFuse Start-Up Profile With
ENABLE
VOUT
VILIM_PRIMARY
VILIM_SECONDARY
IIN_PRIMARY
IIN_SECONDARY
Input Current
IIN_PRIMARY + IIN_SECONDARY
VIN = 12 V, EN stepped up from 0 V to 3 V, RILIM = 400 Ω,
RLIMI2 = 400 Ω, RIREF = 40.2 kΩ, COUT = 25.27 mF, RLOAD = 0.5
Ω, and CDVDT = 22 nF
Figure 5-5. Start-Up Profile With ENABLE: Current
Sharing Between Two (2) TPS25984 eFuses
5.3 Difference Between Current Limit and DVDT Based Start-Up Mechanisms
Use the following instructions to perform the start-up with current limit test:
1. Configure the jumper J2 position to the desired slew rate mentioned in Table 4-3.
2. Configure the jumpers J5 and J7 positions to the desired current limits during start-up as mentioned in Table
4-3.
3. Configure the Jumper J6 position to desired reference voltage for overcurrent protection and active current
sharing as mentioned in Table 4-3.
4. Set the input supply voltage VIN to 12 V and current limit to 100 A.
5. Connect a load of 0.9 Ω between VOUT (Connector T2) and PGND (Connector T3).
6. Connect the input supply between VIN (Connector T1) and PGND (Connector T3).
7. Turn on the power supply by keeping the device disabled using the switch SW1.
8. Enable the eFuse by releasing the switch SW1.
9. Observe the waveform at VOUT (TP6) and input current using an oscilloscope. The main intention of this
experiment is to observe the output voltage and input current profiles and time required to complete the
inrush with two different ILIM set points having all other test conditions identical. The inrush current hits the
current limit set point in one case, but does not in the next.
Figure 5-6 and Figure 5-7 show the difference between the current limit and DVDT based start-up mechanisms
on the TPS25984EVM eFuse evaluation board having two (2) devices in parallel for RILIM of 680, RLIM2 of 680 Ω,
RILIM of 402, and RLIM2 of 402 Ω.
Test Setup and Procedures www.ti.com
10 TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

VIN
VOUT
PG
Input
Current
VIN = 12 V, EN stepped up from 0 V to 3 V, RILIM = 680 Ω,
RLIMI2 = 680 Ω, RIREF = 40.2 kΩ, COUT = 18.47 mF, RLOAD = 0.9
Ω, and CDVDT = 33 nF
Figure 5-6. Start-Up With Current Limit Response
of TPS25984 eFuse
VIN
VOUT
PG
Input
Current
VIN = 12 V, EN stepped up from 0 V to 3 V, RILIM = 402 Ω,
RILIM2 = 402 Ω, RIREF = 40.2 kΩ, COUT = 18.47 mF, RLOAD = 0.9
Ω, and CDVDT = 33 nF
Figure 5-7. Start-Up With Output Slew Rate Control
(Only) Response of TPS25984 eFuse
5.4 Power Up Into Short
Use the following instructions to perform the power up into short test:
1. Set the input supply voltage VIN to 12 V and current limit to 100 A. Connect the supply between VIN
(Connector T1) and PGND (Connector T3) and keep the power supply OFF.
2. Short the output of the EVM. For example, VOUT (Connector T2) to PGND (Connector T3) through a short
and thick cable to make sure the short-circuited path impedance is minimum as possible.
3. Configure the Jumper J6 position to desired reference voltage for overcurrent protection and active current
sharing as mentioned in Table 4-3.
4. Configure the jumpers J5 and J7 positions to the desired current limits during start-up as mentioned in Table
4-3.
5. Keep the TPS25984 eFuses disabled by pushing the switch SW1.
6. Turn ON the power supply.
7. Enable the TPS25984 eFuse by releasing the switch SW1.
Figure 5-8 and Figure 5-9 show the test waveforms of power up into output short on the TPS25984EVM eFuse
Evaluation Board with two (2) devices in parallel.
Note
During power up into short, a thermal fold-back results in the current flowing through the device being
less than the calculated value of the current limit during start-up.
www.ti.com Test Setup and Procedures
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 11
Copyright © 2023 Texas Instruments Incorporated

VIN
VOUT
ENABLE
Input
Current
VIN = 12 V, EN stepped up from 0 V to 3 V, RILIM = 402 Ω,
RILIM2 = 402 Ω, RIREF = 40.2 kΩ, CITIMER = 22 nF, and OUT
shorted to PGND
Figure 5-8. Power Up Into Output Short Response
of TPS25984 eFuse
VOUT
VILIM_PRIMARY
VILIM_SECONDARY
IIN_PRIMARY
IIN_SECONDARY
Input Current
IIN_PRIMARY + IIN_SECONDARY
VIN = 12 V, EN stepped up from 0 V to 3 V, RILIM2 = 402 Ω,
RIREF = 40.2 kΩ, RIREF = 40.2 kΩ, CITIMER = 22 nF, and OUT
shorted to PGND
Figure 5-9. Power Up Into Output Short Response
in TPS25984EVM: Current Sharing Between Two
(2) eFuses
5.5 Overvoltage Lockout
Use the following instructions to perform the overvoltage protection test:
1. Set the input supply voltage VIN to 12 V and current limit to 100 A. Apply the supply between VIN
(Connector T1) and PGND (Connector T3) and enable the power supply.
2. Apply a load of 1.2 Ω between VOUT (Connector T2) and PGND (Connector T3).
3. Increase the input supply VIN from 12 V to 18 V and observe the waveforms using an oscilloscope.
Figure 5-10 shows overvoltage lockout response of TPS25984 eFuse on TPS25984EVM eFuse Evaluation
Board.
Note
The input TVS diodes must be removed during the overvoltage protection test. Make sure to put the
diodes back after this experiment.
VIN
VOUT
PG
Load
Current
VIN Ramped Up from 12 V to 18 V, COUT = 470 μF, and RLOAD = 1.2 Ω
Figure 5-10. Overvoltage Lockout Response of TPS25984 eFuse
Test Setup and Procedures www.ti.com
12 TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

5.6 Transient Overload Performance
Use the following instructions to observe the transient overload performance:
1. Configure the Jumper J3 to an appropriate position to obtain required overcurrent blanking period (tTIMER) as
per Table 4-3.
2. Configure the Jumper J6 position to desired reference voltage for overcurrent protection and active current
sharing as mentioned in Table 4-3.
3. Configure the Jumper J4 in a good position to set required circuit breaker threshold (IOCP) as per Table 4-3.
4. Connect an electronic load (capable of applying load transients of up to 200 A) between VOUT (Connector
T2) and PGND (Connector T3) and leave the load disabled.
5. Set the input supply voltage VIN to 12 V and current limit of 200 A.
6. Connect the power supply between VIN (Connector T1) and PGND (Connector T3) and enable the power
supply.
7. Now apply an overload using the electronic load in the range of IOCP < ILOAD < 2 × IOCP for a time duration
less than tTIMER decided by using jumper J3.
8. Observe the waveforms using an oscilloscope.
Figure 5-11 and Figure 5-12 show transient overload performance of TPS25984 eFuse on TPS25984EVM
eFuse evaluation board with two (2) devices in parallel.
VIN
VOUT
TIMER
Load
Current
VIN = 12 V, CITIMER = 22 nF, COUT = 470 μF, RIMON = 1.1 ∥ 1.1
kΩ, RIREF = 40.2 kΩ, IOUT ramped from 100 A to 175 A then
100 A within 10 ms
Figure 5-11. Transient Overload Performance of
TPS25984 eFuse
VOUT
VILIM_PRIMARY
VILIM_SECONDARY
IIN_PRIMARY
IIN_SECONDARY
Input Current
IIN_PRIMARY + IIN_SECONDARY
VIN = 12 V, CITIMER = 22 nF, COUT = 470 μF, RIMON = 1.1 ∥ 1.1
kΩ, RIREF = 40.2 kΩ, IOUT ramped from 98 A to 180 A then 98 A
within 10 ms
Figure 5-12. Transient Overload Performance in
TPS25984EVM: Current Sharing Between Two (2)
eFuses
www.ti.com Test Setup and Procedures
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 13
Copyright © 2023 Texas Instruments Incorporated

5.7 Overcurrent Event
Use the following instructions to perform the overcurrent test on TPS25984 eFuse:
1. Configure the Jumper J3 to an appropriate position to obtain required overcurrent blanking period (tTIMER) as
per Table 4-3.
2. Configure the Jumper J6 position to desired reference voltage for overcurrent protection and active current
sharing as mentioned in Table 4-3.
3. Configure the Jumper J4 in a good position to set required circuit breaker threshold (IOCP) as per Table 4-3.
4. Connect an electronic load (capable of applying load transients of up to 200 A) between VOUT (Connector
T2) and PGND (Connector T3) and leave the load disabled.
5. Set the input supply voltage VIN to 12 V and current limit of 200 A.
6. Connect the power supply between VIN (Connector T1) and PGND (Connector T3) and enable the power
supply.
7. Now apply an overload using the electronic load in the range of IOCP < ILOAD < 2 × IOCP for a time duration
more than tTIMER decided by using jumper J3.
8. Observe the waveforms using an oscilloscope.
Figure 5-13 and Figure 5-14 show the circuit breaker response of TPS25984 eFuse on TPS25984EVM eFuse
evaluation board with two (2) devices in parallel.
TIMER
Load
Current
VOUT
VIN
VIN = 12 V, CITIMER = 22 nF, COUT = 470 μF, RIMON = 1.1 ∥ 1.1
kΩ, RIREF = 40.2 kΩ, IOUT ramped from 100 A to 150 A for 20
ms
Figure 5-13. Overcurrent Performance of TPS25984
eFuse-1
TIMER
Load
Current
FLTb
PG
VIN = 12 V, CITIMER = 22 nF, COUT = 470 μF, RIMON = 1.1 ∥ 1.1
kΩ, RIREF = 40.2 kΩ, IOUT ramped from 100 A to 150 A for 20
ms
Figure 5-14. Overcurrent Performance of TPS25984
eFuse-2
5.8 Provision to Apply Load Transient and Overcurrent Event Using an Onboard Switching
Circuit
The TPS25984EVM provides an add-on circuit to facilitate load transients and persistent overcurrent events. The
implementation consists of three (3) low side MOSFETs (Q4, Q5, and Q6) and a monoshot gate driver circuit
(U4 and U5) as well as six (6) onboard load resistors of 1 Ω each (R16 to R21) in parallel. Using a single pole
single through (SPST) switch (S1), the monoshot gate driver generates gate signals of 1-ms, 2-ms, 5-ms, 10-ms,
and 20-ms durations. By doing this, the low side MOSFETs (Q4, Q5, and Q6) are turned on for that specific
duration, creating a load transient in addition to the steady-state load. Use the following instructions to apply a
load transient or persistent overcurrent event using this onboard switching circuit:
1. Configure the Jumper J3 to an appropriate position to obtain required overcurrent blanking period (tTIMER) as
per Table 4-3.
2. Configure the Jumper J6 position to desired reference voltage for overcurrent protection and active current
sharing as mentioned in Table 4-3.
3. Configure the Jumper J4 in an acceptable position to set required circuit breaker threshold (IOCP) as per
Table 4-3.
Test Setup and Procedures www.ti.com
14 TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

4. Set the input supply voltage VIN to 12 V and current limit to 200 A.
5. Connect the power supply between VIN (Connector T1) and PGND (Connector T3), then enable the power
supply.
6. Apply a steady-state load between VOUT (Connector T2) and PGND (Connector T3).
7. Use the single pole single through (SPST) switch (S1) to configure the transient load turn on duration.
8. Press the switch SW3 to turn on the Q5, Q6, and Q7 MOSFETs, which creates a load transient of 72 A
(typical) between VOUT and PGND with 12-V output.
9. Observe the waveforms of VOUT (TP6), MOSFET GATE (J9), and input current using an oscilloscope.
Another option is to apply a custom load transient using an external function generator, connected between
TP26 and TP27, and the shunt of jumper J9 set to "2-3".
CAUTION
In that case, make sure to limit the transient load current magnitude to a safe level for reliable
operation of the load resistors (R16 to R21) based on their maximum permissible peak pulse power
vs pulse duration plot.
Figure 5-15 and Figure 5-16 show the test waveforms of transient overload and persistent overload events
respectively using the on-board switching circuit.
VOUT
GATE signal to
Q7, Q8, and Q9
Input Current
TIMER
VIN = 12 V, CITIMER = 22 nF, COUT = 470 μF, RIMON = 1.1
∥ 1.1 kΩ, RIREF = 40.2 kΩ, IOUT (Steady-State) = 100 A, and
IOUT (Transient) = 69 A for 9 ms
Figure 5-15. Transient Overload Performance
in TPS25984EVM Using the Onboard Switching
Circuit
VOUT
GATE signal to
Q7, Q8, and Q9
Input Current
TIMER
VIN = 12 V, CITIMER = 22 nF, COUT = 470 μF, RIMON = 1.1
∥ 1.1 kΩ, RIREF = 40.2 kΩ, IOUT (Steady-State) = 100 A, and
IOUT (Transient) = 69 A for 18 ms
Figure 5-16. Persistent Overload Performance
in TPS25984EVM Using the Onboard Switching
Circuit
www.ti.com Test Setup and Procedures
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 15
Copyright © 2023 Texas Instruments Incorporated

5.9 Output Hot Short
Use the following instructions to perform the output hot short test:
1. Set the input supply voltage VIN to 12 V and connect the power supply between VIN (Connector T1) and
PGND (Connector T3).
2. Turn ON the power supply.
3. Short the output of the device for example, VOUT (Connector T2) to PGND (Connector T3) through a shorter
cable, which is just enough to insert a 150 A current probe.
4. Observe the waveforms using an oscilloscope.
Figure 5-17 shows the test waveforms of output hot short on the TPS25984EVM with two (2) TPS25984 eFuses
in parallel.
VOUT
VIN
Short-circuit
Current
VIN = 12 V, RIMON = 1.1 ∥ 1.1 kΩ, RIREF = 40.2 kΩ, and COUT = 10 µF
Figure 5-17. Output Hot Short Response of TPS25984 eFuse
Make sure there is sufficient input capacitor to eliminate voltage dips at the input. A combination
of electrolytic and ceramic capacitors are preferred. With these capacitors, a large current can be
provided for a short period of time during short-circuit.
Note
Obtaining repeatable and similar short-circuit testing results is very difficult. The following contributes
to the variation in results:
• Source bypassing
• Input leads
• Board layout
• Component selection
• Output shorting method
• Relative location of the short
• Instrumentation
The actual short exhibits a certain degree of randomness because the short microscopically bounces and arcs.
Make sure that configuration and methods are used to obtain realistic results. Hence, do not expect to see
waveforms exactly like the waveforms in this user's guide because every setup is different.
Test Setup and Procedures www.ti.com
16 TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

5.10 Quick Output Discharge (QOD)
Use the following instructions to observe the Quick Output Discharge (QOD) functionality:
1. Set the input supply voltage VIN to 12 V and current limit to 10 A. Turn ON the power supply.
2. Use the switch SW1 to connect the EN/UVLO pin to ground to do power cycling.
3. Use the switch SW2 to enable the QOD by making the voltage at EN/UVLO pin in the range of 0.8 V–1.1 V
with the input voltage of 9.8 V–13.5 V.
4. Observe the waveforms of VIN (TP5), VOUT (TP6), PG (TP20), and EN (TP22) using an oscilloscope.
In Figure 5-18, the turn-off performance of the TPS25984 eFuse with QOD enabled is shown, whereas Figure
5-19 illustrates the turn-off performance with QOD disabled on the TPS25984EVM eFuse evaluation board.
EN
VOUT
VIN
PG
VIN = 12 V, COUT = 470 µF, and EN Pulled Low to 0.8 V
Figure 5-18. QOD Enabled on TPS25984 eFuse
EN
VOUT
VIN
PG
VIN = 12 V, COUT = 470 µF, and EN Pulled Low to 0 V
Figure 5-19. QOD Disabled on TPS25984 eFuse
5.11 Thermal Performance of TPS25984EVM
Use the following instructions to evaluate the thermal performance of TPS25984EVM:
1. Configure the Jumper J6 position to desired reference voltage (VIREF) for overcurrent protection and active
current sharing as mentioned in Table 4-3. The "3-4" position of the jumper J6 is selected in this experiment,
which makes VIREF as 1 V (typical).
2. Configure the jumper J4 in a good position to set required circuit breaker threshold (IOCP) as per Table 4-3.
The "1-2" position of the jumper J4 is selected in this experiment, which makes IOCP as 120 A (typical) with
VIREF as 1 V (typical).
3. Set the input supply voltage VIN to 12 V and current limit of 115 A.
4. Connect the power supply between VIN (Connector T1) and PGND (Connector T3) and enable the power
supply.
5. Now apply a load of 110 A (DC) between VOUT (Connector T2) and PGND (Connector T3) for half an hour
or more to reach the thermal equilibrium point.
6. Capture the thermal image of the EVM or monitor the voltage at TEMP (TP12) pin using a digital multimeter.
Voltage at the TEMP (VTEMP) pin reports the maximum die temperature between two (2) TPS25984 eFuses,
which can be obtained using Equation 1.
TJ°C= 25 + VTEMP mV − 677.6
2.72 mV/°C(1)
www.ti.com Test Setup and Procedures
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 17
Copyright © 2023 Texas Instruments Incorporated

VIN = 12 V, IOUT = 110 A, TA = 25°C, and no external air flow
Figure 5-20. Thermal Performance of TPS25984EVM
Figure 5-20 shows the thermal performance of TPS25984EVM with two (2) TPS25984 eFuses in parallel.
Test Setup and Procedures www.ti.com
18 TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

6 EVAL Board Assembly Drawings and Layout Guidelines
6.1 PCB Drawings
Figure 6-1 and Figure 6-2 show the component placements of the EVM. A pictorial representation of the
TPS25984EVM PCB layers can be found in Figure 6-3 to Figure 6-10.
RECEPTACLE
ILIM
TP12
S1
J1
TP9
6
TP13
C2
9
RZ9
C9 RZ4
2
U2
R5 R12
EN
3
4
2
RM4
IMON
Q6
J7
R36 TP16 DG1
RL2
R35
J6
TP18
TP3
J3 J8
D2
TP4
DVDT
TP1 CTEMP1
CT1 RL1 RM7
TP11
R4
TP10
U5
SW3
TP17
2ms
1ms
TP26
TP19
10
TP24
C20
G1
C3
C12
C1
RM1
RZ1
0.50in
J2
QGND
C6
C4
U1
25
32
C14
J4
SW1
SW2
CO1 CO2
QGND
T2
TP8
1
5
5ms
CT4
GD_EXT
2
VIN
T1
MODE
SWEN
TP27
VIN
U3
C21
VCC_EXT
+5V
RZ2
S2_N
QGND
S1_P
RZ6 C19
C10
RZ8
SWEN
CD4
C5
RF1
25
32
RL6
C13
IMON
RM5
TP15
TP22
D3
TP6
VOUT
TP20
QGND1
G2
+
Q5
C25
ILIM2
RL3
ILIM2
R14
T5
C24
FLTb2
R13
R15
R34
C23
IREF
TP7
GD_EXT
GD_IN
RL5 RL4
4
U4
VDD_Pullup
TP5
CT3
VDD_Pullup
PGND
T3
1.14in C D3
TP2
RM2
CD1 ITIMER2
CD2 R9
VDD-SEC
R11
R16
DR2
RF3 DR1
FLTb
RF2
ITIMER
VDD_Pullup
PGND
C16
C11
TP21
TP25
C17
IREF
20ms
10ms
R24
C27
C22
ILIM
TP14
S2_P S1_N
DVDT
ITIMER
VDD-PRI
TEMP TP23
VCC_EXT
Q4
VOUT
C18
PG MODE2
QGND
R29
R6
CT2
R18R17
REV A
For evaluation only; not FCC approved for resale.
100A Maximum DC100A Maximum DC
PSIL196A TPS25984EVM
Do not touch! Caution Hot surface.
4.86in
3.34in
Figure 6-1. TPS25984EVM Board: Top Assembly
C7
Q1
D1
R2
R7
CM1
R3
Q2
CF1
R23
R22
R25
R8
RZ5
C15
R19
R21
Q3
R27
R26
R28
C26
RZ3
R1
R10
C8
RM6
RM3
D4
D5
R20
OCT 2022
RZ7
305-PD-22-0849
Figure 6-2. TPS25984EVM Board: Bottom
Assembly
4.86in
3.34in
ILIM
TP12
S1
J1
TP9
6
TP13
9
2
EN
3
4
2
IMON
J7
TP16
J6
TP18
TP3
J3 J8
TP4
DVDT
TP1
TP11
TP10
TP17
2ms
1ms
TP26
TP19
10
TP24
G1
0.50in
J2
QGND
25
32
J4
CO2
QGND
T2
TP8
1
5
5ms
GD_EXT
2
VIN
T1
MODE
SWEN
TP27
VIN
VCC_EXT
+5V
S2_N
QGND
S1_P
SWEN
25
32
IMON
TP15
TP22
TP6
VOUT
TP20
G2
+
ILIM2
ILIM2
T5
FLTb2
IREF
TP7
GD_EXT
GD_IN
4
VDD_Pullup
TP5
VDD_Pullup
PGND
T3
1.14in
TP2
ITIMER2
VDD-SEC
FLTb
ITIMER
VDD_Pullup
PGND
TP21
TP25
IREF
20ms
10ms
ILIM
TP14
S2_P S1_N
DVDT
ITIMER
VDD-PRI
TEMP TP23
VCC_EXT
VOUT
PG MODE2
QGND
REV A
100A Maximum DC100A Maximum DC
Contact may cause burns.
PSIL196A TPS25984EVM
Do not touch! Caution Hot surface.
Figure 6-3. TPS25984EVM Board: Top Layer
OCT 2022
305-PD-22-0849
Figure 6-4. TPS25984EVM Board: Bottom Layer
www.ti.com EVAL Board Assembly Drawings and Layout Guidelines
SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
TPS25984 Evaluation Module (EVM) 19
Copyright © 2023 Texas Instruments Incorporated

4.86in
3.34in
D
9
ILIM
A
2
9
6
2
E
N
3
4
2
IMON
DVDT
2ms
1
ms 1 0
0
.50in
QGND
25
32
QGND
1
5
5ms
2
VIN
MODE
SWEN
+5V
S2_N
QGND
S1_P
SWEN
25
32
IMON ILIM2
ILIM2 FLTb2
IREF
GD_EXT
GD_IN
4
VDD_Pullup VDD_Pullup
PGND 1.14in
ITIMER2
VDD-SEC
FLTb
ITIMER
VDD_Pullup
IREF
20ms
10ms
ILIM
S2_P S1_N
DVDT
ITIMER
VDD-PRI
TEMP
VCC_EXT
VOUT
PG MODE2
QGND
REV A
100A Maximum DC100A Maximum DC
Contact may cause burns.
PSIL196A TPS25984EVM
Do not touch! Caution Hot surface.
Figure 6-5. TPS25984EVM Board: Layer 2 (Power)
4.86in
3.34in
D
9
ILIM
A
2
9
6
2
E
N
3
4
2
IMON
DVDT
2ms
1
ms 1 0
0
.50in
QGND
25
32
QGND
1
5
5ms
2
VIN
MODE
SWEN
+5V
S2_N
QGND
S1_P
SWEN
25
32
IMON ILIM2
ILIM2 FLTb2
IREF
GD_EXT
GD_IN
4
VDD_Pullup VDD_Pullup
PGND 1.14in
ITIMER2
VDD-SEC
FLTb
ITIMER
VDD_Pullup
IREF
20ms
10ms
ILIM
S2_P S1_N
DVDT
ITIMER
VDD-PRI
TEMP
VCC_EXT
VOUT
PG MODE2
QGND
REV A
100A Maximum DC100A Maximum DC
Contact may cause burns.
PSIL196A TPS25984EVM
Do not touch! Caution Hot surface.
Figure 6-6. TPS25984EVM Board: Layer 3 (Power)
4.86in
3.34in
D
9
ILIM
A
2
9
6
2
E
N
3
4
2
IMON
DVDT
2ms
1
ms 1 0
0
.50in
QGND
25
32
QGND
1
5
5ms
2
VIN
MODE
SWEN
+5V
S2_N
QGND
S1_P
SWEN
25
32
IMON ILIM2
ILIM2 FLTb2
IREF
GD_EXT
GD_IN
4
VDD_Pullup VDD_Pullup
PGND 1.14in
ITIMER2
VDD-SEC
FLTb
ITIMER
VDD_Pullup
IREF
20ms
10ms
ILIM
S2_P S1_N
DVDT
ITIMER
VDD-PRI
TEMP
VCC_EXT
VOUT
PG MODE2
QGND
REV A
100A Maximum DC100A Maximum DC
Contact may cause burns.
PSIL196A TPS25984EVM
Do not touch! Caution Hot surface.
Figure 6-7. TPS25984EVM Board: Layer 4 (Signal)
4.86in
3.34in
D
9
ILIM
A
2
9
6
2
E
N
3
4
2
IMON
DVDT
2ms
1
ms 1 0
0
.50in
QGND
25
32
QGND
1
5
5ms
2
VIN
MODE
SWEN
+5V
S2_N
QGND
S1_P
SWEN
25
32
IMON ILIM2
ILIM2 FLTb2
IREF
GD_EXT
GD_IN
4
VDD_Pullup VDD_Pullup
PGND 1.14in
ITIMER2
VDD-SEC
FLTb
ITIMER
VDD_Pullup
IREF
20ms
10ms
ILIM
S2_P S1_N
DVDT
ITIMER
VDD-PRI
TEMP
VCC_EXT
VOUT
PG MODE2
QGND
REV A
100A Maximum DC100A Maximum DC
Contact may cause burns.
PSIL196A TPS25984EVM
Do not touch! Caution Hot surface.
Figure 6-8. TPS25984EVM Board: Layer 5 (Signal)
EVAL Board Assembly Drawings and Layout Guidelines www.ti.com
20 TPS25984 Evaluation Module (EVM) SLVUCH6A – JULY 2023 – REVISED NOVEMBER 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated