Texas Instruments DS160PT801X16EVM User manual

User’s Guide
DS160PT801X16EVM Riser Card Evaluation Module
ABSTRACT
The DS160PT801X16EVM is a 16-lane PCIe riser card board intended to be used for evaluation of the
Texas Instruments DS160PT801 PCIe Gen4 retimer. The EVM uses the 1x16 Card Electromechanical (CEM)
connector to enable quick system testing in a standard x16 socket and a standard PCIe endpoint. The evaluation
board may be used with the SigCon Architect software program to provide register control and status information
from the DS160PT801 devices. Contact a local Texas Instruments representative to obtain the SigCon Architect.
Figure 1-1. DS160PT801 EVM
Table of Contents
1 EVM Control and Configuration Information........................................................................................................................3
1.1 Retimer Pin Controls.......................................................................................................................................................... 3
1.2 USB-to-SMBus Interface....................................................................................................................................................4
1.3 PCIe PRSNT# Signal Control and Configuration............................................................................................................... 5
1.4 PCIe Reference Clock Control and Configuration..............................................................................................................5
2 EVM Power.............................................................................................................................................................................. 7
2.1 EVM Current Sensing........................................................................................................................................................ 8
3 SigCon Architect GUI............................................................................................................................................................. 9
3.1 Setup and Installation.........................................................................................................................................................9
3.2 Configuration Page.......................................................................................................................................................... 10
3.3 Low-Level Page................................................................................................................................................................11
3.4 EEPROM Page................................................................................................................................................................ 12
3.5 Control Panel................................................................................................................................................................... 13
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3.6 High-Level Page...............................................................................................................................................................14
3.7 Diagnostic Page............................................................................................................................................................... 18
3.8 Eye Monitor Page.............................................................................................................................................................19
4 PCB Material Information.....................................................................................................................................................20
4.1 DS160PT801 PCB Design............................................................................................................................................... 20
4.2 DS160PT801 PCB Stackup............................................................................................................................................. 20
4.3 DS160PT801 PCB Power Distribution............................................................................................................................. 20
4.4 DS160PT801 Local Decoupling....................................................................................................................................... 22
5 DS160PT801X16EVM Schematic......................................................................................................................................... 24
6 Hardware BOM...................................................................................................................................................................... 33
7 Revision History................................................................................................................................................................... 39
List of Figures
Figure 1-1. DS160PT801 EVM.................................................................................................................................................... 1
Figure 1-1. DS160PT801X16EVM EEPROM Control and Connection....................................................................................... 3
Figure 1-2. DS160PT801X16EVM SMBus Interface Connections.............................................................................................. 5
Figure 1-3. DS160PT801X16EVM PCIe PRSNT# Controls........................................................................................................ 5
Figure 1-4. Common Clock Topology Example........................................................................................................................... 6
Figure 1-5. Independent Clock Topology Example...................................................................................................................... 6
Figure 2-1. 1.17-V Power Supply Pin Controls............................................................................................................................ 7
Figure 2-2. DS160PT801X16EVM Power Network..................................................................................................................... 7
Figure 2-3. DS160PT801X16EVM Current Sense Measurement Locations............................................................................... 8
Figure 3-1. Configuration Page Screenshot.............................................................................................................................. 10
Figure 3-2. Low-Level Page Screenshot....................................................................................................................................11
Figure 3-3. EEPROM Page Screenshot.................................................................................................................................... 12
Figure 3-4. Control Panel Screenshot....................................................................................................................................... 13
Figure 3-5. High-Level Page Screenshot...................................................................................................................................14
Figure 3-6. High-Level Page – Device Status Screenshot........................................................................................................ 15
Figure 3-7. High Level Page – Device Status (Active Link) Screenshot....................................................................................16
Figure 3-8. High-Level – Rx EQ/DFE Page............................................................................................................................... 16
Figure 3-9. High-Level Page Tx FIR.......................................................................................................................................... 17
Figure 3-10. Diagnostic Page Screenshot................................................................................................................................. 18
Figure 3-11. Eye Monitor Page Screenshot...............................................................................................................................19
Figure 4-1. DS160PT801X16EVM PCB Stackup...................................................................................................................... 20
Figure 4-2. Layer 3 High-Speed Analog Analog Power Rails....................................................................................................21
Figure 4-3. Layer 4 Digital Power Rails..................................................................................................................................... 21
Figure 4-4. Layer 9 and 10 Power Distribution.......................................................................................................................... 22
Figure 4-5. Decoupling Solution Frequency Response............................................................................................................. 22
Figure 4-6. PCB Top Layer........................................................................................................................................................ 23
Figure 5-1. Schematic – Cover Sheet........................................................................................................................................24
Figure 5-2. Schematic – High Speed.........................................................................................................................................25
Figure 5-3. Schematic – Control................................................................................................................................................ 26
Figure 5-4. Schematic – Supply Voltage Regulators................................................................................................................. 27
Figure 5-5. Schematic – Retimer 1 Current Sense and Decoupling..........................................................................................28
Figure 5-6. Schematic – Retimer 0 Current Sense and Decoupling..........................................................................................29
Figure 5-7. Schematic – PCIe Gen4 Clock Generation............................................................................................................. 30
Figure 5-8. Schematic – PCIe Gen4 Clock Buffer..................................................................................................................... 31
Figure 5-9. Schematic – MSP430 Microcontroller..................................................................................................................... 32
List of Tables
Table 1-1. Default EVM Jumper Positions................................................................................................................................... 4
Table 6-1. DS160PT801X16EVM Bill of Materials.....................................................................................................................33
Trademarks
Windows® is a registered trademark of Microsoft Corporation.
All trademarks are the property of their respective owners.
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1 EVM Control and Configuration Information
The DS160PT801X16 EVM uses an AT24C16 EEPROM to store retimer configuration settings. This EEPROM
is pre-loaded with an EEPROM image with various settings to enable quick system bring-up for common-clock
PCIe topologies.
Custom EEPROM images for compliance or separate reference independent spread (SRIS) clock topologies
may be created and written to the EEPROM using the SigCon Architect software or by using the DS160PT801
I2C interface. For additional information on EEPROM programming through the I2C interface of the
DS160PT801, please refer to the DS160PT801 EEPROM Programming Guide.1
Figure 1-1. DS160PT801X16EVM EEPROM Control and Connection
The EE-PT801 connect headers (J21 and J24) allow for quick connection or disconnection of the EEPROM
serial interface. Additional test access points are provided at header J23 to allow the user to monitor EEPROM
activity. The J25 header may be used to Write Protect the EEPROM and prevent any changes to the current
EEPROM image. When the EEPROM is disconnected, the retimer will completely rely on the pin-strap settings
for configuration, which may be modified using the shunt jumpers included with the EVM.
1.1 Retimer Pin Controls
The DS160PT801X16EVM is pre-configured on power-up to use the retimer configuration stored in the onboard
EEPROM. These settings may be adjusted by using the pin controls through the onboard headers and jumpers.
There are 3 types of headers on the EVM for pin-controls: 2-level, 4-level, and 5-level headers. This section
highlights the pin controls and how to adjust them. Additional information about pin settings is provided in the
DS160PT801 data sheet.
Jumper options for 2-Level, 3-pin headers are as follows:
• No jumper on header pins – Input floating
• Shunt jumper at pins 1-2 – Input to 1.8 V or 3.3V
• Shunt jumper at pins 2-3 – Input to GND
Jumper options for 4-Level, 6-pin headers are as follows:
• No jumper on header pins – Input floating
• Shunt jumper at pins 1-2 – Inputs to 1.8 V
• Shunt jumper at pins 3-4 – Inputs 10 kΩ to GND
• Shunt jumper at pins 5-6 – Inputs to GND
1The DS160PT801 EEPROM Programming Guide is available upon request.
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Jumper options for 5-Level, 8-pin headers are as follows:
• No jumper on header pins – Input floating
• Shunt jumper at pins 1-2 – Inputs to 1.8 V
• Shunt jumper at pins 3-4 – Inputs 10 kΩ to 1.8 V
• Shunt jumper at pins 5-6 – Inputs 10 kΩ to GND
• Shunt jumper at pins 7-8 – Inputs to GND
The EVM will have many of the headers pre-populated with jumpers out of the box. The default jumper positions
represent the most common positions for the jumpers used during evaluation and testing. Table 1-1 lists the
default position for the jumpers.
Table 1-1. Default EVM Jumper Positions
Header Designator Jumper Position Description
J1 1-2 Disable CDCE6214 SSC clocking
J2 1-2 Disable CDCE6214 clock output
J4 2-3 Disable CDCE6214 EE_SEL
J6 7-8 Set retimer U2 mode to dual-chip link-width manager
J7 5-6 Set retimer U2 SMBus address to 0x20
J8 5-6 Set retimer U2 SMBus address to 0x20
J11 5-6 Set retimer U3 mode to dual-chip link-width follower
J12 3-4 Set retimer U3 SMBus address to 0x22
J13 5-6 Set retimer U3 SMBus address to 0x22
J16 2-3 Assert CLKREQ#, 1 K pulldown to GND
J18 1-2 Deassert Port 0 PRTRST#, 1 K pullup to 1.8 V
J20 1-2 Deassert Port 1 PRTRST#, 1 K pullup to 1.8 V
J21 1-2 Connect EE_CLK to retimer, enable EEPROM
J24 1-2 Connect EE_DAT to retimer, enable EEPROM
J45 1-2 Endpoint control of PRSNT#2 PCIe signal
J46 1-2 Endpoint control of PRSNT#3 PCIe signal
J47 1-2 Endpoint control of PRSNT#1 PCIe signal
J48 1-2 Endpoint control of PRSNT#4 PCIe signal
J49 2-3 Use clock source from CEM connector for REFCLK
J50 2-3 Disable clock output from LMK00334
J58 3-4 Set voltage regulator to output 1.15 V
J59 1-2 Enable U16 voltage regulator with 12 V supply
1.2 USB-to-SMBus Interface
The DS160PT801X16EVM uses an onboard MSP430 microcontroller to create USB-to-SMBus interface. The
USB-to-SMBus interface is intended to be used with Texas Instruments software like SigCon Architect to
communicate to the DS160PT801 retimers.
When using the default jumper configuration listed in Table 1-1, the DS160PT801 at location U2 is setup for
SMBus address 0x20 (8-bit address). The DS160PT801 at location U3 is setup for SMBus address 0x22. The
retimers can also be configured to other SMBus address combinations.
Figure 1-2 shows the locations of the SMBus address headers used to modify the default SMBus addresses for
the retimers. For more information on valid SMBus addresses, please refer to the DS160PT801 data sheet.
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Figure 1-2. DS160PT801X16EVM SMBus Interface Connections
To access the DS160PT801 devices through this interface, power must be applied through the SATA or Gold
Finger connectors.
1.3 PCIe PRSNT# Signal Control and Configuration
The riser card allows users to alter the hot-plug presence detect signal (PRSNT#) returned to the PCIe host
sytem. This is done by using the headers shown in Figure 1-3. By modifying the jumpers it is possible
to have the PRSNT# signal represent a x1, x4, x8, or x16 mechanical link width. When using the default
jumper configuration listed in Table 1-1, the DS160PT801 riser card allows the PRSNT# lines to be dynamically
determined by the connected endpoint, which is useful for hot-plug detection.
Figure 1-3. DS160PT801X16EVM PCIe PRSNT# Controls
Removing the four shunt jumpers on J45–J48 and placing a single shunt across the lower two pins in one of the
connectors allows the riser card to override PRSNT#. This is useful if a certain width is desirable. For example,
by inserting a shunt jumper in position 2-3 on header J45 will force the PRSNT# status to represent a 1x4
mechanical link width.
1.4 PCIe Reference Clock Control and Configuration
The riser card was designed to accommodate common and independent 100-MHz reference clock architectures.
The default configuration is for a common clock distribution. The incoming system clock is buffered with a clock
fanout device (LMK00334) and sent to each retimer and to the endpoint. The following graphics highlight EVM
and BOM changes which are available to modify the PCIe clock configuration.
1. Set J49 = L for CEM Clock distribution (Common Clock – default setting)
2. Set J49 = H for CDCI6214 Clock distribution (Independent Clock)
Regardless of the clock configuration, there are SMP test points available for clock measurement or triggering.
Refer to Figure 1-4 and Figure 1-5 for more details.
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LMK00334
Net: REFCLKP/N
CLK0
CDCE6214
25 MHz
XTAL
DS80PT801
CLK1
Y3
Y1
DS80PT801
A0
A1 J51 Test Point
B0
B1 SMPs
Y2 SMPs
Net: REFCLKP/N_EP
Straddle connector
DNI: R1, R2
DNI: R47, R48
SELECT CLK0
SMPs
DNI: R95, R99
CEM connector
Figure 1-4. Common Clock Topology Example
LMK00334
CLK0
CDCE6214
25 MHz
XTAL
DS80PT801
CLK1
Y3
Y1
DS80PT801
A0
A1 J51 Test Point
B0
B1 SMPs
Y2 SMPs
Net: REFCLKP/N_EP
Straddle connector
DNI: R1, R2
DNI: R47, R48
SELECT CLK1
SMPs
DNI: R95, R99
CEM connector
Figure 1-5. Independent Clock Topology Example
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2 EVM Power
Onboard regulation is used to step down the input 12-V and 3.3-V supplies to power both DS160PT801 retimers
and other devices on the riser card EVM. There are LEDs to indicate power good for the 1.17-V, 1.8-V and 3.3-V
power supplies. The 1.17-V power supply level can be adjusted in 50-mV increments between 1.0 V and 1.2 V.
Connector J58 is used to make these adjustments. By default, the jumper for J58 is set to the 3-4 position, which
is 1.15 V. The center of the header is a 1.1 V supply level, increasing supply levels to the left and decreasing
supply levels to the right. The EVM must be powered off completely 15 seconds to change voltage level.
Figure 2-1. 1.17-V Power Supply Pin Controls
To facilitate debug and prototype system bring up, the DS160PT801X16 EVM can be powered in two different
ways. One method is through the Gold Finger connector. The other is with the SATA connector at the right
side of the riser card design. The SATA connector can be used to power the EVM separately from the system
power supply. This can be used to help diagnose power supply issues and allow for pre-configuration of the
DS160PT801 through the SMBus interface before system power-up.
FUSE
Net: V12
CEM connector
+12V
Net: V12_F
SATA Connector
Current
Sense Net: V12_CS
TPS548B22
Current
Sense
Net: P2_D_0
Retimer_0: 1.1V High-Speed Digital
Net: P2_A_0
Retimer_0: 1.1V High-Speed Analog
Net: V1P1
FUSE
Net: V3P3
CEM connector
+3.3V
Net: V3P3_F
SATA PWR Connector
TPS7A9101
Net: V1P8
Current
Sense Net: V1P8_0
Retimer_0: 1.8V
Net: V1P8_1
Retimer_1: 1.8V
TPS7A9101
Net: V1P8_CDC
CDCI6214: 2.5V
LMK00334: 3.3V
AT24CxxC 3.3V
Net: V3P3_F
SATA PWR Connector
Net: V3P3_F
SATA PWR Connector
TPS73533
Net: tx_3P3V_MSP
MSP430: 3.3V
Net: tx_VBUS
USB Connector
+5.0V
Filter
Net: P2_D_0 Net: V1P1A_0
Retimer_0: 1.1V Analog
Current
Sense
Filter
Net: P2_D_1 Net: V1P1A_1
Retimer_1: 1.1V Analog
Net: P2_D_1
Retimer_1: 1.1V High-Speed Digital
Net: P2_A_1
Retimer_1: 1.1V High-Speed Analog
Figure 2-2. DS160PT801X16EVM Power Network
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2.1 EVM Current Sensing
Onboard current sense devices are incorporated into the EVM design and layout to monitor voltage regulator
power delivery and assist with thermal analysis. The voltages measured at this connector can be used to
calculate the efficiency of the voltage regulator and the current delivered to each DS160PT801 device.
Figure 2-3. DS160PT801X16EVM Current Sense Measurement Locations
Equation 1 through Equation 4 describe the relationship between the voltage measured from the current sense
devices and the current delivered.
12V_SENSE (J60): Input 12-V supply to TPS548B22 VR
VMEASURED / 20 = Input VR Current (Amps) (1)
1P8: 1.8-V supply to retimer 0 (U2).
VMEASURED / 20 = Retimer, 1.8 V current consumption in Amps (2)
P2A: 1.17-V supply to retimer (PWR_2A)
VMEASURED / 20 = Retimer, 1.17 V current consumption (PWR_2A) in Amps. (3)
P2D: 1.17-V supply to retimer (PWR_2B). Also includes PWR_2C.
VMEASURED / 0.2 = Retimer, 1.17 V current consumption (PWR_2B + PWR_2C) in Amps. (4)
Notes:
1. Retimer 0 (U2) sense connections are in J28
2. Retimer 1 (U3) sense connections are in J33
3. 12V_SENSE (J60) is on the bottom layer
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3 SigCon Architect GUI
The SigCon Architect GUI is designed to be used in conjunction with the DS160PT801X16EVM. By
communicating to the two onboard retimers through the included USB cable, the status of the retimers and
PCIe link can be assessed using a graphical interface.
The SigCon Architect framework is also designed to work with other Texas Instruments products. For this
reason, the installation of the software is split into two parts: The SigCon Architect Framework and the product
profile plug-in. Adding the DS160PT801 product profile to the SigCon Architect framework will enable its
evaluation features. At the time of this document's release, the latest version of the SigCon Architect framework
is version 3.1.0.1, and the latest DS160PT801 profile is version 1.4.0.1.
Together this software enables users to evaluate the DS160PT801 PCIe Gen4 retimer in a system environment.
SigCon Architect is available by request. Please contact a local TI sales representative for more information.
3.1 Setup and Installation
The SigCon Architect framework and DS160PT801 product profile are designed to work with a Windows®
operating system. The installation of the software takes place in two parts. First the installation of the SigCon
Architect v3 framework. After installing the framework, the DS160PT801 product profile may be added.
The step-by-step setup instructions below show be followed to complete the installation of the software and
prepare the DS160PT801X16EVM for evaluation using SigCon Architect.
1. Download and install SigCon Architect Version 3.
2. Download and install the DS160PT801 profile.
3. Connect the included micro-USB cable to the EVM and to the Windows PC.
4. Connect the EVM to the host system by plugging the EVM into a PCIe x16 CEM slot.
5. Install a PCIe end point card, such as a network interface card or GPU, into the opposing top mount straddle
connector.
6. Provide power to the EVM by turning on the host system.
7. Start the SigCon Architect application to begin evaluation.
8. Confirm that the DS160PT801 Configuration page is selected in the navigation panel on the left side of the
window.
The EVM and software should now be ready for evaluation. The DS160PT801 SigCon Architect profile contains
6 pages that group similar functions of the retimer together. These pages are: configuration, low-level, EEPROM,
high-level, diagnostic, and eye monitor. The navigation panel on the left side of the window provides navigation
to all pages; however, pages will be inaccessible until an SMBus connection is established by using the
Configuration page.
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3.2 Configuration Page
Figure 3-1. Configuration Page Screenshot
The Configuration page of the DS160PT801 profile in the SigCon Architect GUI is the only page enabled after
starting the software. This page is intended to be used to configure a connection to the EVM's onboard retimers
through the USB2ANY interface for full access to the retimer functions. To establish a connection, the SMBus
address for the link-width manager and link-width follower should be specified in the provided dropdowns. After
the valid SMBus addresses are specified, the Apply button is used to establish the connection. The following are
descriptions of the various input fields of the Configuration page:
•Manager Address Dropdown specifies the SMBus address of the link-width manager.
•Follower Address Dropdown specifies the SMBus address of the link-follower.
•Toggle LED Button can toggle an onboard LED and can be used to confirm a successful connection.
•Apply Button attempts to establish an SMBus connection to the onboard retimers. If a connection is
successfully established, the other pages of the DS160PT801 GUI will be enabled.
•Online Documentation Button connects to online documentation for the DS160PT801 on ti.com.
•Demo Mode Checkbox may be used to enable GUI demo mode. In this mode, all features of the GUI are
enabled to demonstrate the features of the GUI without an active retimer connection. This may be used to
create EEPROM images, view the register map, or evaluate other portions of the DS160PT801 GUI.
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3.3 Low-Level Page
Figure 3-2. Low-Level Page Screenshot
The Low-Level page of the GUI is used for basic register access to the register map of the DS160PT801 retimer
by providing SMBus read and write functions. The ability to save a specific retimer configuration for use later is
also provided and can be used performing system evaluation. The description of the input fields of the Low-Level
page are as follows.
•Device Select Dropdown allows a user to change the active register map from either the link-width manager
or link-width follower SMBus address.
•Block Select Dropdown allows a user to change the active register block between Global, Shared, Channel,
or PLL registers.
•Current Address Field displays the currently selected register address.
•Data Field displays the data currently stored at the selected register address.
•Mask Value Field displays the mask value that will be used for write operations at this register. Only the bits
that are set to a "1" in this field will be written to.
•Write Register Button issues an SMBus write of the data listed in the data field at the current address using
the bit mask indicated in the Mask Value field.
•Broadcast Button becomes active when one of the channel register blocks are selected. Clicking this button
performs a write operation similar to the Write Register button, but it will broadcast the write to all channels in
the currently selected device.
•Read Register Button issues an SMBus read of the data listed in the current address field.
•Read All Button issues a SMBus read of all registers for the currently selected register block.
•Reset Device Button resets all register values back to their default values. This will cause an active PCIe
link to fail.
•Load Config Button can be used to load a previously saved set of SMBus register values.
•Save Config Button saves a file that stores the current values for all SBMus registers. This file can later be
loaded using the Load Config button.
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3.4 EEPROM Page
Figure 3-3. EEPROM Page Screenshot
The EEPROM page provides access to the EEPROM reading and writing functions of the retimer. It also allows
a user to load or save a pre-configured EEPROM image stored in the .hex file format. For more details about
EEPROM image formatting, please refer to the DS160PT801 EEPROM Programming Guide.2
•CRC Check Box sets the CRC bit to "1" in the EEPROM base header. If enabled, CRC value is computed for
all configuration sets and CRC checking is performed.
•Speed Select Dropdown modifies the write speed field in the EEPROM base header for the current
EEPROM image. This effects how quickly the EEPROM is loaded after power-up.
•Burst Select Dropdown modifies the EEPROM base header to change the amount of consecutive bytes per
read when loading an EEPROM image.
•Download EEPROM Button initiates a download of the currently loaded image on the EEPROM to the
retimer.
•Read From EEPROM Button reads the currently loaded EEPROM image and updates the GUI with its
contents.
•Write to EEPROM Button writes the EEPROM configuration that is currently active in the GUI to the
EEPROM device.
•Load From Hex File Button opens a file explorer window that allows the user to load a .hex file EEPROM
image.
•Write to EEPROM Hex Button saves the currently loaded configuration in the GUI to a .hex file EEPROM
image.
•View Details of Configuration Set Dropdown selects the current EEPROM Configuration Set that is
displayed and can be edited in the GUI.
•No. of Configs Field shows the maximum number of configuration sets for the current configuraiton
•Device Select Dropdown, combined with the Mask Select dropdown, modifies the SMBus addresses that
are effected by the currently displayed configuration set.
•Mask Select Dropdown, combined with the Device Select dropdown, modifies the SMBus addresses that
are effected by the currently displayed configuration set.
2The DS160PT801 EEPROM Programming Guide is available upon request.
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•Configured Devices List shows SMBus addresses of the retimers that will be effected by the currently
displayed configuration set.
•Reg Page Select Dropdown modifies the register page for the currently displayed configuration set.
•Reg Start Offset Addr Dropdown modifies the starting register offset address for the currently displayed
configuration set.
•Payload Size Dropdown determines the number of bytes to be written in the currently selected configuration
set. The bytes will begin writing at the location specified by the Reg Start Offset Addr Dropdown.
•Register Data Table displays the SMBus addresses and corresponding values in the currently selected
configuration set.
•Die 0 Checkbox enables Die 0 to be written to by the currently selected configuration set.
•Die 1 Checkbox enables Die1 to be written to by the currently selected configuration set.
•Load From Device Button updates the current configuration set's data with the register settings of the active
device.
•Write to Device Button updates the register settings of the active device with the current configuration set's
data.
•Active Device Dropdown changes the active device for the Load From Device and Write to Device
commands.
•Field Description Table shows the register map information about the currently selected register.
•EEPROM Data Table shows the full raw EEPROM data that will be loaded on the retimer.
3.5 Control Panel
Figure 3-4. Control Panel Screenshot
The retimer control panel is present in the High-Level, Diagnostic, and Eye Monitor pages of the DS160PT801
GUI. Based on the page that a user is currently on, it will enable and disable certain functions. A list of the
functions for each of the fields within the control panel is shown below:
•Device Select Dropdown selects the active device being configured, either the link-width manager or
link-width follower. It is enabled in the High-Level page when modifying the Rx/Tx EQ settings, the Diagnostic
page, and Eye Monitor pages.
•Channel Select Dropdown selects the active channel being configured. It is enabled in the High-Level page
when modifying the Rx/Tx EQ settings, the Diagnostic page, and Eye Monitor pages.
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•Update Time Dropdown updates the refresh rate for the GUI when the GUI is automatically polling for
retimer status information, such as the Device Status section of the High-Level page.
•SD Settings Radio Buttons changes the Signal Detect mode of the currently selected channel between
State Machine controlled, Force Enabled, and Force Disabled.
•Channel Indicators reports if the currently active channel is detecting a signal and if the CDR is locked onto
the incoming signal.
•Reset CDR All Channels Button reset the CDR for all channels on the currently active device. This will
break a PCIe link and should be used for evaluation only.
•Apply to All Channels Button applies changes specified in the GUI to all channels on the retimer. It is
enabled in the High-Level page when modifying the Rx/Tx EQ settings, the Diagnostic page, and Eye Monitor
pages.
•Load From File Button allows a user to load a previously saved configuration file.
•Save to File Button enables a user to save the current SMBus configuration for the retimer in a configuration
file.
•Reset CDR Button resets the CDR for the currently selected channel.
•Apply to Channel Button applies signal detect settings to the currently selected channel.
•Reset Device Button completely resets the retimer to the default register settings. This will disable a PCIe
link.
•Refresh From Device Button refreshes data in the GUI by downloading the current SMBus configuration of
the retimer.
3.6 High-Level Page
Figure 3-5. High-Level Page Screenshot
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The High-Level page of the DS160PT801 SigCon Architect GUI provides a user-friendly display of the current
status of the retimer along with basic configuration. It contains multiple tabs within the page; the first tab of the
page is the Block Diagram, which shows the analog signal components of the DS160PT801 retimer. This page
will automatically read the current register link-width setting of the retimer and display it on the left side of the
window. The fields that can be used on this page are as follows:
•Bifurcation Options Dropdown allows a user to select from all link width bifurcation options for the PCIe
link.
•Disable Retimer Present Checkbox allows the retimer to disable the broadcasting of its presence in the
PCIe link over the PCIe protocol.
•Initialize Button applies the Bifurcation and Retimer Present changes to the retimer over SMBus
communication. It is important to note than any SMBus settings affecting PCIe link configuration like the
link-width will not take effect after a PCIe link has already been established.
Figure 3-6. High-Level Page – Device Status Screenshot
The device status tab in the High-Level page have multiple sub-tabs with information about the retimer status.
The Rx/Tx status (without Active link) shows status information that does not require an active PCIe link to be
valid. This includes receiver detection, signal detection, and equalizer signal conditioning settings.
•Edit Field Visibility Button allows a user to show or hide different columns within the channel status table.
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Figure 3-7. High Level Page – Device Status (Active Link) Screenshot
After a link is established, there are a number of fields that are updated in the retimer to reflect the current status
of the PCIe link. This includes the Link, Lane number, and orientation of the data flow.
•Edit Field Visibility Button allows a user to show or hide different columns within the channel status table.
Figure 3-8. High-Level – Rx EQ/DFE Page
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This section of the High-Level page allows a user to force the CTLE settings of the DS160PT801. Both the CTLE
and DFE is automatically adaptive by default, and changing these values is generally not needed. However,
when performing evaluation or when the retimer is not actively participating in PCIe protocol, such as during
PRBS checking, it may be useful to set these to a static value.
•DFE Manual Override? Checkbox enables a user to override the DFE values
•DFE Tap 1 Checkbox enables override for DFE Tap 1
•DFE Tap 2 Checkbox enable override for DFE Tap 2
•Set DFE Taps Button applies the DFE settings shown in the GUI to the retimer through SMBus
•Clear DFE Taps Button resets the DFE Tap values to 0
•CTLE Boost Settings List allows a user to select from the pre-configured CTLE Indexes. Selecting higher
values indicates a higher gain.
•Boost Stage 1 Field modifies the index setting for the first stage of the CTLE equalizer.
•Boost Stage 2 Field modifies index setting for the second stage of the CTLE equalizer.
•Boost Stage 3 Field modifies index setting for the third stage of the CTLE equalizer.
•Enable Manual EQ Boosting? Checkbox enables a user to finely control the boost stage settings for the
CTLE.
•Reset CTLE Button resets the CTLE Index to 0
•Load CTLE Button loads a saved pre-configured CTLE value
•Save as CTLE Button saves the currently selected CTLE configuration in a .ini file.
Figure 3-9. High-Level Page Tx FIR
The Tx FIR/VOD tab allows a user to control the coefficient values of the FIR filter at the transmitter of the
DS160PT801. These values are auotmatically negotiated through the PCIe protocol, manually changing them
would cause the retimer to operate outside of specification. For this reason the FIR values should only be
changed when the retimer is not actively participating in PCIe protocol, such as while using the PRBS generator.
•Preset Dropdown changes the PCIe preset value of the DS160PT801's transmitters. This will update the
pre, post, and main cursor value.
•Pre Cursor Tap Field sets the pre cursor value for the Tx FIR.
•Main Cursor Field sets the main cursor value for the Tx FIR.
•Post Cursor Tap Field sets the post cursor value for the Tx FIR.
•Co efficient abs Sum Field displays the absolute value of the Pre, Post, and Main cursor.
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•Read Taps Button reads the current value of the Tx FIR taps.
•Set Taps Button set the Tx FIR tap values to what is currently shown in the GUI.
3.7 Diagnostic Page
Figure 3-10. Diagnostic Page Screenshot
The Diagnostic page contains features of the retimer that are meant to be used for evaluating the signal
integrity of a system. By using the PRBS Checker and PRBS Generator functions of the retimer, it is possible to
determine the Bit Error Ratio (BER) of a channel. This operational mode of the retimer does not operate through
the PCIe protocol. It forced the retimer to simply transmit an electrical pattern specified by a user. There is also
an option to force the transmission of a specific PCIe compliance pattern. The fields available in this page are as
follows:
•Enable Button enables or disables the PRBS or compliance pattern generator with the specified pattern type
and datarate. If using a PCIe compliance pattern, it is possible to also force a specific PCIe preset value for
the transmitted signal.
•Pattern Type Dropdown modifies the pattern that is transmitted by the retimer.
•Data Rate Dropdown changes the datarate of the signal transmitted.
•Preset Dropdown will change the PCIe of the output signal when a compliance pattern is selected in the
pattern type dropdown.
•Capture Period Dropdown modifies the time period used to capture and count errors using the PRBS
Checker.
•Turn ON* Button turns on the PRBS checker.
•Turn OFF* Button turns off the PRBS checker.
•Reset Checker* resets the error count for the PRBS checker.
•Error Count Graph displays the amount of errors accumulated by the PRBS checker over time.
•Clear Checker Button clears the error count graph.
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3.8 Eye Monitor Page
Figure 3-11. Eye Monitor Page Screenshot
The Eye Monitor page allows a user to check the eye openining of a signal at the retimer receiver after
completing CTLE and DFE equalization. This feature can only be used reliably when a PCIe link is stable
enough to maintain the L0 link state. The fields available in the Eye Monitor page are as follows:
•Single Capture Button creates a single eye diagram from in the incoming signal on the selected channel
and stops capturing.
•Continuous Capture monitors the eye diagram from in the incoming signal on the selected channel by
continuously creating eye diagrams unil the user stops the capture.
•Stop Capture stops a continuous capture.
•Recompute HEO/VEO performs a quick measurement of the HEO and VEO of a channel. This method uses
the same technique on the high-level device status page to calculate the HEO and VEO.
•Rx Margin Count Select Dropdown selects the number of bits used when performing Rx margining.
•Rx Margin Error Select modifies the maximum number of errors allowed for each sample point when
performing Rx margining.
•Export Raw Data Button exports the pass or fail results of an eye diagram measurement.
•Export Density exports the results of an eye diagram including error density information.
•Clear Plots clears the Raw Data, Error Hit Count, and Contour data graphs.
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4 PCB Material Information
4.1 DS160PT801 PCB Design
• 62 mils – 12 layer design
• PCIe data traces are 85-Ω target
• PCIe clock traces are 100-Ω target
4.2 DS160PT801 PCB Stackup
Figure 4-1 illustrates the DS160PT801X16EVM PCB stackup.
Figure 4-1. DS160PT801X16EVM PCB Stackup
4.3 DS160PT801 PCB Power Distribution
The riser card power distribution network was designed for observation and performance. Four power layers
were dedicated to retimer supply voltages. This improves isolation between sensitive analog circuits and reduces
losses where high dynamic currents are present.
Layer 3 and Layer 4 in the stackup are dedicated to the high-speed analog and digital supply rails. Both of these
rails are nominally 1.1-V voltage levels. Using two layers as close to the mounted DS160PT801 as possible
improves decoupling performance and aligns with internal package power supply design. Note that previous
designs with a single PWR2_HSD supply are completely compatible with the Revision C pre-production silicon
used on this EVM.
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