Texas Instruments DS320PR412-421EVM User manual

User’s Guide
DS320PR412-421EVM User's Guide
ABSTRACT
The DS320PR412-421EVM evaluation module provides a complete high-bandwidth platform for evaluating the
signal conditioning features of the DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 Quad-
Channel PCI Express 5.0 Linear Redrivers with integrated Mux/Demux. This evaluation board can be used for
standard compliance testing, performance evaluation, and initial system prototyping.
Note: In this document, all instances of DS320PR412 can be interchangeable with SN75LVPE5412 and all
instances of DS320PR421 are interchangeable with SN75LVPE5421.
Figure 1-1. DS320PR412-421EVM
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Features............................................................................................................................................................................. 3
1.2 Applications........................................................................................................................................................................3
2 Description.............................................................................................................................................................................. 4
2.1 Redriver-Mux 5-Level I/O Control Inputs............................................................................................................................4
2.2 Redriver-Mux Modes of Operation..................................................................................................................................... 4
2.3 Redriver-Mux SMBus or I2C Register Control Interface.................................................................................................... 4
2.4 Redriver-Mux Equalization Control.................................................................................................................................... 5
2.5 Redriver-Mux RX Detect State Machine............................................................................................................................ 5
2.6 Redriver-Mux DC Gain Control.......................................................................................................................................... 6
2.7 DS320PR412-421EVM Global Controls............................................................................................................................ 7
2.8 DS320PR412-421EVM Downstream Devices Control.......................................................................................................8
2.9 DS320PR412-421EVM Upstream Devices Control........................................................................................................... 9
2.10 Quick-Start Guide (Pin Mode)........................................................................................................................................ 10
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2.11 Quick-Start Guide (SMBus Slave Mode)........................................................................................................................ 11
3 Schematics............................................................................................................................................................................13
4 PCB Layouts..........................................................................................................................................................................20
5 Bill of Materials..................................................................................................................................................................... 23
List of Figures
Figure 1-1. DS320PR412-421EVM............................................................................................................................................. 1
Figure 2-1. SigCon Architect DS320PR412-421 High Level Page............................................................................................ 12
Figure 3-1. DS320PR412.......................................................................................................................................................... 13
Figure 3-2. DS320PR421.......................................................................................................................................................... 14
Figure 3-3. Configuration Headers............................................................................................................................................ 15
Figure 3-4. I2C Adapter Selection............................................................................................................................................. 15
Figure 3-5. Power...................................................................................................................................................................... 16
Figure 3-6. EDGE Finger........................................................................................................................................................... 17
Figure 3-7. PCIe Clock.............................................................................................................................................................. 18
Figure 3-8. PCIe x8 Connector A...............................................................................................................................................18
Figure 3-9. PCIe x16 Connector B.............................................................................................................................................19
Figure 4-1. Top Layer.................................................................................................................................................................20
Figure 4-2. Layer 2.................................................................................................................................................................... 20
Figure 4-3. Layer 3.................................................................................................................................................................... 21
Figure 4-4. Layer 4.................................................................................................................................................................... 21
Figure 4-5. Layer 5.................................................................................................................................................................... 22
Figure 4-6. Bottom Layer........................................................................................................................................................... 22
List of Tables
Table 2-1. Five-Level Control Pin Settings...................................................................................................................................4
Table 2-2. Modes of Operation.................................................................................................................................................... 4
Table 2-3. Redriver-Mux SMBus Address Map............................................................................................................................4
Table 2-4. Equalization Control Settings......................................................................................................................................5
Table 2-5. Rx Detect Control Pin Settings................................................................................................................................... 6
Table 2-6. GAIN Control...............................................................................................................................................................6
Table 2-7. EVM Global Controls.................................................................................................................................................. 7
Table 2-8. EVM Downstream Devices Controls...........................................................................................................................8
Table 2-9. EVM Upstream Devices Controls............................................................................................................................... 9
Table 2-10. Pin Mode Shunt Configuration................................................................................................................................ 10
Table 2-11. SMBus/I2C Mode Shunt Configuration....................................................................................................................11
Table 5-1. DS320PR412-421 Bill of Materials........................................................................................................................... 23
Trademarks
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1 Introduction
The DS320PR412-421EVM features two DS320PR412 and two DS320PR421 linear redrivers that can extend
the transmission distance of a PCIe Gen-5 x8 bus. The EVM can be directly plugged into a PCIe slot on a server
or PC motherboard using the PCIe Edge connector on the board and paired with a PCIe add-in card using one
of the two PCIe connectors on the EVM.
1.1 Features
DS320PR412-421EVM includes the following features:
• PCIe x16 and PCIe x8 Riser Card with two DS320PR412 and two DS320PR421 4-channel unidirectional
linear redrivers operating at rates up to 32Gbps.
• DS320PR412: linear redriver with 1:2 MUX
• DS320PR421: linear redriver with 2:1 DEMUX
• Linear equalization for seamless support of link training and PCIe channel extension
• CTLE boosts up to 24dB at 16GHz
• Device configuration and MUX selection by pin control, SMBus, or I2C.
• Flow-thru layout with no heat sink required
1.2 Applications
• PCI Express Gen 1, 2, 3, 4, and 5
• High-speed interfaces up to 32Gbps
• Enterprise server motherboard, workstation
• Enterprise storage
• Enterprise add-in card, end-point
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2 Description
2.1 Redriver-Mux 5-Level I/O Control Inputs
Each DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 features 5-level input pins (MODE,
GAIN/SDA, EQ0/ADDR, EQ1, and RX_DET/SCL) that are used to control the configuration of the device. These
5-level inputs use a resistor divider to help set the five valid levels to provide a wider range of control settings.
Table 2-1. Five-Level Control Pin Settings
PIN LEVEL PIN SETTING
L0 1 kΩ to GND
L1 8.25K Ω to GND
L2 24.9 Ω to GND
L3 75 Ω to GND
L4 Float
2.2 Redriver-Mux Modes of Operation
Each DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 can be configured to operate in either
Pin Mode, SMBus Mode, or I2C Slave Mode. The mode of operation of the redriver is determined by the pin
strap setting on the MODE pin as shown in Table 2-2.
Table 2-2. Modes of Operation
MODE PIN LEVEL MODE OF OPERATION
L0 Pin Mode
L1 SMBus Mode or I2C Slave Mode
L2 SMBus Mode or I2C Slave Mode
L3 RESERVED
L4 RESERVED
2.3 Redriver-Mux SMBus or I2C Register Control Interface
The DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 internal registers can be accessed
through standard SMBus protocol. The DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421
features two banks of channels, Bank 0 (Channels 0-1) and Bank 1 (Channels 2-3), each featuring a separate
register set and requiring a unique SMBus slave address. The SMBus slave address pairs (one for each channel
bank) are determined at power up based on the configuration of the MODE and EQ0/ADDR pins. The pin state
is read on power up, after the internal power-on reset signal is deasserted.
There are 8 unique SMBus slave address pairs (one address for each channel bank) that can be assigned to
the device by placing external resistor straps on the MODE and EQ0/ADDR pins as shown in Table 2-3. When
multiple DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 devices are on the same SMBus
interface bus, each channel bank of each device must be configured with a unique SMBus slave address pair.
Table 2-3. Redriver-Mux SMBus Address Map
MODE EQ0/ADDR Pin Level Channels 0-1:
7-Bit Address [HEX]
Channels 2-3:
7-Bit Address [HEX]
L1 L0 0x18 0x19
L1 L1 0x1A 0x1B
L1 L2 0x1C 0x1D
L1 L3 0x1E 0x1F
L2 L0 0x20 0x21
L2 L1 0x22 0x23
L2 L2 0x24 0x25
L2 L3 0x26 0x27
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2.4 Redriver-Mux Equalization Control
Each channel of the DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 features a continuous-
time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize
the frequency-dependent insertion loss effects of the passive channel. Table 2-4 shows available equalization
boost index through EQ control pins (EQ1 and EQ0) for all channels when in Pin Control mode (MODE = L0).
Please refer to data sheet for actual EQ Gain values.
Table 2-4. Equalization Control Settings
EQ INDEX EQ1 PIN LEVEL EQ0 PIN LEVEL
0 L0 L0
1 L0 L1
2 L0 L2
3 L0 L3
4 L0 L4
5 L1 L0
6 L1 L1
7 L1 L2
8 L1 L3
9 L1 L4
10 L2 L0
11 L2 L1
12 L2 L2
13 L2 L3
14 L2 L4
15 L3 L0
16 L3 L1
17 L3 L2
18 L3 L3
19 L3 L4
The equalization gain of each channel of each device can also be set by writing to SMBus / I2C registers in I2C
Mode.
2.5 Redriver-Mux RX Detect State Machine
Each DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 deploys an RX Detect state machine
that governs the RX detection cycle as defined in the PCI Express specification. At power up or after a manually
triggered event, the redriver determines whether or not a valid PCI Express termination is present at the far
end of the link. The RX_DET/SCL pin of DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421
provides additional flexibility to system designers to appropriately set the device in their desired mode, according
to Table 2-5.
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Table 2-5. Rx Detect Control Pin Settings
PD PIN LEVEL RX_DET PIN LEVEL DESCRIPTION
L L0
PCI Express RX detection state machine is disabled.
Recommended for non-PCI Express use cases. Inputs
are always 50 Ω.
L L1 Outputs poll until three consecutive valid detections.
L L2 Outputs poll until two consecutive valid detections.
L L3 Reserved.
L L4 TX polls every ~150us until valid termination is
detected. Recommended Default setting for PCIe.
H X Manual reset, inputs are Hi-Z
2.6 Redriver-Mux DC Gain Control
When operating in Pin Mode, the GAIN/SDA pin can be used to set the overall datapath DC (low frequency) gain
of the DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 as shown in Table 2-6. Please refer to
data sheet for actual Gain values.
Table 2-6. GAIN Control
GAIN/SDA PIN
LEVEL GAIN SETTING
L0 Refer to data sheet
L1 Refer to data sheet
L2 Refer to data sheet
L3 Refer to data sheet
L4 0 dB (Recommended for most use cases)
The DC gain of each channel of each device can also be set by writing to SMBus / I2C registers in Slave or
Master Modes.
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2.7 DS320PR412-421EVM Global Controls
Table 2-7 shows the DS320PR412, DS320PR421, SN75LVPE5412 and SN75LVPE5421 EVM global controls
that affect all devices on the board.
Table 2-7. EVM Global Controls
COMPONENT NAME FUNCTION OR DESCRIPTION
J1 DS320PR412-0 VCC
Pins 1-2 : PCIe Connector VCC
Pins 2-3:
Regulator 3.3V
J2 DS320PR412-1 VCC
Pins 1-2 : PCIe Connector VCC
Pins 2-3:
Regulator 3.3V
J3 DS320PR421-2 VCC
Pins 1-2 : PCIe Connector VCC
Pins 2-3:
Regulator 3.3V
J4 DS320PR421-3 VCC
Pins 1-2 : PCIe Connector VCC
Pins 2-3:
Regulator 3.3V
J5 PCIe JTAG TRST
1-2: Edge Finger to PCIe-B
3-4 Edge Finger to PCIe A + B
5-6 Edge Finger to PCIe-A
J6 PCIe JTAG TCK
1-2: Edge Finger to PCIe-B
3-4 Edge Finger to PCIe A + B
5-6 Edge Finger to PCIe-A
J7 PCIe TDI
1-2: Edge Finger to PCIe-B
3-4 Edge Finger to PCIe A + B
5-6 Edge Finger to PCIe-A
J8 PCIe TDO
1-2: Edge Finger to PCIe-B
3-4 Edge Finger to PCIe A + B
5-6 Edge Finger to PCIe-A
J9 PCIe TMS
1-2: Edge Finger to PCIe-B
3-4 Edge Finger to PCIe A + B
5-6 Edge Finger to PCIe-A
J10 Board Regulator 3.3-V
Output
Pin 1 : Board 3.3V
Pin 2: GND
J11 Board 12-V Supply Pin 1 : Board 12V
Pin 2: GND
JMP7 MUX SEL 1-2 : PCIe Edge Finger to PCIe-B
2-3: PCIe Edge Finger to PCIe-A
JMP8 Redriver PD 1-2 : Power Down
2-3: Normal Operation
JMP17 I2C Interface Sel 1-2 : USB2ANY
2-3: Aardvark
JMP18 CLK Buffer Enable 1-2 : Disabled
2-3: Enabled
JMP19 CLK Buffer Input Sel 1-2 : CLKIN1
2-3: CLKIN0
JMP20 CLK Buffer Ref. Out 1-2 : Enabled
2-3: Disabled
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2.8 DS320PR412-421EVM Downstream Devices Control
Table 2-8 shows DS320PR412-421EVM downstream devices controls that affect DS1 and DS2 devices on the
board.
Table 2-8. EVM Downstream Devices Controls
COMPONENT NAME FUNCTION OR DESCRIPTION
JMP1 DS320PR412_0
EQ0_ADDR_0
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
JMP2 DS320PR412_0
EQ1
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
JMP3 DS320PR412_0
MODE
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
J30 DS320PR412_0
RX_DET_SCL_0
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
9-10: SCL
J23 DS320PR412_0
GAIN_SDA
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
9-10: SDA
JMP4 DS320PR412_1
EQ0_ADDR_0
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
JMP5 DS320PR412_1
EQ1
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
JMP6 DS320PR412_1
MODE
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
J24 DS320PR412_1
RX_DET_SCL_0
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
9-10: SCL
J25 DS320PR412_1
GAIN_SDA
1-2: L0
3-4: L1
5-6: L2
7-8: L3
N/C: L4
9-10: SDA
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2.9 DS320PR412-421EVM Upstream Devices Control
Table 2-9 shows DS320PR412-421EVM upstream devices controls that affect US1-US2 devices on the board.
Table 2-9. EVM Upstream Devices Controls
COMPONENT NAME FUNCTION OR DESCRIPTION
JMP9 DS320PR421_0
EQ0_ADDR_0
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
JMP10 DS320PR421_0 EQ1 1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
JMP11 DS320PR421_0 MODE 1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
J26 DS320PR421_0
RX_DET_SCL_0
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4 9-10: SCL
J27 DS320PR421_0
GAIN_SDA
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4 9-10: SDA
JMP14 DS320PR421_1
EQ0_ADDR_0
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
JMP15 DS320PR421_1 EQ1 1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
JMP16 DS320PR421_1 MODE 1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4
J28 DS320PR421_1
RX_DET_SCL_0
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4 9-10: SCL
J29 DS320PR421_1
GAIN_SDA
1-2: L0 3-4: L1 5-6: L27-8: L3 N/C: L4 9-10: SDA
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2.10 Quick-Start Guide (Pin Mode)
Check that the shunts are at the following positions as shown in Table 2-10.
Table 2-10. Pin Mode Shunt Configuration
SHNT# HEADER SHUNT ACROSS
PINS
1 J1 - J4 1-2
2 JMP7 1-2
3 JMP8 2-3
4 JMP17 2-3
5 JMP18 2-3
6 JMP19 2-3
7 J17 1-2, 3-4
8 J18 1-2, 3-4
9 J19 1-2, 3-4
10 J20 1-2, 3-4
11 J21 1-2, 3-4
12 JMP1 1-2
13 JMP2 3-4
14 JMP3 1-2
15 J30 N/C
16 J23 N/C
17 JMP4 1-2
18 JMP5 3-4
19 JMP6 1-2
20 J24 N/C
21 J25 N/C
22 JMP9 1-2
23 JMP10 3-4
24 JMP11 1-2
25 J26 N/C
26 J27 N/C
27 JMP14 1-2
28 JMP15 3-4
29 JMP16 1-2
30 J28 N/A
31 J29 N/A
The redrivers are configured to operate in Pin Mode (MODE pins tied to L0).
1. RX_Detect state machine of all redrivers is enabled by leaving RX_DET pin open.
2. The redrivers are enabled (PWDN pins tied to GND).
3. The board is configured for any PCIe bus width.
4. DC Gain of all redrivers is set to 0 dB by leaving the GAIN config pin open for the redrivers.
5. EQ level is set to CTLE index 5.
6. If necessary, adjust EQ levels of the downstream and upstream redrivers.
7. Plug the EVM into a PCIe x16 server motherboard slot. Ensure the motherboard is powered down before
installing the EVM or configured for hot-plug operation.
8. Install a compatible PCIe endpoint card into one of the PCIe connectors on the EVM based on configuration
of the SEL pin. Note: PCIe-A requires enabling bifurcation on the motherboard.
9. Power-up the motherboard.
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2.11 Quick-Start Guide (SMBus Slave Mode)
Configure all devices to operate in the SMBus Slave Mode by setting their MODE pins to the L1 level, each
redriver is assigned a unique SMBus secondary address. This is accomplished by placing shunts as shown in
Table 2-11.
Table 2-11. SMBus/I2C Mode Shunt Configuration
SHNT# HEADER SHUNT ACROSS
PINS
1 J1 - J4 1-2
2 JMP7 1-2
3 JMP8 2-3
4 JMP17 2-3
5 JMP18 2-3
6 JMP19 2-3
7 J17 1-2, 3-4
8 J18 1-2, 3-4
9 J19 1-2, 3-4
10 J20 1-2, 3-4
11 J21 1-2, 3-4
12 JMP1 5-6
13 JMP2 3-4
14 JMP3 3-4
15 J30 9-10
16 J23 9-10
17 JMP4 7-8
18 JMP5 3-4
19 JMP6 3-4
20 J24 9-10
21 J25 9-10
22 JMP9 1-2
23 JMP10 1-2
24 JMP11 3-4
25 J26 9-10
26 J27 9-10
27 JMP14 3-4
28 JMP15 1-2
29 JMP16 3-4
30 J28 9-10
31 J29 9-10
1. Connect USB2ANY or Aardvark Adapter to P4 (Note that the Adapter is not supplied with the
DS320PR412-421EVM). Install shunt on JMP17 across pins 1-2 for USB2ANY, 3-4 for Aardvark.
2. Install SigCon Architect Version 3.0.0.16 application and the DS320PR412-421 profile.
3. Plug the EVM into a PCIe x16 server motherboard slot. Ensure the motherboard is powered down before
installing the EVM or configured for hot-plug operation.
4. Install a compatible PCIe endpoint card into the straddle connector of the EVM.
5. Power-up the motherboard.
6. Start the SigCon Architect application.
7. Select the DS320PR412-421 Configuration Page and select the Apply box to enable the device profile. If
necessary, edit device addresses in the Edit Device Addresses box.
8. In the DS320PR412-421 High Level Page, select Block Diagram as shown in Figure 2-1.
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9. Select desired EQ Settings and Driver VOD.
10. Select the devices to which you want to apply the selected settings and click the Apply to All Channels
button.
Figure 2-1. SigCon Architect DS320PR412-421 High Level Page
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3 Schematics
Figure 3-1 through Figure 3-9 show the EVM schematics.
Figure 3-1. DS320PR412
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Figure 3-2. DS320PR421
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Figure 3-3. Configuration Headers
Figure 3-4. I2C Adapter Selection
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Figure 3-5. Power
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Figure 3-6. EDGE Finger
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Figure 3-7. PCIe Clock
Figure 3-8. PCIe x8 Connector A
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Figure 3-9. PCIe x16 Connector B
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4 PCB Layouts
Figure 4-1 through Figure 4-6 illustrate the EVM PCB layout images.
Figure 4-1. Top Layer
Figure 4-2. Layer 2
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