Texas Instruments LMG342XEVM-04X User manual

User’s Guide
LMG342XEVM-04X User Guide
ABSTRACT
The LMG342XEVM-04X features two LMG342XR0X0 600-V GaN FETs with an integrated driver and protection
in a half-bridge configuration with all the required bias circuit and logic/power level shifting. Essential power
stage and gate-driving, high-frequency current loops are fully enclosed on the board to minimize power loop
parasitic inductance for reducing voltage overshoots and improving performance. The LMG342XEVM-04X is
configured for a socket style external connection for easy interface with external power stages to run the
LMG342XR0X0 in various applications. Refer to the LMG342XR0X0 data sheet before using this EVM.
Table of Contents
1 General TI High Voltage Evaluation User Safety Guidelines ............................................................................................. 3
1.1 Safety and Precautions...................................................................................................................................................... 4
2 Introduction.............................................................................................................................................................................5
2.1 LMG342XEVM-04X Daughter Card................................................................................................................................... 5
2.2 Mother Boards....................................................................................................................................................................9
2.3 Typical Applications............................................................................................................................................................9
2.4 Features............................................................................................................................................................................. 9
3 LMG342XEVM-04X Schematic............................................................................................................................................. 10
4 Mother Board Schematic......................................................................................................................................................11
5 Recommended Footprint..................................................................................................................................................... 13
6 Test Equipment..................................................................................................................................................................... 14
7 Test Procedure When Paired With LMG342X-BB-EVM......................................................................................................15
7.1 Setup................................................................................................................................................................................15
7.2 Start-Up and Operating Procedure.................................................................................................................................. 16
7.3 Test Results......................................................................................................................................................................17
7.4 Shutdown Procedure........................................................................................................................................................18
7.5 Additional Operating Notes.............................................................................................................................................. 18
8 Test Procedure When Paired With LMG34XX-BB-EVM..................................................................................................... 19
8.1 Setup................................................................................................................................................................................19
8.2 Start-Up and Operating Procedure.................................................................................................................................. 21
8.3 Shutdown Procedure........................................................................................................................................................22
8.4 Additional Operation Notes.............................................................................................................................................. 22
9 Bill of Materials..................................................................................................................................................................... 23
10 Revision History................................................................................................................................................................. 26
List of Figures
Figure 2-1. LMG342XEVM-04X Block Diagram.......................................................................................................................... 6
Figure 2-2. Front Side View of the EVM...................................................................................................................................... 7
Figure 2-3. Back Side View of the EVM.......................................................................................................................................8
Figure 3-1. LMG342XEVM-04X Schematic............................................................................................................................... 10
Figure 4-1. LMG342X-BB-EVM Schematic................................................................................................................................11
Figure 4-2. LMG34XX-BB-EVM Schematic............................................................................................................................... 12
Figure 5-1. Recommended Footprint for LMG342XEVM-04X .................................................................................................. 13
Figure 7-1. LMG342X-BB-EVM Motherboard With LMG342XEVM-04X .................................................................................. 15
Figure 7-2. Connector and LEDs on the LMG342X-BB-EVM....................................................................................................16
Figure 7-3. Switch-Node Voltage Measurement with High-Bandwidth Probe and Pigtail Ground Connection..........................16
Figure 7-4. 85 V/ns at 400 V/20 A............................................................................................................................................. 17
Figure 7-5. 100 V/ns at 400 V/20 A........................................................................................................................................... 17
Figure 7-6. 30 V/ns at 400 V/20 A............................................................................................................................................. 18
Figure 7-7. 150 V/ns at 400 V/5 A............................................................................................................................................. 18
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Figure 8-1. LMG342XEVM-04X Connected to the LMG34XX-BB-EVM....................................................................................19
Figure 8-2. Recommended Connection Points..........................................................................................................................20
List of Tables
Table 2-1. EVM Version Lookup Table.........................................................................................................................................5
Table 2-2. Logic Pin Function Description................................................................................................................................... 5
Table 2-3. Power Pin Function Description..................................................................................................................................6
Table 8-1. Test Point Functional Description..............................................................................................................................21
Table 8-2. List of Terminals........................................................................................................................................................ 21
Table 9-1. Bill of Materials for LMG342XEVM-04X ...................................................................................................................23
Table 9-2. Bill of Materials for LMG342X-BB-EVM.................................................................................................................... 24
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
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1 General TI High Voltage Evaluation User Safety Guidelines
WARNING
Always follow TI’s set-up and application instructions, including the use of all interface components within the
recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure
your personal safety and the safety of those working around you. Contact TI’s Product Information Center at
http://support/ti./com for further information.
Note
Save all warnings and instructions for future reference.
Failure to follow warnings and instructions may result in personal injury, property damage, or
death due to electrical shock and/or burn hazards.
The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed PCB
(printed circuit board) assembly. It is intended strictly for use in development laboratory environments, solely for
qualified professional users having training, expertise, and knowledge of electrical safety risks in development
and application of high-voltage electrical circuits. Any other use or application is strictly prohibited by Texas
Instruments. If you are not suitably qualified, you must immediately stop from further use of the HV EVM.
•Work Area Safety:
– Maintain a clean and orderly work area.
– Qualified observer(s) must be present anytime circuits are energized.
– Effective barriers and signage must be present in the area where the TI HV EVM and its interface
electronics are energized; indicating operation of accessible high voltages may be present for the purpose
of protecting inadvertent access.
– All interface circuits, power supplies, evaluation modules, instruments, meters, scopes, and other related
apparatus used in a development environment exceeding 50 VRMS/75 VDC must be electrically located
within a protected Emergency Power Off (EPO) power strip.
– Use a stable and non-conductive work surface.
– Use adequately insulated clamps and wires to attach measurement probes and instruments. No freehand
testing whenever possible.
•Electrical Safety:
– As a precautionary measure, it is always a good engineering practice to assume that the entire EVM may
have fully accessible and active high voltages.
– De-energize the TI HV EVM and all its inputs, outputs, and electrical loads before performing any
electrical or other diagnostic measurements. Confirm that TI HV EVM power has been safely de-
energized.
– After confirming the EVM is de-energized, proceed with the required electrical circuit configurations,
wiring, measurement equipment hook-ups, and other application needs while still assuming the EVM
circuit and measuring instruments are electrically live.
– When EVM readiness is complete, energize the EVM as intended.
WARNING
While the EVM is energized, never touch the EVM or its electrical circuits as they could be at high
voltages capable of causing electrical shock hazard.
•Personal Safety:
– Wear personal protective equipment like latex gloves and safety glasses with side shields, or protect the
EVM from accidental touch in an adequate translucent plastic box with interlocks.
•Limitation for Safe Use:
– EVMs are not to be used as all or part of a production unit.
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1.1 Safety and Precautions
The EVM is designed for professionals who have received the appropriate technical training and is designed
to operate from an AC power supply or a high-voltage DC supply. Read this user guide and the safety-related
documents that come with the EVM package before operating this EVM.
CAUTION
!
Do not leave the EVM powered when unattended.
WARNING
Hot surface! Contact may cause burns. Do not touch!
WARNING
High Voltage! Electric shock is possible when connecting board to live wire. Board must be handled
with care by a professional.
For safety, use of isolated test equipment with overvoltage and overcurrent protection is highly
recommended.
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2 Introduction
The LMG342XEVM-04X operates as a half-bridge daughter card that can be either part of a larger custom
designed system or paired with the mother board. TI provides two mother boards (LMG342X-BB-EVM and
LMG34XX-BB-EVM) to interface with LMG342XEVM-04X. LMG342X-BB-EVM can support up to 4-kW, and
LMG34XX-BB-EVM can provide up to 1.7-kW. The mother boards are designed to operate LMG342XR0X0 in an
open-loop synchronous buck or boost converters. Probe locations are provided to measure the logic and power
stage voltages.
Note
TI provides a custom interposer board that must be used when the LMG342XEVM-04X is paried with
the LMG34XX-BB-EVM. The interposer board is not needed with LMG342x-BB-EVM.
2.1 LMG342XEVM-04X Daughter Card
The LMG342XEVM-04X has two LMG342XR0X0 GaN FETs in a half-bridge configuration. All the bias and level
shifting components are included, which allows low-side referenced signals to control both FETs. High-frequency
decoupling capacitors are included on the power stage in an optimized layout to minimize parasitic inductance
and reduce voltage overshoot.
The layout of the board is critical to device's performance and functionality. TI prefers a four-layer or higher layer
count board to reduce the parasitic inductance of the layout to achieve suitable performance. Layout guidelines
are provided in the LMG342xR030 600-V 30-mΩ GaN FET With Integrated Driver, Protection, and Temperature
Reporting data sheet to optimize the solder-joint reliability, power loop inductance, signal to ground connection,
switched-node capacitance and thermal heat dissipation.
Table 2-1. EVM Version Lookup Table
EVM NAME FEATURED GaN FET WITH INTEGRATED DRIVER AND
PROTECTION
LMG3422EVM-041 LMG3422R050
LMG3422EVM-043 LMG3422R030
LMG3425EVM-041 LMG3422R050
LMG3425EVM-043 LMG3425R030
There are 12 logic pins on the LMG342XEVM-04X.
Table 2-2. Logic Pin Function Description
PIN PIN DESIGNATION DESCRIPTION
LS PWM 1 Logic gate signal input for low-side LMG342XR0X0. Compatible with both 3.3-V and 5-V logic.
Referenced to AGND.
HS TEMP 2 PWM TEMP output for high-side LMG342XR0X0. Referenced to AGND.
LS Fault 3 FAULT output signal for low-side LMG342XR0X0. Referenced to AGND.
HS OC 4 OC output signal for high-side LMG342XR0X0. Referenced to AGND.
LS OC 5 OC output signal for low-side LMG342XR0X0. Referenced to AGND.
HS Fault 6 FAULT output signal for high-side LMG342XR0X0. Referenced to AGND.
LS Temp 7 PWM TEMP output for low-side LMG342XR0X0 . Referenced to AGND.
HS PWM 8 Logic gate signal input for high-side LMG342XR0X0. Compatible with both 3.3-V and 5-V logic.
Referenced to AGND.
12V 9 Auxiliary power input for when the LMG342XEVM-04X is configured in bootstrap mode. Pin is not
used when configured in isolated power mode.
5V 10 Auxiliary power input for the LMG342XEVM-04X. Used to power logic isolators. Used as input bias
power of LMG342XR0X0 devices when configured in isolated power mode.
AGND 11,12 Logic and bias power ground return pin. Functionally isolated from PGND.
There are six power pins on the LMG342XEVM-04X.
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Table 2-3. Power Pin Function Description
PIN DESCRIPTION
SW Switch node of the half-bridge configuration
HV Input DC voltage of the half-bridge configuration
PGND Power ground of the half-bridge configuration. Functionally isolated from AGND.
Figure 2-1. LMG342XEVM-04X Block Diagram
CAUTION
High-voltage levels are present on the evaluation module whenever it is energized. Take proper
precautions when working with the EVM.
2.1.1 FAULT and OC
The FAULT and OC pins of the LMG342XEVM-04X are active low when an undervoltage lockout occurs on an
auxiliary voltage rail, when an overtemperature event occurs, or when an overcurrent/short-circuit event occurs
on the LMG342XR0X0. The signals are level-shifted to AGND. Refer to the LMG342XR0X0 data sheet for
operation details.
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CAUTION
Do NOT ignore a FAULT signal when using the LMG342XEVM-04X. Turn off both top and bottom
devices if any device generates a FAULT signal. The device under a fault condition may operate
in the undesired third-quadrant mode and can overheat or become damaged due to the high source-
drain voltage drop if the other device is still switching.
2.1.2 Power Pins
There are some high frequency decoupling capacitors on the LMG342XEVM-04X from VDC to PGND to
minimize voltage overshoot during switching, but more bulk capacitance is required to hold up the DC voltage
during operation. TI recommends preventing any overlap and parasitic capacitance from VSW to VDC, PGND,
and any logic pins. The two ground PGND and AGND pins are functionally isolated from each other on the
LMG342XEVM-04X.
2.1.3 Bootstrap Mode
The LMG342XEVM-04X card can be modified to operate in bootstrap mode, where the 12-V bias voltage is used
to power both LMG342XR0X0 devices. This mode can be achieved by the following modifications to the EVM:
1. Remove R1.
2. Place a 2-Ω resistor on R2.
3. Place a 600-V SOD-123 diode on D1, such as UFM15PL-TP.
4. Adjust Rdrv resistor for the low side to be above 70 kΩ, which corresponds to a slew rate below 60 V/ns for
the low side.
2.1.4 Heat Sink
The heat sink is installed to help with heat dissipation of the LMG342XR0X0. Exposed copper pads are attached
to the die attach pad (DAP) on the high-side and low-side devices to provide a low thermal impedance point
for the heat sink. The two copper pads have a high-voltage potential difference between them, therefore an
electrically isolated thermal interface material (TIM) is required.
For optimal thermal dissipation and board level reliability, recommendation for thermal via pattern and
solder paste example are provided in the LMG342xR030 600-V 30-mΩ GaN FET With Integrated Driver,
Protection, and Temperature Reporting data sheet. In this daughter card design, 'S05MZZ12-A' heatsink
and 'GR80A-0H-50GY', thermal interface material has been used. More details on thermal performance and
comparison between different TIM are shown in Thermal Performance of QFN 12x12 Package for 600-V GaN
Power Stage application note.
Figure 2-2. Front Side View of the EVM
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Figure 2-3. Back Side View of the EVM
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2.2 Mother Boards
Two mother boards are available from TI: LMG342X-BB-EVM and LMG34XX-BB-EVM.
Note
TI provides a custom interposer board that must be used when the LMG342XEVM-04X is paried with
the LMG34XX-BB-EVM. The interposer board is not needed with LMG342x-BB-EVM.
2.2.1 Bias Supply
The motherboard requires one 12-V bias supply. A linear dropout regulator (in LMG34XX-BB-EVM) or buck
regulator (in LMG342X-BB-EVM) steps the voltage down to a tightly regulated 5-V for the logic and auxiliary
power of the LMG342XR0X0 when the LMG342XEVM-04X is configured in isolated power mode.
2.2.2 PWM Input
Both LMG342X-BB-EVM and LMG34XX-BB-EVM mother boards have on-board complementary PWM
generation circuits that create a pair of complimentary PWM signals out of a single PWM input. A 0-V to 5-V
square wave input is recommended. In LMG34XX-BB-EVM, the default dead time is 50ns, and other values are
achievable by changing the resistance values (R1 and R5). In LMG342X-BB-EVM mother boards, the dead time
can be easily adjusted by tuning the trimmer resistance values (R3 and R15).
2.2.3 Fault Protection
There is an option to disable the PWM input to the daughter card in the event of a fault signal from the
LMG342XEVM-04X. When the FAULT Protect jumper is placed in the EN mode, PWM is disabled when either
LMG342XR0X0 has an active fault. This disable is not latching, so PWM immediately resumes when the fault
clears. If the FAULT Protect mode is not desired, that mode can be disabled by placing the jumper in the DIS
position. The FAULT LED will still illuminate when either LMG342XR0X0 has an active fault, regardless of the
position of FAULT Protect jumper.
2.3 Typical Applications
The LMG342XEVM-04X is designed for use in AC/DC, DC/DC and DC/AC applications:
• Totem-Pole PFC Converters
• Phase-Shifted Full Bridge or LLC Converters
• Inverters
• Buck or Boost Converters
2.4 Features
The LMG342XEVM-04X has the following features and specifications:
• Overtemperature, overcurrent, short-circuit, and undervoltage lockout protection with FAULT and OC
indication that is level-shifted to an AGND referenced signal
• A real-time digital output with its duty cycle indicating the device's junction temperature
• Cycle-by-cycle overcurrent protection and latched short-circuit protection
• Gate logic input support of either 3.3-V or 5-V logic
• Maximum recommended operating voltage of 480-V and absolute maximum voltage of 600-V
The mother boards have the following features and specifications:
• Requires only a single 12-V bias supply
• Requires only a single 0-V to 5-V PWM input to generate a gate drive signal
• PWM disables in the event of a fault from the LMG342XEVM-04X
• Maximum recommended operating voltage of 480-V and absolute maximum voltage of 600-V
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3 LMG342XEVM-04X Schematic
t_FET_PWM
AGND
ISO_12V_L
0.022µF
C15
0.022µF
C16
0.022µF
C17
iVSWNET
i
VSWNET
i
VHV
5V_H
Power Connector
HVBUS
LMG342x Half-Bridge GaN Daughter Card
ISO_12V_H
AGND
5V_H
0.1uF
C20
0.1uF
C21
5V
AGND
5V
AGND
49.9
R16
49.9
R7
ISONC2
ISO_12V_L
PGND
ISO_12V_H
ISO_12V_L_B
ISO_12V_H_B
D1 1
D2 3
VCC
2
GND 4
EN
5
CLK
6
U6
SN6505BDBVR
D1 1
D2 3
VCC
2
GND 4
EN
5
CLK
6
U5
SN6505BDBVR
16V
D5
10uF
C1
4.7uF
C37
4.7uF
C36
4.7uF
C30
4.7uF
C31
4.7uF
C33 4.7uF
C35
68pF
C14
68pF
C6
TP1
5016
0
R1
ISO_RET_H_B
SW
SW
SW
ISO_RET_L_B
VDD
46 DRAIN 1
DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5
DRAIN 6
DRAIN 7
DRAIN 8
DRAIN 9
DRAIN 10
DRAIN 11
DRAIN 12
DRAIN 13
DRAIN 14
DRAIN 15
DRAIN 16
SOURCE 17
SOURCE 18
SOURCE 19
SOURCE 20
SOURCE 21
SOURCE 22
SOURCE 23
SOURCE 24
SOURCE 25
SOURCE 26
SOURCE 27
SOURCE 28
SOURCE 29
SOURCE 30
SOURCE 31
SOURCE 32
SOURCE 33
SOURCE 34
SOURCE 35
SOURCE 36
SOURCE 37
SOURCE 38
SOURCE 39
SOURCE 40
FAULT
48
OC
50
BBSW
43
IN
47
LDO5V
53
RDRV
52
TEMP
51
VNEG
41 VNEG
42
GND 44
GND 45
GND 49
GND 54
PAD 55
LMG3422R030RQZT
U2
5V_H
SW
1uF
C26
0.1uF
C10
SW
0
R3
SW
SW
22pF
C5
20k 100V/ns
70k 50V/ns
iVSWNET
5V_L
12V
AGND
5V_L
IN_L
5V_L
1uF
C9
0.1uF
C27
PGND
0
R12
PGND
22pF
C23
20k 100V/ns
70k 50V/ns
AGND
5V
AGND
5V
AGND
Bot_FET_PWM
5V12V
Bot_FET_FAULT
Bot_FET_OC
Bot_FET_TEMP
1 2
3 4
5 6
7 8
9 10
11 12
J1
TSW-106-08-G-D-RA
AGND AGND
ISO_12V_L
PGND
PGND
PGND
0.022µF
C18
PGND
Bot_FET_FAULT
Bot_FET_OC
Bot_FET_TEMP
RDRV_H
IN_H
TEMP_H
FAULT_H
OC_H
OC_L
TEMP_L
VNEG_L
VNEG_H
DNP
PGND
PGND
Have R15 close to GaN FET
10uF
C11
PGND
0.1uF
C19
0.1uF
C38
SW
SW
SW
Have R6 close to GaN FET
DNP
300
R15
300
SDEM20161T-4
R6
R7MS
SDEM20161T-4R7MS
Max. 1A current on the FET
0.22µF
C12
0.22µF
C2
3
2
1
4
5
6
T2
750315371
5V
5V_H
PGND
TP3PGND
TP6 SW
HV TP5
PGND
HVBUS
SW
2
4
1
3
~
~
+
-
D2
ISONC3
3
2
1
4
5
6
T1
750315371
2
4
1
3
~
~
+
-
D3
VCC1 1 VCC2
16
EN1 7 EN2
10
INA 3
INB 4
INC 5
IND
11
OUTA
14
OUTB
13
OUTC
12
OUTD 6
GND1 2
GND1 8
GND2
9GND2
15
ISO7741FDBQR
U3
L1
L2
iINGND
iINGND
iINGND
i
INGND
0
R10
12
3
4
L3
12
3
4
L4
Top_FET_PWM
Top_FET_FAULT
Top_FET_OC
Top_FET_TEMP
TH1 TH2 TH3 TH4
HS push-pin
NC1
NC2
NC3
NC4
TP2
PGND
TP4
PGND
25V
2.2uF
C3
25V
2.2uF
C13
20.0k
DNP
R5
DNP
16V
D6
VDD
46 DRAIN 1
DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5
DRAIN 6
DRAIN 7
DRAIN 8
DRAIN 9
DRAIN 10
DRAIN 11
DRAIN 12
DRAIN 13
DRAIN 14
DRAIN 15
DRAIN 16
SOURCE 17
SOURCE 18
SOURCE 19
SOURCE 20
SOURCE 21
SOURCE 22
SOURCE 23
SOURCE 24
SOURCE 25
SOURCE 26
SOURCE 27
SOURCE 28
SOURCE 29
SOURCE 30
SOURCE 31
SOURCE 32
SOURCE 33
SOURCE 34
SOURCE 35
SOURCE 36
SOURCE 37
SOURCE 38
SOURCE 39
SOURCE 40
FAULT
48
OC
50
BBSW
43
IN
47
LDO5V
53
RDRV
52
TEMP
51
VNEG
41 VNEG
42
GND 44
GND 45
GND 49
GND 54
PAD 55
LMG3422R030RQZT
U1
50V
100pF
C7
50V
100pF
C8
D1
GB01SLT06-214
TP8
Top_FET_FAULT
TP9
Bot_FET_FAULT
TP10
AGND
TP11
AGND
300
R8
300
R9
68pF
C25
68pF
C24
Top_FET_FAULT
Top_FET_OC
AGND AGND
FAULT_L
Top_FET_FAULT
1
23
Q1
MGSF1N02LT1G
20.0k
DNP
R17
20.0k
R14
Top_FET_TEMP
Top_FET_PWM
FAULT_L
TEMP_L
OC_L
10.0
R18
OUTA INA
iPGND
i PGND
GND1 8
INA 2
INB 3
INC 4
IND 5
OUTE 6
OUTF 7
VCC1 1
GND2
9
INE
11
OUTA
15
OUTB
14
OUTC
13
OUTD
12
VCC2
16
INF
10
ISO7762FQDBQRQ1
U4
U2NC1
U2NC16
U2NC17
U2NC54
U1NC1
U1NC16
U1NC17
U1NC54
i
VHV
i VHV
i PGND
i PGND
i VSWNET
i VSWNET
i VSWNET
i VSWNET
2.05
R2
0
R4
0
R11
Figure 3-1. LMG342XEVM-04X Schematic
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4 Mother Board Schematic
AGND
AGND
AGND
AGND
Vin
HS_FET_PWM
LS_FET_PWM
PGND
VAUX 12V
AGND
PGND
PGND
PGND
PGNDAGND
12V
AGND
VIN
1
EN
3
SS
5GND 4
FB 6
RON
2
VOUT 7
EP 8
LMZ12001EXTTZ/NOPB
U4
AGND
AGND
AGND
AGND
630V
0.1uF
CIN3
630V
0.1uF
CIN4
1
2 3 4 5
J3
112404
1
2 3 4 5
J8
112404
D1
BAT54WS-7-F
71
SN74LVC3G14DCUTG4
U3A
53
SN74LVC3G14DCUTG4
U3B
26
SN74LVC3G14DCUTG4
U3C
GND 4 VCC
8
SN74LVC3G14DCUTG4
U3D
D3
BAT54WS-7-F
53
SN74LVC3G14DCUTG4
U5B
26
SN74LVC3G14DCUTG4
U5C
71
SN74LVC3G14DCUTG4
U5A
AGND
GND 4 VCC
8
SN74LVC3G14DCUTG4
U5D
7
1
2
U1A
3
5
6
U1B
VCC
8GND 4
U1C
AGND
1
3
5
7
9
11
J5A
HLE-106-02-G-DV-BE-A
2
4
6
8
10
12
J5B
HLE-106-02-G-DV-BE-A
1
2
J6
282834-2
630V
0.1uF
COUT3
630V
0.1uF
COUT4
0
R9
1
2
3
J7
TSW-103-07-G-S
SH-J1
SNT-100-BK-G
1.6k
R31
Green
12
5V_EN
LG L29K-G2J1-24-Z
12 34
47uH
47uH
L3
HS_FET_PWM
HS_FET_OCZ
HS_FET_TEMP
HS_FET_FAULTZ
AGND
LS_FET_PWM
LS_FET_OCZ
LS_FET_TEMP
LS_FET_FAULTZ
1.18k
R26
AGND
PGND
30k
R16
30k
R17
30k
R11
30k
R12
30k
R18
30k
R13
30k
R19
30k
R14
30k
R20
30k
R10
HVBUS
Red
12
HS_FLT
LS L29K-G1J2-1-Z
5
4
1
2
3
6
J2
TSW-106-07-G-S
5
4
1
2
3
6
J4
TSW-106-07-G-S
12VVAUX
ACMGND AGND2
AGND1
HVIN
HVOUT
PGND4
SW PGND5
PWM_HS
PWM_LS
HS_FET_PWM
LS_FET_PWM
5V
5V
5V
5V
5V
LS_FET_FAULTZ
SH-J2
SNT-100-BK-G
SH-J3
SNT-100-BK-G
LS_FET_TEMP_FILT
HS_FET_TEMP_FILT
3
5
6
U2B
VCC
8GND 4
U2C
AGND
AGND
5V
AGNDAGND
Red
12
LS_FLT
LS L29K-G1J2-1-Z
5V
AGNDAGND
5K
R3
3224X-1-502E
5K
R15
3224X-1-502E
5V
1
2
J12
282834-2
AGND
5V
AGND
25V
10uF
C15
6.3V
100uF
C17
22nF
50V
C16
33.2k
R28
22nF
50V
C20
AGND
600V
150uF
C25
3.3k
R1
3.3k
R5
LS_FET_OCZ
HS_FET_OCZ
7
1
2
U2A
HS_FET_FAULTZ
1
2
3
J14
TSW-103-07-G-S
SH-J5
SNT-100-BK-G
J17
3267
J16
3267
J18
3267
1
2
J10
TSW-102-07-G-S
1
2
J11
TSW-102-07-G-S
5V
100k
R6
100k
R22
3 1 2
4
900V
20µF
C22
Yellow
12
HS_OC
SML-E12Y8WT86
5V
AGNDAGND
3.3k
R29
HS_FET_OCZ
Yellow
12
LS_OC
SML-E12Y8WT86
5V
AGNDAGND
3.3k
R30
LS_FET_OCZ
0
R2
0
R4
Green
12
HVIN_EN
LG L29K-G2J1-24-Z
VAUX
HVBUS
HVOUT
PWM_HS
PWM_LS
PGND
SW
L2
12V aux
1µF
25V
C1
1µF
25V
C9
1µF
25V
C18
50V
39pF
C10
50V
39pF
C23
50V
39pF
C12
50V
39pF
C5
50V
39pF
C14
50V
39pF
C21
25V
10uF
C19
1
2
J1
0395443002
1
2
J9
0395443002
1
HVBUS1
1
SW1
1
PGND1
1
HVBUS2
1
SW2
1
PGND2
SH-J4
SNT-100-BK-G
1
2
J13
TSW-102-07-G-S
6.20k
R25
HS_FET_TEMP
AGND
HS_FET_TEMP_FILT
105k
R8
50V
1600pF
C2
HS_FET_OCZ
100
R7 HS_FET_FAULTZ
HS_FET_PWM
5V
AGND
1µF
25V
C8
12V
AGND
1µF
25V
C6
LS_FET_TEMP
AGND
LS_FET_TEMP_FILT
105k
R27
50V
1600pF
C3
LS_FET_OCZ
100
R21 LS_FET_FAULTZ
LS_FET_PWM
1
2
3
J15
TSW-103-07-G-S
AGND 12V
TACH
TACH
Figure 4-1. LMG342X-BB-EVM Schematic
www.ti.com LMG342XEVM-04X Schematic
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AGND
1
2 3 4 5
J3
112404
AGND
1 6
5
2
U1A
SN74LVC2G14DCKR
1µF
C9
AGND
5V
39pF
C13
D2
BAT54WS-7-F
AGND
AGND
HDEAD1
PWM
1µF
C11 5V
3 4
5
2
U3B
SN74LVC2G14DCKR
39pF
C5
D1
BAT54WS-7-F
AGND
AGND
5V
LDEAD1
1µF
C4 5V
AGND
1.20k
R1
1.20k
R5
HVIN
PGND1
Vin
HVOUT
PGND2
Vout
LOW
HIGH
FAULT
1000pF
C14
AGND
PGND
1µF
C6
1
2
7
48
U2A
SN74LVC2G08IDCTRQ1
5
6
3
48
U2B
SN74LVC2G08IDCTRQ1
5V
AGND
5V
5V
5V
12V aux
FAULT Indicator
SW1 PGND3
AGND
0
R9
1
2
J6
282834-2
5µF
C1
5µF
C15
HIGH
LOW
PGND
PGND
PGND PGND
39pF
C7
0
R2
AGND
0
R4
39pF
C12
AGND
39pF
C10
AGND
0
R3 VDC
PGND
SW
AGND
5V
1 6
5
2
U3A
SN74LVC2G14DCKR
0.1µF
630V
C3
0.1µF
630V
C2
0.1µF
630V
C17
0.1µF
630V
C16
1µF
C18
AGND
1µF
C20
LOW_2
HIGH_2
HIGH_2
LOW_2
5
4
1
2
3
6
J4
TSW-106-07-G-S
1µF
C8
VAUX
ACMGND
1
2
3
4
5
6
J2
0448120024
AGND1
AGND4
5V
AGND
3 4
5
2
U1B
SN74LVC2G14DCKR
AGND3
0
R23
0
R21
IN
1OUT 3
GND 2 TAB
4
U4
LM2940IMP-5.0/NOPB 33µF
C19
10µF
C21
12V
12V
12V
Green
1
2
D4
Red
1
2
D3
1.6k
R6
1.6k
R8
30k
R10
30k
R16
30k
R11
30k
R17
30k
R18
30k
R12
30k
R13
30k
R19
30k
R20
30k
R14
1
2
3
J7
TSW-103-07-G-S
5V
Red
1
2
D5
PGND
SH-J1
1
2
J5
282841-2
1
2
J1
282841-2
1
2
3
4
47µH
L3
DRQ73-470-R
TI HV Synchronous Buck Motherboard
150µH
L1
150µH
L2
10.0k
R7
5V
AGND
AGND
AGND
AGND2
Copyright © 2016, Texas Instruments Incorporated
Figure 4-2. LMG34XX-BB-EVM Schematic
LMG342XEVM-04X Schematic www.ti.com
12 LMG342XEVM-04X User Guide SNOU176A – OCTOBER 2020 – REVISED JANUARY 2022
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5 Recommended Footprint
When the EVM daughter card is used in a custom design system, the recommended footprint to interface with
the LMG342XEVM-04X daughter card is shown below.
Figure 5-1. Recommended Footprint for LMG342XEVM-04X
www.ti.com Recommended Footprint
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6 Test Equipment
DC Voltage Source: Capable of supplying the input of the EVM up to 480 V.
DC Bias Source: Capable of 12-V output up to 1.5-A.
Function Generator: Capable of 0-V to 5-V square wave output with adjustable duty cycle and frequency in
the operating range. TI recommends operating the LMG342XEVM-04X and mother boards with a switching
frequency between 50 kHz to 200 kHz in hard-switching converters.
Note
TI provides a custom interposer board that must be used when the LMG342XEVM-04X is paried with
the LMG34XX-BB-EVM. The interposer board is not needed with LMG342x-BB-EVM.
Oscilloscope: Capable of at least 200 MHz operation. A 1 GHz or greater oscilloscope and probes with short
ground springs are required for accurate measurements.
DC Multimeter(s): Capable of 600-V measurement, suitable for determining operation and efficiency (if desired).
DC Load: Capable of 600-V operation at up to 20-A in current-mode operation.
Fan: For the heatsink-version EVM daughter card, a dedicated cooling fan is attached on the back side of the
heatsink. Please make sure the fan is powered by the 12-V power supply before test.
Test Equipment www.ti.com
14 LMG342XEVM-04X User Guide SNOU176A – OCTOBER 2020 – REVISED JANUARY 2022
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7 Test Procedure When Paired With LMG342X-BB-EVM
7.1 Setup
The inductor on LMG342X-BB-EVM is capable of around 3-kW operation. For higher power levels, use an
external inductor.
TI recommends the following procedure to set up the LMG342X-BB-EVM with the LMG342XEVM-04X:
1. Connect the LMG342XEVM-04X to LMG342X-BB-EVM as shown in Figure 7-1. The area for connection on
the mother board is shown in Figure 7-2.
2. Install the LMG342X-BB-EVM inside a ventilated HV safety box.
3. Disconnect jumper J13 to enable the 12-V to 5-V onboard power conversion.
4. Disconnect jumper J12.
5. If the onboard complementary PWM generation circuits are used to generate the dead time, please connect
Pin 2 to Pin 3 for header J7 and J14 with jumpers. Under this configuration, only one PWM signal is required
and it can be connected to either J3 or J8.
6. If two complementary PWM signals with dead time are provided to J3 (high-side PWM) and J8 (low-side
PWM), then please connect Pin 1 to Pin 2 for header J7 and J14 (Pin1 of J7 and J14 are indicated in Figure
7-2). This action allows the two PWM signals to directly control the high-side and low-side devices.
7. If fault interlock feature is desired, please connect jumper J10 and J11. Otherwise, disconnect them and the
PWM signals can always pass through to the devices.
8. Set the signal generator to a desired frequency and duty cycle (that is, 100 kHz, and 50% duty cycle). 5 V for
high input and 0 V for low input.
9. Connect the signal generator output to the LMG342X-BB-EVM PWM input as shown in Figure 7-2.
10. Connect 12-V, 2-A DC power supply to the LMG342X-BB-EVM 12-V bias supply as shown in Figure 7-2.
11. Connect the high voltage power supply to the LMG342X-BB-EVM high voltage input for buck mode (High
Voltage) as shown in Figure 7-2.
12. Provide 12-V bias supply to fan by connecting the 3-pin power cord from fan to J15.
Figure 7-1. LMG342X-BB-EVM Motherboard With LMG342XEVM-04X
www.ti.com Test Procedure When Paired With LMG342X-BB-EVM
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12V Input 5V LED Fault LEDs
Daughter Card
Connector
High Voltage
Input
Low side
PWM
Pin1 of J7 & J14
High side
PWM
Figure 7-2. Connector and LEDs on the LMG342X-BB-EVM
7.2 Start-Up and Operating Procedure
1. Turn on +12VDC to the LMG342X-BB-EVM. Watch the power supply for the DC current to settle down after
approximately 3 to 5 seconds.
2. Make sure all the fault LEDs are off and the 5-V LED is on.
3. Turn on +12VDC to enable the fan.
4. Turn on the function generator to output the continuous pulse, and check the deadtime of the PWM signals.
5. User proper probes for measurement. To measure the fast switching transient in the switch-node, it
is recommended to use the high-bandwidth high-voltage passive probes with minimized ground loop
connections.
6. It is recommended to add common-mode chokes to the measurement signals and to the power input/output
connections.
7. Enable the high voltage power supply and make sure to ramp the voltage up gradually from 0V to the
desired bus voltage (up to 480V). As the voltage is ramping up, the HV LED will turn on and become
brighter.
Figure 7-3. Switch-Node Voltage Measurement with High-Bandwidth Probe and Pigtail Ground
Connection
Test Procedure When Paired With LMG342X-BB-EVM www.ti.com
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WARNING
Do NOT turn on the device at the absolute maximum voltage. TI recommends to start the device at
or below 480 V. Slowly increase the input voltage and monitor the VSW to ensure the peak voltage
does not exceed the absolute maximum rating of 600 V.
7.3 Test Results
In this test example, a synchronous buck converter operation is implemented. The input voltage is 400 V, and
the output voltage is 200 V with 50% duty cycle. With the heatsink-version EVM, the inductor current goes to
20 A in this test, and an output power of 4 kW is achieved. The waveform for continuous operation is shown
in Figure 7-4 . The slew rate is set to 85 V/ns by connecting 20 kohm between Rdrv and ground. From this
waveform, a turn-on voltage slew rate of 85 V/ns is observed at 400 V/20 A switching conditions.
The turn-on slew-rate of the device can be easily adjusted from 30V/ns to 150V/ns by changing the Rdrv resistor
values. This is also verified from the test results shown in Figure 7-7. The adjustable slew-rate feature provides a
flexibility to adapt the device's switching speed in different applications.
rrent(10A/div)
Node Voltage(100V/div)
Slew rate: 85V/ns
Figure 7-4. 85 V/ns at 400 V/20 A
Load Current(10A/div)
Switch Node Voltage(100V/div)
Slew rate: 100V/ns
Figure 7-5. 100 V/ns at 400 V/20 A
www.ti.com Test Procedure When Paired With LMG342X-BB-EVM
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Load Current
(10A/div)
Switch Node
Voltage
(100V/div)
Slew rate: 30V/ns
Figure 7-6. 30 V/ns at 400 V/20 A
Load Current(5A/div)
Switch Node Voltage(100V/div)
Slew rate: 150V/ns
Figure 7-7. 150 V/ns at 400 V/5 A
7.4 Shutdown Procedure
1. Turn off the high voltage power supply then PWM. Wait until red “HV Enable” LED turns off.
2. Disable the 12-V bias supply.
7.5 Additional Operating Notes
• Fault protection on the LMG342X-BB-EVM is not latching, therefore PWM will resume if a fault clears and the
LMG342X-BB- EVM is still operational.
Test Procedure When Paired With LMG342X-BB-EVM www.ti.com
18 LMG342XEVM-04X User Guide SNOU176A – OCTOBER 2020 – REVISED JANUARY 2022
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8 Test Procedure When Paired With LMG34XX-BB-EVM
8.1 Setup
The following procedure is recommended to set up the LMG34XX-BB-EVM with the LMG342XEVM-04X. The
inductor on the LMG34XX-BB-EVM is capable of up to 1.7-kW operation. For a higher power level, use an
external inductor.
Figure 8-1 shows the LMG342XEVM-04X connected to the LMG34XX-BB-EVM.
Note
TI provides a custom interposer board that must be used when the LMG342XEVM-04X is paired with
the LMG34XX-BB-EVM. The interposer board is not needed with LMG342x-BB-EVM.
Figure 8-1. LMG342XEVM-04X Connected to the LMG34XX-BB-EVM
www.ti.com Test Procedure When Paired With LMG34XX-BB-EVM
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LMG342XEVM-04X User Guide 19
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Figure 8-2 shows the LMG34XX-BB-EVM power and probe connection points.
Figure 8-2. Recommended Connection Points
PCB Notes:
• A: Probe points for gate drive logic
• B: 100-mil header for PWM input, PWM signals to LMG342XEVM-04X and FAULT output
• C: BNC connector for PWM input
• D: 12-V bias supply input
• E: FAULT protection option header
• F: Power stage high voltage input
• G: Probe point for power stage switch node
• H: Power stage high voltage output
To connect the LMG342XEVM-04X to the LMG34XX-BB-EVM:
1. Connect the oscilloscope or multimeter probes to the desired test points in A or G.
2. Connect the 12-V bias supply, connect load to output, and connect the input supply to input.
3. Connect the function generator to either the BNC connector PWM input at C or 100-mil header connector
input at pin 6 (PWM) and pin 5 (GND) at B.
4. Connect 12-V bias supply to the fan attached on the EVM, or enable an external fan to direct airflow across
the heat sink attached to the LMG342XEVM-04X.
Test Procedure When Paired With LMG34XX-BB-EVM www.ti.com
20 LMG342XEVM-04X User Guide SNOU176A – OCTOBER 2020 – REVISED JANUARY 2022
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