Texas Instruments LMK04832SEPEVM User manual

User’s Guide
LMK04832SEPEVM User’s Guide
ABSTRACT
The LMK04832SEPEVM (EVM) is designed to evaluate the performance and features of the LMK04832-SEP
Space Grade Ultra-Low-Noise JESD204B Dual-Loop Clock Jitter Cleaner from Texas Instruments. The user’s
guide describes how to set up and operate the EVM. The LMK04832-SEP device on each EVM is an
Engineering Model, intended for engineering evaluation only. The devices and EVMs are not suitable for
qualification, production, radiation testing or flight use.
Table of Contents
1 Evaluation Board Kit Contents..............................................................................................................................................2
2 Quick Start...............................................................................................................................................................................2
2.1 Quick Start Description...................................................................................................................................................... 2
3 PLL Loop Filters and Loop Parameters................................................................................................................................4
3.1 PLL1 Loop Filter.................................................................................................................................................................4
3.2 PLL2 Loop Filter.................................................................................................................................................................4
4 Default TICS Pro Mode........................................................................................................................................................... 5
5 Using TICS Pro to Program the LMK04832-SEP..................................................................................................................5
5.1 Start TICS Pro Application................................................................................................................................................. 5
5.2 Select Device..................................................................................................................................................................... 5
5.3 Program the Device........................................................................................................................................................... 6
5.4 Restoring a Default Mode.................................................................................................................................................. 7
5.5 Visual Confirmation of Frequency Lock..............................................................................................................................7
5.6 Enable Clock Outputs........................................................................................................................................................ 7
6 Evaluation Board Inputs and Outputs.................................................................................................................................. 9
7 Recommended Test Equipment.......................................................................................................................................... 12
8 Schematics............................................................................................................................................................................13
9 Bill of Materials..................................................................................................................................................................... 16
A USB2ANY Firmware Upgrade..............................................................................................................................................21
B TICS Pro Usage.................................................................................................................................................................... 25
11.1 Communication Setup.................................................................................................................................................... 25
11.2 User Controls..................................................................................................................................................................26
11.3 Raw Registers Page.......................................................................................................................................................27
11.4 Set Modes Page.............................................................................................................................................................28
11.5 Holdover Page................................................................................................................................................................29
11.6 CLKinX Control Page..................................................................................................................................................... 30
11.7 PLL1 and 2 Page............................................................................................................................................................31
11.8 SYNC / SYSREF Page...................................................................................................................................................32
11.9 Clock Outputs Page........................................................................................................................................................33
11.10 Other Page................................................................................................................................................................... 34
11.11 Burst Mode Page.......................................................................................................................................................... 35
Trademarks
PLLatinum™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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1 Evaluation Board Kit Contents
Table 1-1 lists the components found in the evaluation board kit.
Table 1-1. EVM Contents
HSDC140
Evaluation Board LMK04832SEPEVM Evaluation Board with VCXO (1)
USB cable USB Cable A Plug to Micro B Plug cable (1)
2 Quick Start
Figure 2-1. Quick Start Diagram
2.1 Quick Start Description
The LMK04832SEP EVM allows full verification of the device functionality and performance specifications. To
quickly set up and operate the board with basic equipment, refer to the quick start procedure below and test
setup shown in Figure 2-1.
1. Connect a voltage of 4.5 V to the VCC SMA connector or terminal block. The LMK04832-SEP and onboard
VCXO operate at 3.3 V provided by the onboard TPS73801-SEP LDO and LP5900 LDO, respectively.
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2. Connect a reference clock to the CLKin1* port from a signal generator or other source. Use 122.88 MHz for
the default configuration.
3. Connect a USB A Plug-B Micro Plug cable to a PC and the USB connector (J45) at EVM.
4. Program the device with TICS Pro. TICS Pro is available for download at: http://www.ti.com/tool/ticspro-sw.
a. Select LMK04832-SEP from the Select Device menu. Click Select Device → Clock Generator/Jitter
Cleaner (Dual Loop).
b. Select USB2ANY mode from the Communication Setup window. To access this, select USB
communications → Interface. Click Identify to confirm that the PC to USB communication is working.
A blinking green LED on the USB2ANY indicates the PC is able to communicate through the USB2ANY.
c. Select a default mode from the Default Configuration menu. For the quick start, use: CLKin1 122.88
MHz, OSCin 122.88 MHz, VCO1 2949.12 MHz.
d. Press Ctrl+L at least once to load all registers. Alternatively, click the USB communications → Write All
Registers menu, the Write All Registers button on toolbar, or the Raw Registers page (see Section 11.3).
5. Measurements may be made at an active CLKout port through the SMA connector.
2.1.1 Clock Outputs Page Description
Clock outputs are grouped in pairs. This description applies for all clock outputs on the Clock Outputs page of
the TICS Pro GUI (see Section 11.9).
1 2 4
20
5 6 7 8 13 14 15 16 17
19
9 11 12
21 22 23 2524 26 2718
3 10
Figure 2-2. Clock Outputs Page Description Diagram
1. SYNC_DISX: Prevent the divider from being reset by SYNC/SYSREF path.
2. DCLKX_Y_DIV: Divide value for the device clock. If set to 1, then DCLKX_Y_DCC (DCC & HS) must = 1.
3. DDLYdX_EN: Enable dynamic digital delay for this divider.
4. DCLKX_Y_HSg_PD: If clear, glitchless half-step adjustments are enabled.
5. DCLKX_Y_HS: Set half step for this divider. DCLKX_Y_DCC (DCC & HS) must = 1.
6. DCLKX_Y_DDLY_PD: If clear, the digital delay value is assured when a SYNC occurs.
7. DCLKX_Y_DDLY: The digital delay value to be used when a SYNC occurs.
8. DCLKX_Y_PD: Power down the device clock divider and path.
9. DCLKX_Y_DCC: Enable duty cycle correct and half-step for this device clock divider.
10. DCLKX_Y_POL: If set, polarity of device clock is inverted.
11. DCLKX_Y_BYP: If set, the device clock divider is bypassed for CLKoutX and #15 must be CML.
12. CLKoutX_SRC_MUX: Select device clock or SYSREF clock path for CLKoutX.
13. CLKoutX_Y_IDL: Increase input drive level to improve noise floor at cost of power (approximately 2 mA).
14. SYSREF_GBL_PD: Set the conditional for SCLKX_Y_DIS_MODE registers.
15. CLKoutX_FMT: Set the clock output format for CLKoutX.
16. CLKoutX_Y_ODL: Increase output drive level to improve noise floor at cost of power (approximately 3 mA).
No effect for CLKoutX in bypass mode.
17. CLKoutX_Y_PD: Power down the entire CLKoutX_Y clock pair.
18. SCLKX_Y_DDLY: The SYSREF clock digital delay setting.
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19. SCLKX_Y_HS: Set half step for the SYSREF output.
20. SCLKX_Y_ADLY_EN: Enable analog delay for the SYSREF clock path.
21. SCLKX_Y_ADLY: If enabled, set the analog delay for the SYSREF clock path.
22. SCLKX_Y_PD: Power down the SYSREF clock path.
23. SCLKX_Y_POL: If set, polarity of SYSREF output clock is inverted.
24. CLKoutY_SRC_MUX: Select device clock or SYSREF clock path for CLKoutY.
25. SCLKX_Y_DIS_MODE: Set the output state of output clock drivers for the SYSREF clock. For values of 1
and 2 works in conjunction with control on this list #14, SYSREF_GBL_PD.
26. CLKoutY_FMT: Set the clock output format for CLKoutY.
27. Clock output frequency for CLKoutX and CLKoutY.
2.1.2 TICS Pro Tips
Mousing over different controls will display a help prompt with the register address, the data bit location and
length, and a brief register description in the lower-left Context help pane.
You can set a register equal to 0 or uncheck a register’s checkbox to perform the same action. Similarly, setting
a register equal to 1 is the same as checking that register’s checkbox.
3 PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to substitute
the phase noise of a low-noise oscillator (VCXO) for the phase noise of a dirty reference clock. The first PLL is
typically configured with a narrow loop bandwidth to minimize the impact of the reference clock phase noise. The
reference clock consequently serves only as a frequency reference rather than a phase reference.
The loop filters on the LMK04832SEPEVM evaluation board are set up using the approach above. The loop filter
for PLL1 has been configured for a narrow loop bandwidth (< 1 kHz). The specific loop bandwidth values depend
on the phase noise performance of the oscillator mounted on the board. Table 3-1 and Table 3-2 contain the
parameters for PLL1 and PLL2 for each oscillator option.
TI’s PLLatinum™ Sim tool can be used to optimize PLL phase noise/jitter for given specifications. See https://
www.ti.com/tool/PLLATINUMSIM-SW for more information.
3.1 PLL1 Loop Filter
Table 3-1. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO
122.88 MHz VCXO PLL(1)
Phase Margin 50˚ Kφ (Charge Pump) 450 µA
Loop Bandwidth 14 Hz Phase Detector Freq 1.024 MHz
VCO Gain 2.5 kHz/V
Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz (To PLL 2)
Loop Filter Components LF1_C1 (C31) = 100 nF LF1_C2 (C14) = 680 nF LF1_R2 (R44) = 39 kΩ
(1) Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.
3.2 PLL2 Loop Filter
Table 3-2. Integrated VCO PLL
PARAMETER(1) LMK04832-SEP UNIT
VCO0 VCO1
LF2_C1 (C12) 0.047 nF
LF2_C2 (C10) 3.9 nF
C3 (internal) 0.03 nF
C4 (internal) 0.01 nF
LF2_R2 (R41) 0.62 kΩ
R3 (internal) 0.2 kΩ
R4 (internal) 0.2 kΩ
Charge Pump Current, Kφ 3.2 mA
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Table 3-2. Integrated VCO PLL (continued)
PARAMETER(1) LMK04832-SEP UNIT
VCO0 VCO1
Phase Detector Frequency 122.88 MHz
Frequency 2457.6 2949.12 MHz
Kvco 13.0 25.0 MHz/V
N 20 24
Phase Margin 68 71 degrees
Loop Bandwidth 210 326 kHz
(1) PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφ and N will change the loop bandwidth.
4 Default TICS Pro Mode
TICS Pro saves the state of the selected LMK04832-SEP device when exiting the software. Table 4-1 lists the
available modes for the software. To ensure a common starting point, go to the Default Configuration menu and
select the appropriate device configuration for your device.
Table 4-1. Default TICS Pro Modes for the LMK04832-SEP
DEFAULT TICS PRO MODE DEVICE MODE CLKin FREQUENCY OSCin FREQUENCY
CLKin1 122.88 MHz, OSCin
122.88 MHz, VCO1 2949.12 MHz
Dual PLL, Internal VCO 122.88 MHz 122.88 MHz
Figure 4-1. Selecting a Default Mode for the LMK04832-SEP Device
5 Using TICS Pro to Program the LMK04832-SEP
This section will demonstrate how to use TICS Pro. For more information on using TICS Pro, refer to Appendix
A. TICS Pro is available for download at http://www.ti.com/tool/ticspro-sw.
Before proceeding, be sure to follow the instructions in Section 2 to ensure proper hardware connections.
5.1 Start TICS Pro Application
Click Start → Programs → Texas Instruments → TICS Pro.
The TICS Pro program is installed by default to the Texas Instruments application group.
5.2 Select Device
Click Select Device → Clock Generator/Jitter Cleaner (Dual Loop) → LMK04832-SEP.
After start-up, the TICS Pro will load to the last used device. A recent history of used devices can be quickly
accessed under the File menu. To load a new device, click Select Device from the menu bar, select the
subgroup, then select the device to load.
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Figure 5-1. Selecting the LMK04832-SEP
5.3 Program the Device
To program, press Ctrl+L.
Alternatively, click USB communications → Write All Registers from the menu to program the device to the
current state of the register map to the device. Ctrl+L is the accelerator key assigned to the Write All Registers
option and is very convenient.
Figure 5-2. Loading the Device
After the device is initially loaded, TICS Pro will automatically program changed registers, so it is not necessary
to reload the device upon subsequent changes in the device configuration. It is possible to disable this
functionality by ensuring there is no checkmark by the Options → AutoUpdate.
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A default mode will be restored in the next step, therefore this step is not necessary. It is included, however, to
emphasize the importance of pressing Ctrl+L to load the device at least once after starting TICS Pro, restoring a
mode, or restoring a saved setup using the File menu.
See TICS Pro instructions located at http://www.ti.com/tool/ticspro-sw/.
5.4 Restoring a Default Mode
Click Default configuration → CLKin1 122.88 MHz, OSCin 122.88 MHz, VCO1 2949.12 MHz. Press Ctrl+L to
restore the default configuration.
Figure 5-3. Setting the Default Configuration for LMK04832-SEP
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point. This
is important because when TICS Pro is closed, the software remembers the last settings used for a particular
device. Again, remember to press Ctrl+L as the first step after loading a default mode.
5.5 Visual Confirmation of Frequency Lock
After a default mode is restored and loaded, LED D1 and D2 must illuminate when PLL1 and PLL2 are
locked to the reference clock applied to CLKin1. This assumes PLL1_LD_MUX = PLL1_DLD, PLL2_LD_MUX =
PLL2_DLD, and PLLX_LD_TYPE = Output (Push-Pull).
5.6 Enable Clock Outputs
The LMK04832-SEP offers programmable clock output buffer formats, the evaluation board is shipped with
pre-configured output terminations. Refer to Table 6-1 to see the list of output formats available and what output
formats your hardware is configured for out of the factory.
To measure phase noise at one of the clock outputs (for example, CLKout0):
1. Go to the Clock Outputs page (Section 11.9).
2. Uncheck CLKoutX_Y_PD in the Clock Output box to enable the channel.
3. Set the following as needed:
a. For Device Clock:
i. DCLKX_Y_PD = 0 in Clock Mode Select box
ii. Set Bypass Div (DCLKX_Y_BYP) or Clock Divider (DCLK0_1_DIV) as desired for device clock
frequency:
1. If bypass mode is set, CLKoutX must be set to a CML output format. Bypass mode is not
available on CLKoutY.
2. If Clock Divider = 1, then DCLKX_Y_DCC must be set for clock output.
iii. Phase of the device clock can be adjusted with:
1. Static Digital delay (DCLKX_Y_DDLY) after a SYNC. Digital Delay (DCLKX_Y_DDLY_PD) must
be powered up.
2. Dynamic Digital delay (DDLYdX_EN), then programming DDLYd_STEP_CNT. Digital Delay
(DCLKX_Y_DDLY_PD) must be powered up. Press the Send button at top-right of Clock
Outputs window to program the DDLYd_STEP_CNT field multiple times.
3. Half Step bit (DCLKX_Y_HS) if DCC & HS (DCLKX_Y_DCC) is set.
4. The Polarity bit (DCLKX_Y_POL)
iv. Select the device clock for CLKoutX or CLKoutY with CLKout#_SRC_MUX = 0 (Device Clock) as
desired.
b. While the phase noise of a SYSREF Clock is typically not of concern, to configure an output for
SYSREF:
i. SCLKX_Y_PD = 0 in Clock Mode Select box
ii. Phase of the SYSREF clock can be adjusted:
1. Local digital delay can be set with SCLKX_Y_DDLY.
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2. Local analog delay can be set by enabling with ADLY_EN = 1 (SCLKX_Y_ADLY_EN) and then
setting SCLKX_Y_ADLY to the desired time delay.
3. Global digital delay can be set with SYSREF_DDLY, but this delay change will take effect only
after a SYNC.
iii. Enable SYSREF outputs globally. The necessary bits depend upon the type of SYSREF to be
enabled. For a simple continuous SYSREF (not recommended in final application due to extra
power consumption and crosstalk), set SYSREF_PD = 0, SYSREF_MUX = 0x03 (Continuous), and
SYNC_DISSYSREF = 1.
iv. Select the SYSREF clock for CLKoutX or CLKoutY with CLKout#_SRC_MUX = 1 (SYSREF) as
desired.
Figure 5-4. Setting Digital Delay, Clock Divider, Analog Delay, and Output Format
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument with
a single-ended, 50-Ω input as follows:
a. For LVDS:
i. A balun (like ADT2-1T or a high-quality Prodyn BIB-100G) is recommended for differential-to-single-
ended conversion.
b. For LVPECL:
i. A balun can be used, or
ii. One side of the LVPECL signal can be terminated with a 50-Ω load and the other side can be run
single-ended to the instrument.
c. For HSDS:
i. A balun (like ADT2-1T or high-quality Prodyn BIB-100G) is recommended for differential-to-single-
ended conversion.
d. For CML:
i. A balun can be used, or
ii. One side of the CML signal can be terminated with a 50-Ω load and the other side can be run
single-ended to the instrument.
e. For LVCMOS:
i. Connect the LVCMOS signal to measurement equipment as desired. If an output of a pair is
not used, TI recommends leaving the output floating close to the IC. Alternatively, place a 50-Ω
termination at the end of an unused trace.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
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6 Evaluation Board Inputs and Outputs
Table 6-1 contains descriptions of the inputs and outputs for the evaluation board. Additionally, some applicable
TICS Pro programming controls are noted for convenience.
Table 6-1. Description of Evaluation Board Inputs and Outputs
CONNECTOR NAME SIGNAL TYPE, INPUT/OUTPUT DESCRIPTION
Clock Outputs
Populated:
CLKout0_P(J1),
CLKout0_N(J2),
CLKout1_P(J3),
CLKout1_N(J4),
CLKout2_P(J6),
CLKout2_N(J5),
CLKout3_P(J8),
CLKout3_N(J7),
CLKout4_P(J9),
CLKout4_N(J10),
CLKout5_P(J12),
CLKout5_N(J11),
CLKout6_P(J13),
CLKout6_N(J14),
CLKout7_P(J16),
CLKout7_N(J15),
CLKout8_P(J17),
CLKout8_N(J18),
CLKout9_P(J20),
CLKout9_N(J19)
Analog, Output
Clock outputs with programmable output buffers.
The output terminations by default on the evaluation board are
shown here:
Clock Output Pair Default Board Termination
CLKout0 LVPECL / LCPECL, 240 Ω
CLKout1 LVPECL / LCPECL, 240 Ω
CLKout2 LVPECL / LCPECL, 120 Ω
CLKout3 LVPECL / LCPECL, 120 Ω
CLKout4 CML, 68 nH - 20 Ω
CLKout5 CML, 50 Ω to Vcc
CLKout6 CML, 68 nH - 20 Ω
CLKout7 CML, 50 Ω to Vcc
CLKout8 LVDS / HSDS
CLKout9 LVDS / HSDS
Each CLKout pair has a programmable LVDS, LVPECL, LCPECL,
HSDS, CML, or LVCMOS buffer. The output buffer type can be
selected in the TICS Pro under the Clock Outputs page (Section
11.9) through the CLKoutX_FMT control. All clock outputs are AC-
coupled to allow safe testing with RF test equipment. If an output
pair is programmed to LVCMOS, each output can be independently
configured (normal, inverted, or off/tri-state). Best performance/EMI
reduction is achieved by using a complementary output mode like
Norm/Inv. TI does NOT recommend using Norm/Norm or Inv/Inv
mode.
Not Populated:
CLKout10_P(J21),
CLKout10_N(J22),
CLKout11_P(J24),
CLKout11_N(J23),
CLKout12_P(J25),
CLKout12_N(J26),
CLKout13_P(J28),
CLKout13_N(J27)
OSCout
OSCout_P(J29)
OSCout_N(J30)
Analog, Output
Buffered outputs of OSCin port.
The output terminations on the evaluation board are shown here:
OSC Output Pair Default Board Termination
OSCout LVPECL, 240 Ω
OSCout has a programmable LVDS, LVPECL, or LVCMOS output
buffer. The OSCout buffer type can be selected in the TICS
Pro under the Clock Outputs page (Section 11.9) through the
OSCout_FMT control.
OSCout is AC-coupled to allow safe testing with RF test equipment.
If OSCout is programmed as LVCMOS, each output can be
independently configured (normal, inverted, inverted, and off/tri-
state). Best performance/EMI reduction is achieved by using a
complementary output mode like Norm/Inv. TI does NOT recommend
using Norm/Norm or Inv/Inv mode.
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Table 6-1. Description of Evaluation Board Inputs and Outputs (continued)
CONNECTOR NAME SIGNAL TYPE, INPUT/OUTPUT DESCRIPTION
Power
VccEXT(J39/J40/TP13)
Vcc(TP12)
Power, Input
Main power supply input for the evaluation board.
The LMK04832SEPEVM default is setup to use the TPS73801-SEP
voltage regulator. This is a space grade (SEP) voltage regulator.
0-Ω resistors R93, R94 and R95 can be re-configured to route
power through the onboard commercial grade LDO, the TPS73801-
SEP. The LMK04832-SEP contains internal voltage regulators for
the VCO and other internal blocks. The clock outputs do not have
an internal regulator, so a clean power supply with sufficient output
current capability is required for optimal performance. If using an
external voltage please ensure the voltage is filtered to get the best
performance on the outputs.
Apply power to either Vcc SMA(J39) or terminal block(J40), but not
both.
Clock Inputs
CLKin0_P(J32),
CLKin0_N(J31),
CLKin1_P(J34),
CLKin1_N(J33)
OSCout_P(J29),
OSCout_N(J30)
Fin0_P(J37),
Fin0_N(J38)
Analog, Input
Reference Clock Inputs for PLL1 or PLL1 (CLKin0, CLKin1, CLKin2)
CLKin1_N is configured by default for a single-ended reference clock
input from a 50-Ω source. The non-driven input pin CLKin1_P can be
configured as R15 - DNI and R216 replace with 0-Ω resistor. CLKin0
is configured by default for a differential reference clock input from a
50-Ω source.
CLKin1 is the default reference clock input selected in the TICS Pro.
If OSCout is to be used as a CLKin2, then the PCB must be updated
to operate as an input instead of an output.
Clock Distribution with Fin0 or CLKin1/Fin1
Fin0 and CLKin1 (Fin1) are shared for use as an RF Input for Clock
Distribution mode or for an external VCO mode.
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use as an external feedback clock input
(FBCLKin) to PLL1 N or PLL2 N for 0-delay mode. Refer to the
LMK04832-SEP (SNAS838) data sheet for more details on using
0-delay mode with the evaluation board and the evaluation board
software.
OSCin,
PLL2 reference/PLL1 feedback
OSCin_P(J36),
OSCin_N(J35)
Analog, Input
Feedback VCXO clock input to PLL1 and Reference clock input to
PLL2.
The single-ended output of the onboard VCXO (Y1/Y2) drives the
OSCin_N input of the device and the OSCin_P input of the device is
connected to GND with 0.1 µF. VCXO Y1 and Y2 may also be used
with differential VCXOs.
An external VCXO may be optionally attached through these SMA
connectors with minor modification to the components going to the
OSCin pins of device.
A single-ended or differential signal may be used to drive the OSCin
pins and must be AC coupled. If operated in single-ended mode, the
unused input must be connected to GND with 0.1 µF.
Refer to the LMK04832-SEP (SNAS838) data sheet Electrical
Characteristics table for PLL2 Reference Input (OSCin)
specifications.
VCO Tuning Voltages
VTUNE1 (TP1/J41)
VTUNE2 (TP2/J42)
Analog, Input/Output
Tuning voltage output from the loop filter for PLL1 and PLL2 of the
LMK04832-SEP. If an external VCXO is used, this tuning voltage can
be connected to the voltage control pin of the external VCXO.
The default board does not come with J41 and J42 populated.
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