Texas Instruments TAS2572 User manual

EVM User's Guide: TAS2572EVM TAS2572
TAS2572 Evaluation Module
Description
The TAS2572EVM has been designed to demonstrate
the performance of TAS2572 in a dual-mono
configuration. This tool utilizes the AC-MB
motherboard to provide an interface and supply
voltages to the EVM daughter card. Up to four devices
can share a common bus through I2S/TDM + I2C
interfaces; two EVMs can be mounted one on top of
each other, as shown in Section 2.9.
Get Started
1. Download TAS2572 data sheet.
2. Order the EVM at TAS2572 product folder.
3. Request access and download PPC3 from
TAS2572 product folder.
4. Visit and ask questions at e2e forum.
Features
• Mono or dual-mono speaker evaluation
• Interface using PurePath Console 3 Windows®
software
• EVM interconnection for up to 4 audio channels
• USB input
• External I2C and I2S/TDM host controller
connection available
Applications
•Mobile Phone, Tablets and Wearables
•Smart Speakers with Voice Assistance
•Bluetooth and Wireless Speakers
TAS2572 Dual-Mono Evaluation Module
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1 Evaluation Module Overview
1.1 Introduction
This user's guide describes the function and use of the TAS2572EVM. This document includes the hardware
configuration instructions, a quick-start guide, jumper and connector descriptions, software description,
schematics, and printed circuit board (PCB) layout that demonstrate TI's recommended practices for these
devices.
This section provides details on what is included inside the evaluation module box, what are TAS2572
capabilities and operation ranges, as well as what is the additional test equipment that can be required for
a full audio evaluation.
1.2 Kit Contents
The evaluation kit consists of the following items:
• TAS2572EVM
• AC-MB controller board
A speaker is not included in the kit, however any speaker can be connected to each of the amplifiers outputs
using the banana jacks or screw headers.
Similarly, a power supply is not part of the kit, but the barrel jack connector can be connected to any power
supply in a range of 2.4V to 5.5V.
1.3 Specification
The TAS2572 is a digital input Class-D audio amplifier optimized for delivering best battery life for real use case
of Music playback and Voice calls.
The integrated boost operation is flexible so that TAS2572 can be implemented in 1S, 2S and 3S battery
applications. TAS2572EVM showcases the 1S battery broadly used in mobile and industrial applications.
TAS2572
OUT_P
OUT_N
VBAT
BGND
GND
IOVDD
PGND
VDD
PVDD
VSNS_N
VSNS_P
SW
VDD
1.65 V - 1.95 V
GREG
DREG
SDZ
AD1
IRQZ
IOVDD
1.2 V / 1.8 V
C3
2.2 µF
C6
0.1 µF
R1
R2 C11
C10
L2
L3
Optional Components if EMI
filtering is required
AD2
C2
1 µF
C1
1 µF
VBAT
2.5 V - 5.5 V
C4
1 µF
VBAT_SNS
(opt.)
L1
1 µF
C5
10 µF
C9
0.1 µF
C7
10 µF
C8
10 µF
3
3
IOVDD
I2S
4
I2C
2
3 4 3
Figure 1-1. Application Diagram for 1 S Battery System
For 2 S battery applications, the boost inductor can be supplied by a higher supply from 4.5V to 9 V. VBAT pin
must still be supplied by a voltage from 2.5V to 5.5V.
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TAS2572
OUT_P
OUT_N
VBAT
BGND
GND
IOVDD
PGND
VDD
PVDD
VSNS_N
VSNS_P
SW
VDD
1.65 V - 1.95 V
GREG
DREG
SDZ
AD1
IRQZ
IOVDD
1.2 V / 1.8 V
C3
2.2 µF
C6
0.1 µF
R1
R2 C11
C10
L2
L3
Optional Components if EMI
filtering is required
AD2
C2
1 µF
C1
1 µF
VDD_5V
3.0 V - 5.5 V
C4
1 µF
VBAT_SNS
(opt.)
L1
1 µF
C5a
10 µF
C9
0.1 µF
C7
10 µF
C8
10 µF
3
3
IOVDD
I2S
4
I2C
2
3 4 3
VBAT2S
4.5 V - 9.0 V
Figure 1-2. Application Diagram for 2 S Battery System
In a 3 S battery application, the integrated boost can be bypassed, and an external power rail up to 14 V can
supply PVDD directly. The boost inductor is not required in this case and SW pins are left open. VBAT pin must
still be supplied by a voltage from 2.5V to 5.5V.
TAS2572
OUT_P
OUT_N
VBAT
BGND
GND
IOVDD
PGND
VDD
PVDD
VSNS_N
VSNS_P
SW
VDD
1.65 V - 1.95 V
GREG
DREG
SDZ
AD1
IRQZ
IOVDD
1.2 V / 1.8 V
C3
2.2 µF
C6
0.1 µF
R1
R2 C11
C10
L2
L3
Optional Components if EMI
filtering is required
AD2
C2
1 µF
C1
1 µF
VDD_5V
2.5 V - 5.5 V
C4
1 µF
VBAT_SNS
(opt.)
C9
0.1 µF
C7
10 µF
3
3
IOVDD
I2S
4
I2C
2
3 4 3
PVDD (ext.)
(VBAT - 14 V)
Figure 1-3. Application Diagram for 3 S Battery System
1.4 Device Information
TAS2572 is a mono, digital-input, Class-D audio amplifier optimized for efficiently driving high peak power into
small loudspeaker applications. The Class-D amplifier is capable of delivering 6W of max average power into 8
Ω load at a battery voltage of 4.2 V. Integrated speaker voltage and current sense provides real time monitoring
of loud speakers. Up to four devices can share a common bus via I2S/TDM + I2C interfaces.
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2 Hardware
2.1 AC-MB Settings
2.1.1 Audio Serial Interface Settings
The AC-MB provides the digital audio signals to the evaluation module from the USB, optical connector, stereo
jack, and external audio serial interface (ASI) header. Figure 2-1 shows a block diagram of the ASI routing on the
AC-MB.
MUX
USB
Optical Input
Stereo Analog
Input
External ASI Header
Source
Selector
(SW2)
Audio
Processor
PCM921 1Optical Output
To EVM
Figure 2-1. AC-MB Audio Serial Interface Routing
Switch SW2 on the AC-MB selects the audio serial bus that interfaces with the TAS2572EVM daughter card.
Next to switch SW2, the AC-MB has a quick reference table to identify the audio serial interface source options
and switch settings. The AC-MB acts as the controller for the audio serial interface, with three different modes of
operation: USB, optical or analog, or external ASI.
2.1.2 USB
The serial interface clocks and data are provided from the USB interface. The sampling rate and format are
determined by the USB audio class driver on the operating system.
The default settings for the USB audio interface are 32-bit frame size, 48-kHz sampling rate, BCLK and FSYNC
ratio is 256, and the format is time division multiplexing (TDM).
The AC-MB is detected by the OS as an audio device with the name TI USB Audio UAC2.0. Figure 2-2
illustrates the AC-MB audio setting for the USB mode of operation.
Figure 2-2. AC-MB USB Audio Setting
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2.1.3 External
In this mode, the audio serial interface clocks for the evaluation board are provided through connector J7 from
an external source. This architecture allows the use of an external system to communicate with the evaluation
board, such as a different host processor or test equipment (for instance, Audio Precision PSIA). The clocks
generated from the USB interface and PCM9211 are isolated with this setting. Figure 2-3 shows the AC-MB
audio setting for the external mode of operation.
Figure 2-3. AC-MB External Audio Setting
Figure 2-4 shows how to connect the external audio interface, with the bottom row for the signal and the top row
for ground.
Figure 2-4. AC-MB Connection with External Audio Serial Interface
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2.2 AC-MB Power Supply
The AC-MB motherboard is powered from a single 5-V power supply. However, the motherboard has different
low-dropout regulators (LDOs) integrated that provide the required power supplies to the different blocks of
the board. Figure 3-1 shows a block diagram depicting the power structure of the AC-MB. The AC-MB can
be powered from the host computer by using the USB 5-V power supply (VBUS) by shorting header J5, USB
POWER. Additionally, the AC-MB can be powered from an external power supply connected to terminal J4,
EXTERNAL POWER. Header J5 must be open for external supply operation. The IOVDD voltage for the digital
signals that is provided to the evaluation module is generated on the motherboard from the main power supply
(USB or external). The voltage levels available are 1.2V, 1.8V and 3.3V, and can be selected via the J3 header
IOVDD. Default setting for TAS2572EVM operation is 1.8V; 3.3V operation cannot be used for TAS2572EVM.
When the motherboard is fully powered and the power supplies from the onboard LDOs are correct, the
green POWER LED (D3) turns ON. The USB READY LED indicates that a successful USB communication is
established between the AC-MB and the host computer.
Figure 2-5. Power -Supply Distribution of the AC-MB
2.3 Default Jumper Setting on TAS2572EVM
Figure 4-1 given below illustrates all the default jumper settings for TAS2572EVM.
Figure 2-6. Default Jumper Settings
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Table 4-1 shows the default positions for all the jumpers on TAS2572EVM.
Table 2-1. Default Jumper Settings
Jumper Setting Description
J7 Insert IOVDD current sense for U1
J8 Insert AVDD current sense for U1
J29 DNI External VBST for U1
J6 Insert VBAT pin current sense for U1
J93 Insert SDOUT break for U1
J82 Insert SDIN break for U1
J71 Insert RST break for U1
J60 Insert SBCLK break for U1
J50 Insert FSYNC break for U1
J13 Insert INT break for U1
J91 Insert SDA break for U1
J92 Insert SCL break for U1
J56 Insert (1-2) VBAT source selector for U1
J28 Insert (2-3) VBAT_SNS selector for U1
J39 Insert VBAT source from barrel jack for U1
J46 Insert VBAT source from barrel jack for U1
J34 Insert IOVDD current sense for U2
J35 Insert AVDD current sense for U2
J32 DNI External VBST for U2
J33 Insert VBAT pin current sense for U2
J97 Insert SDOUT break for U2
J96 Insert SDIN break for U2
J100 Insert RST break for U2
J94 Insert SBCLK break for U2
J95 Insert FSYNC break for U2
J14 Insert INT break for U2
J99 Insert SDA break for U2
J98 Insert SCL break for U2
J57 Insert (1-2) VBAT source selector for U2
J52 Insert (2-3) VBAT_SNS selector for U2
J41 Insert VBAT source from barrel jack for U2
J49 Insert VBAT source from barrel jack for U2
J74 DNI EEPROM write protect
J51 DNI EEPROM address selector
J37-4-9 IOVDD_MB Buffer source selector
J38-5-2 IOVDD_MB IOVDD source selector for U1 and U2
J36-11-10 IOVDD_MB AVDD source selector for U1 and U2
J45 Insert (2-3) 1.8V LDO source selector
J19 Insert I2C pull-up connect
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Table 2-1. Default Jumper Settings (continued)
Jumper Setting Description
J20 Insert I2C pull-up connect
J77 DNI FSYNC loopback for APx connection
J78 DNI SBCLK loopback for APx connection
2.4 I2C Target Address Selection
TAS2572EVM has DIP switches S2 and S3 for setting the I2C target address for each channel individually as per
the table provided in the silk screen of the PCB. Make sure both the devices have different target address.
Figure 2-7. DIP Switch S2-S3 for I2C Address Selection
2.5 IOVDD and AVDD Power Supply Options on EVM
TAS2572EVM daughter card provide multiple flexible options for IOVDD_BUFF, IOVDD and AVDD power
supplies. There are options to select between internal or external voltage sources for each of these supplies
individually.
IOVDD_BUFF is 1.8V power supply, which is used for the buffers and voltage translators.
IOVDD is the input/output power supply for TAS2572 device, which can be either 1.2V or 1.8V.
AVDD is the analog power supply for TAS2572 device, which must be 1.8V fixed. If using IOVDD_MB from
AC-MB as 1.2V, make sure to select AVDD source to be either external or +1.8V_LDO.
Figure 6-1shows the default jumper setting for IOVDD_BUFF, IOVDD and AVDD. By default, 1.8V coming from
the AC-MB motherboard (IOVDD_MB) has been selected for IOVDD_BUFF, IOVDD and AVDD with the help of
jumper J9, J5 and J11.
Figure 2-8. Default Jumper Setting for IOVDD_BUFF, IOVDD and AVDD
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There are 1.8V and 3.3V LDOs included in the EVM. These LDOs are powered from the supply connected to
J43, or these can be supplied either from 5 V rail coming from AC-MB, depending on the configuration of jumper
J45.
2.6 VBAT Power Supply for TAS2572 on EVM
By default, the barrel jack connector J43 is used to power VBAT on both TAS2572 channels. Supply 2.4V-5.5V
on this connector.
Alternatively, independent connectors can be used for the external VBAT supply for both the channels –
VBAT1_IN and VBAT2_IN. Jumpers J39 and J46 must be open to disconnect VBAT to VBAT1_IN form J43
input, and similarly J41 and J49 must be open to disconnect VBAT to VBAT2_IN from J43 input.
For channel-1, external VBAT1_IN can be connected between connectors J30 (or J72) and J31 (or J73) as
shown in Figure 7-1.
For channel-2, external VBAT2_IN can be connected between connectors J55 (or J58) and J3 (or J59) as shown
in Figure 7-1.
Channel-1
VBAT1_IN
Channel-2
VBAT2_IN
Channel-1&2
VBAT_IN
Figure 2-9. VBAT Connector for Channel-1 and Channel-2
2.6.1 VBAT 2S EVM Hardware Configuration
This section shows how to set the EVM jumpers to evaluate TAS2572EVM in a 2 S battery application for VBAT,
as depicted in Figure 1-2.
In this case, VBAT pin C1 must still be connected to a power supply range from 3 V up to 5 V, while VBAT_SNS
and the boost inductor can be connected to a higher 2 S supply range from 4.5V up to 9 V.
• VBAT pin C1 connection can be connected to USB-5V by changing J56 position to 2-3 instead of 1-2.
• VBAT_SNS pin C4 connection can be modified using J28, this connection is optional.
• 2 S VBAT supply is directly available at J30 (or J72) and J31 (or J73) for channel-1 and J55 (or J58) and
J3 (or J59) for channel-2. If using J43 to supply 2 S battery voltage, then make sure to change J45 to use
+5V_MB instead.
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2.6.2 VBAT 3 S EVM Hardware Configuration
This section shows how to set the EVM jumpers to evaluate TAS2572EVM in a 3 S battery application for VBAT
as depicted in Figure 1-3.
VBAT pin C1 must still be connected to a power supply range from 3 V up to 5 V. VBAT_SNS cannot be used
so VBAT_SNS must be shorted to GND. The internal boost is not used, so the SW pins are left floating and the
inductor can be removed from the circuit.
3 S battery supply range from VBAT pin C1 level up to 14 V is directly connected to PVDD node, the decoupling
capacitors and GREG capacitor are still required.
• VBAT pin C1 connection can be connected to USB-5V by changing J56 position to 2-3 instead of 1-2.
• VBAT_SNS pin C4 connection must be left as default with J28 shorted across pins 2-3.
• 3 S VBAT supply must be connected to J1 for channel-1 and J12 for channel-2, short the jumpers across J29
and J32.
2.7 Speaker Outputs
Since TAS2572EVM is a dual-mono EVM, each channel has a speaker output connector.
SPK1_P and SPK1_N are the outputs for channel-1 device, whereas SPK2_P and SPK2_N are the outputs
for channel-2. Multiple type of connectors have been provided like horizontal banana barrel connectors, vertical
banana sockets, screw terminal connector and pin headers to be able to connect speaker or dummy load with
fly-wires or male banana connectors. These can also be used to connect into an audio analyzer analog input
cable for performance measurements.
Channel-1 output connectors as shown in Figure 8-1:
• J22 (SPK1_P) and J24 (SPK1_N)
• J21 (SPK1_P) and J26 (SPK1_N)
• J23: Pin-2 (SPK1_P) and Pin-1 (SPK1_N)
• TP-16 (SPK1_P) and TP-18 (SPK1_N)
Channel-2 output connectors as shown in Figure 8-1:
• J47 (SPK2_P) and J54 (SPK2_N)
• J25 (SPK2_P) and J27 (SPK2_N)
• J48: Pin-2 (SPK2_P) and Pin-1 (SPK2_N)
• TP-42 (SPK2_P) and TP-44 (SPK2_N)
Channel-1 Output
SPK1_P & SPK1_N
Channel-2 Output
SPK2_P & SPK2_N
Figure 2-10. Speaker Output Connector for Channel-1 and Channel-2
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