Texas Instruments LMK04826 User manual

User's Guide
SNAU145A–MAY 2013–Revised JUNE 2013
LMK04826/28 User’s Guide
1 Introduction
These evaluation board instructions describes how to set up and operate the LMK04828/6 evaluation
module (EVM). The LMK04828/6 is the industry's highest performance clock conditioner with JEDEC
JESD204B support.
2 Evaluation Board Kit Contents
The evaluation board kit includes. -002 and -003 are currently available:
Table 1. EVM Contents
SV600788 -001 -002 -003
(1) LMK04826B Evaluation
Evaluation Board (1) LMK04828B Evaluation Board Board
USB Communications (1) USB2UWIRE-IFACE (1) USB2ANY
LPT Communicaitions (1) CodeLoader uWire cable -
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x
x
x
x
x
Laptop or PC
Parallel Port or USB
Connector to SPI
4 to 5 V
1
3
4Program with CodeLoader
%HVXUHWRSUHVVµ&WUO- /¶
CLKin1*
Reference clock from
signal generator or other
external source.
122.88 MHz (Default)
2
Power
Reference
LMK0482x
Parallel Port Cable, or
USB2UWIRE-IFACE cable, or
USB2ANY cable
DCLKout2
DCLKout2*
SDCLKout11*
SDCLKout11
DCLKout3* DCLKout3
OSCout OSCout*
CLKin0 CLKin0*
OSCin OSCin*
These SMAs not used by default.
With PCB change, can be used for reference
input for single PLL mode.
SDCLKout1* SDCLKout1 DCLKout0* DCLKout0
DCLKout10*
DCLKout10
Default is
LDO to IC
PLL1 Digital Lock Detect LED
PLL2 Digital
Lock Detect LED
Quick Start www.ti.com
3 Quick Start
Figure 1. Quick Start Diagram
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3.1 Quick Start Description
The LMK04828/6 EVM allows full verification of the device functionality and performance specifications.
To quickly set up and operate the board with basic equipment, refer to the quick start procedure below
and test setup shown in Figure 1.
1. Connect a voltage of 4.5 volts to the Vcc SMA connector or terminal block. Device operates at 3.3 V
using onboard LP3878-ADJ LDO. VCXO operates at 3.3 V using onboard LP5900 LDO.
2. Connect a reference clock to the CLKin1 port from a signal generator or other source. Use 122.88 MHz
for default. Exact frequency and input port (CLKin0/CLKin1) depends on programming.
3. Connect the SPI header to a computer using USB2ANY, USB2UWIRE-IFACE, or parallel port with the
CodeLoader cable.
4. Program the device with CodeLoader. CodeLoader is available for download at:
http://www.ti.com/tool/codeloader.
(a) Select LMK04828B or LMK04826B from “Select Device →Clock Conditioners” Menu.
(b) Select LPT or USB mode from the Port Setup tab as required. If USB is selected, confirm that
USB device being used to communicate with EVM is chosen from list of available USB devices.
(c) Select a default mode from the “Mode” Menu. For the quick start use, “CLKin1 122.88 MHz, OSCin
122.88 MHz”
(d) Ctrl-L must be pressed at least once to load all registers. Alternatively click menu Keyboard
Controls →Load Device.
5. Measurements may be made at an active CLKout port via its SMA connector.
NOTE: New REV C boards dated 02-18-2013 have an updated Pin Configuration which is defaulted.
For older pre-release boards, Pin Configuration must manually be changed and only work with
USB2UWIRE-IFACE or LPT cable.
Figure 2. Pin Configuration for Pre-Release Boards
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1 2 3 5 64 98 10
11 12 13 14
7
15 16
Quick Start www.ti.com
3.1.1 CLKout Tab Description
Figure 3. CLKout Tab Description Diagram
Device Clock Controls
1. CLKoutX_Y_CNTL/CNTH for controlling digital delay.
2. Half step bit (must have a HS mode selected by #6 or #7).
3. Power down digital delay for DCLKoutX.
4. DCLKoutX_DIV, divider for the output channel.
5. Analog delay (if enabled with #6).
6. Select source for output. Can be divider only, divider w/ DCC+HS (duty cycle correction and half step),
bypass, or analog delay w/ Divider (and DCC/HS if selected by #7).
7. Select DCC/HS or not when using analog delay mode.
8. Powerdown the entire CLKoutX_Y block. Both outputs will be off.
Device Clock/SYSREF Controls
9. Select output type for each output.
10. SYNC_POL bit, will allow SYNC when in default configuration (SYNC_MODE / SYSREF_MUX setup
for normal SYNC).
SYSREF Controls
11. SYSREF clock digital delay.
12. SYSREF clock half step
13. SYSREF analog delay (if enabled by #14)
14. Enable analog delay
15. Select Device Clock or SYSREF clock for output to SDCLKoutY clock.
16. Calculated output frequency.
3.1.2 CodeLoader Tips
• On Bits/Pins tab right-clicking any register name in the Bits/Pins tab will display a Help prompt with the
register address, data bit location/length, and a brief register description.
• On PLL tabs clicking Show Bits will show register info.
• On other tabs, pressing ~ with a control focused will show help.
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3.2 SYSREF Quick Start
The LMK0482x EVK allows for verification of the LMK0482x’s implementation of JESD 204B SYSREF
functionality. To quickly setup and operate the SYSREF functions refer to the following procedures.
3.2.1 Continuous SYSREF
1. Set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout)
2. Set SDCLKoutY_MUX = 1 (Set to “SR” for desired SDCLKout)
3. Set SYSREF_PD and SYSREF_DDLY_PD = 0
4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout)
5. Perform a SYNC event (toggle SYNC_POL on/off/on)
6. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1
7. Set SYSREF_MUX = 3 (SYSREF Continuous)
8. Ensure SYSREF_CLR = 0 (SYSREF tab, location: right side, below clock output pic)
In Figure 2 and Figure 4 the Blue trace is DCLKout6 at 245.76 MHz and the Green trace is SDCLKout7
(SYSREF) at 24.475 MHz. Figure 5 shows the configuration of the LMK0482xB outputs.
Figure 4. Continuous SYSREF Output
3.2.2 Pulsed SYSREF
1. Set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout)
2. Set SDCLKoutY_MUX = 1 (Set to “SR” for desired SDCLKout)
3. Set SYSREF_PD and SYSREF_DDLY_PD = 0
4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout)
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Quick Start www.ti.com
5. Perform a SYNC event (toggle SYNC_POL on/off/on)
6. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1
7. Set SYSREF_MUX = 2 (SYSREF Pulses)
8. Set SYSREF_PULSE_CNT = 1, 2, 4, or 8 as desired
9. Generate a SYNC event (i.e. toggle SYNC_POL on/off/on)
10. Ensure SYSREF_CLR = 0 (SYSREF tab, location: right side, below clock output pic)
Figure 5. Pulsed SYSREF Output
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Figure 6. Clock Outputs Tab Setup for SYSREF Output on SDCLKout7
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PLL Loop Filters and Loop Parameters www.ti.com
4 PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a
“dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to
minimize the impact of the reference clock phase noise. The reference clock consequently serves only as
a frequency reference rather than a phase reference.
The loop filters on the LMK048xx evaluation board are setup using the approach above. The loop filter for
PLL1 has been configured for a narrow loop bandwidth (> 100 kHz). The specific loop bandwidth values
depend on the phase noise performance of the oscillator mounted on the board. The following tables
(Table 2 and Table 3) contain the parameters for PLL1 and PLL2 for each oscillator option.
TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See:
http://www.ti.com/tool/clockdesigntool
4.1 PLL1 Loop Filter
Table 2. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO(1)
122.88 MHz VCXO PLL
Phase Margin 50˚Kφ(Charge Pump) 450 uA
Loop Bandwidth 14 Hz Phase Detector Freq 1.024 MHz
VCO Gain 2.5 kHz/V
Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz
(To PLL 2)
Loop Filter Components C1_A1 = 100 nF C2_A1 = 680 nF R2_A1 = 39 kΩ
(1) Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N will change the loop bandwidth.
4.2 PLL2 Loop Filter
Table 3. Integrated VCO PLL(1)
LMK04826 LMK04828
VCO0 VCO1 VCO0 VCO1
C1_A2 0.047 nF
C2_A2 3.9 nF
C3 (internal) 0.01 nF
C4 (internal) 0.01 nF
R2_A2 0.62 kΩ
R3 (internal) 0.2 kΩ
R4 (internal) 0.2 kΩ
Charge Pump Current, Kφ3.2 mA
Phase Detector Frequency 122.88 MHz
Frequency 1966.08 2457.6 2457.6 2949.12 MHz
Kvco 15.3 8.9 21.9 17.4 MHz/V
N16 20 20 24
Phase Margin 73 64 73 70 degrees
Loop Bandwidth 303 151 344 233 kHz
(1) PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N will change the loop
bandwidth.
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www.ti.com Default CodeLoader Modes for the LMK0482x
5 Default CodeLoader Modes for the LMK0482x
CodeLoader saves the state of the selected LMK0482x device when exiting the software. To ensure a
common starting point, the following modes listed in Table 4 may be restored by clicking “Mode” and
selecting the appropriate device configuration.
Table 4. Default CodeLoader Modes for the LMK0482x
Default CodeLoader Mode Device Mode CLKin Frequency OSCin Frequency
CLKin1 122.88 MHz, OSCin Dual PLL, Internal VCO 122.88 MHz 122.88 MHz
122.88 MHz
Figure 7. Selecting a Default Mode for the LMK04828 Device
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Using CodeLoader to Program the LMK04828 www.ti.com
6 Using CodeLoader to Program the LMK04828
The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements
with the LMK04828B device as an example. For more information on CodeLoader refer to CodeLoader 4
instructions located at http://www.ti.com/tool/codeloader
Before proceeding, be sure to follow the Section 3 section above to ensure proper connections. To
program the LMK04826B the procedure would be the same but select the LMK04826B as the device.
6.1 Start CodeLoader Application
Click “Start” →“Programs” →“CodeLoader 4” →“CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
6.2 Select Device
Click “Select Device” →“Clock Conditioners” →“LMK04828B”
Once started CodeLoader 4 will load the last used device. To load a new device click “Select Device” from
the menu bar, then select the subgroup and finally device to load. For this example, the LMK04828B is
chosen. Selecting the device does cause the device to be programmed.
6.3 Program/Load Device
Assuming the Port Setup settings are correct, press the “Ctrl+L” shortcut or click “Keyboard Controls” →
“Load Device” from the menu to program the device to the current state of the newly loaded LMK04828
file.
Figure 8. Loading the Device
Once the device has been initially loaded, CodeLoader will automatically program changed registers so it
is not necessary to re-load the device upon subsequent changes in the device configuration. It is possible
to disable this functionality by ensuring there is no checkmark by the “Options” →“AutoReload with
Changes.”
Because a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting CodeLoader,
restoring a mode, or restoring a saved setup using the File menu.
See CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader/ for more information on Port
Setup. This contains information on troubleshooting communications.
6.4 Restoring a Default Mode
Click “Mode” →“CLKin1 122.88 MHz, OSCin 122.88 MHz”; then press Ctrl+L.
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