Texas Instruments LMK04826 User manual

User's Guide
SNAU145A–MAY 2013–Revised JUNE 2013
LMK04826/28 User’s Guide
1 Introduction
These evaluation board instructions describes how to set up and operate the LMK04828/6 evaluation
module (EVM). The LMK04828/6 is the industry's highest performance clock conditioner with JEDEC
JESD204B support.
2 Evaluation Board Kit Contents
The evaluation board kit includes. -002 and -003 are currently available:
Table 1. EVM Contents
SV600788 -001 -002 -003
(1) LMK04826B Evaluation
Evaluation Board (1) LMK04828B Evaluation Board Board
USB Communications (1) USB2UWIRE-IFACE (1) USB2ANY
LPT Communicaitions (1) CodeLoader uWire cable -
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x
x
x
x
x
Laptop or PC
Parallel Port or USB
Connector to SPI
4 to 5 V
1
3
4Program with CodeLoader
%HVXUHWRSUHVVµ&WUO- /¶
CLKin1*
Reference clock from
signal generator or other
external source.
122.88 MHz (Default)
2
Power
Reference
LMK0482x
Parallel Port Cable, or
USB2UWIRE-IFACE cable, or
USB2ANY cable
DCLKout2
DCLKout2*
SDCLKout11*
SDCLKout11
DCLKout3* DCLKout3
OSCout OSCout*
CLKin0 CLKin0*
OSCin OSCin*
These SMAs not used by default.
With PCB change, can be used for reference
input for single PLL mode.
SDCLKout1* SDCLKout1 DCLKout0* DCLKout0
DCLKout10*
DCLKout10
Default is
LDO to IC
PLL1 Digital Lock Detect LED
PLL2 Digital
Lock Detect LED
Quick Start www.ti.com
3 Quick Start
Figure 1. Quick Start Diagram
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www.ti.com Quick Start
3.1 Quick Start Description
The LMK04828/6 EVM allows full verification of the device functionality and performance specifications.
To quickly set up and operate the board with basic equipment, refer to the quick start procedure below
and test setup shown in Figure 1.
1. Connect a voltage of 4.5 volts to the Vcc SMA connector or terminal block. Device operates at 3.3 V
using onboard LP3878-ADJ LDO. VCXO operates at 3.3 V using onboard LP5900 LDO.
2. Connect a reference clock to the CLKin1 port from a signal generator or other source. Use 122.88 MHz
for default. Exact frequency and input port (CLKin0/CLKin1) depends on programming.
3. Connect the SPI header to a computer using USB2ANY, USB2UWIRE-IFACE, or parallel port with the
CodeLoader cable.
4. Program the device with CodeLoader. CodeLoader is available for download at:
http://www.ti.com/tool/codeloader.
(a) Select LMK04828B or LMK04826B from “Select Device →Clock Conditioners” Menu.
(b) Select LPT or USB mode from the Port Setup tab as required. If USB is selected, confirm that
USB device being used to communicate with EVM is chosen from list of available USB devices.
(c) Select a default mode from the “Mode” Menu. For the quick start use, “CLKin1 122.88 MHz, OSCin
122.88 MHz”
(d) Ctrl-L must be pressed at least once to load all registers. Alternatively click menu Keyboard
Controls →Load Device.
5. Measurements may be made at an active CLKout port via its SMA connector.
NOTE: New REV C boards dated 02-18-2013 have an updated Pin Configuration which is defaulted.
For older pre-release boards, Pin Configuration must manually be changed and only work with
USB2UWIRE-IFACE or LPT cable.
Figure 2. Pin Configuration for Pre-Release Boards
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1 2 3 5 64 98 10
11 12 13 14
7
15 16
Quick Start www.ti.com
3.1.1 CLKout Tab Description
Figure 3. CLKout Tab Description Diagram
Device Clock Controls
1. CLKoutX_Y_CNTL/CNTH for controlling digital delay.
2. Half step bit (must have a HS mode selected by #6 or #7).
3. Power down digital delay for DCLKoutX.
4. DCLKoutX_DIV, divider for the output channel.
5. Analog delay (if enabled with #6).
6. Select source for output. Can be divider only, divider w/ DCC+HS (duty cycle correction and half step),
bypass, or analog delay w/ Divider (and DCC/HS if selected by #7).
7. Select DCC/HS or not when using analog delay mode.
8. Powerdown the entire CLKoutX_Y block. Both outputs will be off.
Device Clock/SYSREF Controls
9. Select output type for each output.
10. SYNC_POL bit, will allow SYNC when in default configuration (SYNC_MODE / SYSREF_MUX setup
for normal SYNC).
SYSREF Controls
11. SYSREF clock digital delay.
12. SYSREF clock half step
13. SYSREF analog delay (if enabled by #14)
14. Enable analog delay
15. Select Device Clock or SYSREF clock for output to SDCLKoutY clock.
16. Calculated output frequency.
3.1.2 CodeLoader Tips
• On Bits/Pins tab right-clicking any register name in the Bits/Pins tab will display a Help prompt with the
register address, data bit location/length, and a brief register description.
• On PLL tabs clicking Show Bits will show register info.
• On other tabs, pressing ~ with a control focused will show help.
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www.ti.com Quick Start
3.2 SYSREF Quick Start
The LMK0482x EVK allows for verification of the LMK0482x’s implementation of JESD 204B SYSREF
functionality. To quickly setup and operate the SYSREF functions refer to the following procedures.
3.2.1 Continuous SYSREF
1. Set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout)
2. Set SDCLKoutY_MUX = 1 (Set to “SR” for desired SDCLKout)
3. Set SYSREF_PD and SYSREF_DDLY_PD = 0
4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout)
5. Perform a SYNC event (toggle SYNC_POL on/off/on)
6. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1
7. Set SYSREF_MUX = 3 (SYSREF Continuous)
8. Ensure SYSREF_CLR = 0 (SYSREF tab, location: right side, below clock output pic)
In Figure 2 and Figure 4 the Blue trace is DCLKout6 at 245.76 MHz and the Green trace is SDCLKout7
(SYSREF) at 24.475 MHz. Figure 5 shows the configuration of the LMK0482xB outputs.
Figure 4. Continuous SYSREF Output
3.2.2 Pulsed SYSREF
1. Set SDCLKoutY_PD = 0 (where Y is the desired SDCLKout)
2. Set SDCLKoutY_MUX = 1 (Set to “SR” for desired SDCLKout)
3. Set SYSREF_PD and SYSREF_DDLY_PD = 0
4. Set SYNC_DISX and SYNC_DISSYSREF = 0 (where X is the desired DCLKout)
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Quick Start www.ti.com
5. Perform a SYNC event (toggle SYNC_POL on/off/on)
6. Set SYNC_DISX = 1 (for desired DCLKout’s) and SYNC_DISSYSREF = 1
7. Set SYSREF_MUX = 2 (SYSREF Pulses)
8. Set SYSREF_PULSE_CNT = 1, 2, 4, or 8 as desired
9. Generate a SYNC event (i.e. toggle SYNC_POL on/off/on)
10. Ensure SYSREF_CLR = 0 (SYSREF tab, location: right side, below clock output pic)
Figure 5. Pulsed SYSREF Output
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Figure 6. Clock Outputs Tab Setup for SYSREF Output on SDCLKout7
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PLL Loop Filters and Loop Parameters www.ti.com
4 PLL Loop Filters and Loop Parameters
In jitter cleaning applications that use a cascaded or dual PLL architecture, the first PLL’s purpose is to
substitute the phase noise of a low-noise oscillator (VCXO or crystal resonator) for the phase noise of a
“dirty” reference clock. The first PLL is typically configured with a narrow loop bandwidth in order to
minimize the impact of the reference clock phase noise. The reference clock consequently serves only as
a frequency reference rather than a phase reference.
The loop filters on the LMK048xx evaluation board are setup using the approach above. The loop filter for
PLL1 has been configured for a narrow loop bandwidth (> 100 kHz). The specific loop bandwidth values
depend on the phase noise performance of the oscillator mounted on the board. The following tables
(Table 2 and Table 3) contain the parameters for PLL1 and PLL2 for each oscillator option.
TI’s Clock Design Tool can be used to optimize PLL phase noise/jitter for given specifications. See:
http://www.ti.com/tool/clockdesigntool
4.1 PLL1 Loop Filter
Table 2. PLL1 Loop Filter Parameters for Crystek 122.88 MHz VCXO(1)
122.88 MHz VCXO PLL
Phase Margin 50˚Kφ(Charge Pump) 450 uA
Loop Bandwidth 14 Hz Phase Detector Freq 1.024 MHz
VCO Gain 2.5 kHz/V
Reference Clock Frequency 122.88 MHz Output Frequency 122.88 MHz
(To PLL 2)
Loop Filter Components C1_A1 = 100 nF C2_A1 = 680 nF R2_A1 = 39 kΩ
(1) Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N will change the loop bandwidth.
4.2 PLL2 Loop Filter
Table 3. Integrated VCO PLL(1)
LMK04826 LMK04828
VCO0 VCO1 VCO0 VCO1
C1_A2 0.047 nF
C2_A2 3.9 nF
C3 (internal) 0.01 nF
C4 (internal) 0.01 nF
R2_A2 0.62 kΩ
R3 (internal) 0.2 kΩ
R4 (internal) 0.2 kΩ
Charge Pump Current, Kφ3.2 mA
Phase Detector Frequency 122.88 MHz
Frequency 1966.08 2457.6 2457.6 2949.12 MHz
Kvco 15.3 8.9 21.9 17.4 MHz/V
N16 20 20 24
Phase Margin 73 64 73 70 degrees
Loop Bandwidth 303 151 344 233 kHz
(1) PLL Loop Bandwidth is a function of Kφ, Kvco, N as well as loop components. Changing Kφand N will change the loop
bandwidth.
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www.ti.com Default CodeLoader Modes for the LMK0482x
5 Default CodeLoader Modes for the LMK0482x
CodeLoader saves the state of the selected LMK0482x device when exiting the software. To ensure a
common starting point, the following modes listed in Table 4 may be restored by clicking “Mode” and
selecting the appropriate device configuration.
Table 4. Default CodeLoader Modes for the LMK0482x
Default CodeLoader Mode Device Mode CLKin Frequency OSCin Frequency
CLKin1 122.88 MHz, OSCin Dual PLL, Internal VCO 122.88 MHz 122.88 MHz
122.88 MHz
Figure 7. Selecting a Default Mode for the LMK04828 Device
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Using CodeLoader to Program the LMK04828 www.ti.com
6 Using CodeLoader to Program the LMK04828
The purpose of this section is to walk the user through using CodeLoader 4 to make some measurements
with the LMK04828B device as an example. For more information on CodeLoader refer to CodeLoader 4
instructions located at http://www.ti.com/tool/codeloader
Before proceeding, be sure to follow the Section 3 section above to ensure proper connections. To
program the LMK04826B the procedure would be the same but select the LMK04826B as the device.
6.1 Start CodeLoader Application
Click “Start” →“Programs” →“CodeLoader 4” →“CodeLoader 4”
The CodeLoader 4 program is installed by default to the CodeLoader 4 application group.
6.2 Select Device
Click “Select Device” →“Clock Conditioners” →“LMK04828B”
Once started CodeLoader 4 will load the last used device. To load a new device click “Select Device” from
the menu bar, then select the subgroup and finally device to load. For this example, the LMK04828B is
chosen. Selecting the device does cause the device to be programmed.
6.3 Program/Load Device
Assuming the Port Setup settings are correct, press the “Ctrl+L” shortcut or click “Keyboard Controls” →
“Load Device” from the menu to program the device to the current state of the newly loaded LMK04828
file.
Figure 8. Loading the Device
Once the device has been initially loaded, CodeLoader will automatically program changed registers so it
is not necessary to re-load the device upon subsequent changes in the device configuration. It is possible
to disable this functionality by ensuring there is no checkmark by the “Options” →“AutoReload with
Changes.”
Because a default mode will be restored in the next step, this step isn’t really needed but included to
emphasize the importance of pressing “Ctrl+L” to load the device at least once after starting CodeLoader,
restoring a mode, or restoring a saved setup using the File menu.
See CodeLoader 4 instructions located at http://www.ti.com/tool/codeloader/ for more information on Port
Setup. This contains information on troubleshooting communications.
6.4 Restoring a Default Mode
Click “Mode” →“CLKin1 122.88 MHz, OSCin 122.88 MHz”; then press Ctrl+L.
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www.ti.com Using CodeLoader to Program the LMK04828
Figure 9. Setting the Default Mode for LMK04828
For the purpose of this walkthrough, a default mode will be loaded to ensure a common starting point.
This is important because when CodeLoader is closed, it remembers the last settings used for a particular
device. Again, remember to press Ctrl+L as the first step after loading a default mode.
6.5 Visual Confirmation of Frequency Lock
After a default mode is restored and loaded, LED D4, and D5 should illuminate when PLL1 and PLL2 are
locked to the reference clock applied to CLKin1. This assumes PLL1_LD_MUX = PLL1_DLD,
PLL2_LD_MUX = PLL2_DLD and PLLX_LD_TYPE = Output (Push-Pull).
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Evaluation Board Inputs and Outputs www.ti.com
6.6 Enable Clock Outputs
While the LMK0482x offers programmable clock output buffer formats, the evaluation board is shipped
with preconfigured output terminations to match the default buffer type for each output.
To measure Phase noise at one of the clock outputs, for example DCLKout0:
1. 1. Click on the Distribution tab,
2. 2. Uncheck “Powerdown” in the Clock output box to enable the channel,
3. 3. Set the following settings as needed:
(a) Digital Delay value
(b) Clock Divider value
(c) Analog delay select and Analog Delay value (if not “Analog Delay and Divider” is selected in the
Analog Delay Select box,
Figure 10. Setting Digital Delay, Clock Divider, Analog Delay and Output Format
4. Depending on the configured output type, the clock output SMAs can be interfaced to a test instrument
with a single-ended 50-ohm input as follows.
(a) For LVDS:
(i) A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-to-
single-ended conversion.
(b) For LVPECL:
(i) A balun can be used, or
(ii) One side of the LVPECL signal can be terminated with a 50-ohm load and the other side can
be run single-ended to the instrument.
(c) For HSDS:
(i) A balun (like ADT2-1T or high quality Prodyn BIB-100G) is recommended for differential-to-
single-ended conversion.
5. The phase noise may be measured with a spectrum analyzer or signal source analyzer.
TI’s Clock Design Tool can be used to calculate divider values to achieve desired clock output
frequencies. See: http://www.ti.com/tool/clockdesigntool
7 Evaluation Board Inputs and Outputs
The following table (Table 5) contains descriptions of the inputs and outputs for the evaluation board.
Unless otherwise noted, the connectors described can be assumed to be populated by default.
Additionally, some applicable CodeLoader programming controls are noted for convenience.
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www.ti.com Evaluation Board Inputs and Outputs
Table 5. Description of Evaluation Board Inputs and Outputs
Connector Name Signal Type, Description
Input/Output
Populated: Analog, Clock outputs with programmable output buffers.
DCLKout0, Output The output terminations by default on the evaluation board are shown below:
DCLKout0*,
SDCLKout1, Clock Output Pair Default Board Termination
SDCLKout1*, DCLKout0 240 Ω
DCLKout2,
DCLKout2*, SDCLKout1 240 Ω
SDCLKout3, DCLKout2 240Ω
SDCLKout3*,
DCLKout10, SDCLKout3 240 Ω
DCLKout10* DCLKout4 HSDS / LVDS
SDCLKout11,
SDCLKout11* SDCLKout5 HSDS / LVDS
DCLKout6 HSDS / LVDS
SDCLKout7 HSDS / LVDS
DCLKout8 HSDS / LVDS
SDCLKout9 HSDS / LVDS
DCLKout10 HSDS / LVDS
SDCLKout11 HSDS / LVDS
DCLKout12 HSDS / LVDS
SDCLKout13 HSDS / LVDS
Each CLKout pair has a programmable LVDS, LVPECL, or HSDS buffer. The
output buffer type can be selected in CodeLoader in the Clock Outputs tab via the
CLKoutX_TYPE control.
All clock outputs are AC-coupled to allow safe testing with RF test equipment.
All LVPECL clock outputs are terminated using 240 Ωemitter-resistors.
If an output pair is programmed to LVCMOS, each output can be independently
configured (normal, inverted, or off/tri-state).
Populated: Analog, Buffered outputs of OSCin port.
OSCout, OSCout* Output The output terminations on the evaluation board are shown below.:
OSC output pair Default Board Termination
OSCout LVPECL
OSCout has a programmable LVDS, LVPECL, or LVCMOS output buffer. The
OSCout buffer type can be selected in CodeLoader on the Distribution tab via the
OSCout_FMT control.
OSCout is AC-coupled to allow safe testing with RF test equipment.
The OSCout output is terminated using 240 Ωemitter-resistors.
If OSCout is programmed as LVCMOS, each output can be independently
configured (normal, inverted, inverted, and off/tri-state).
Best performance/EMI reduction is achieved by using a complementary output
mode like Norm/Inv. It is NOT recommended to use Norm/Norm or Inv/Inv mode.
Vcc Power, Main power supply input for the evaluation board.
Input The LMK0482x contains internal voltage regulators for the VCO, PLL and other
internal blocks. The clock outputs do not have an internal regulator, so a clean
power supply with sufficient output current capability is required for optimal
performance.
On-board LDO regulators and 0 Ωresistor options provide flexibility to supply and
route power to various devices. See the schematics in section Section 11 for more
details.
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Evaluation Board Inputs and Outputs www.ti.com
Table 5. Description of Evaluation Board Inputs and Outputs (continued)
Connector Name Signal Type, Description
Input/Output
Populated: Power, Alternative power supply input for the evaluation board using two unshielded wires
J1 Input (Vcc and GND).
Apply power to either Vcc SMA or J1, but not both.
VccVCXO/Aux Power, Optional Vcc input to power the VCXO circuit if separated voltage rails are needed.
Input The VccVCXO/Aux input can power these circuits directly or supply the on-board
LDO regulators. 0 Ωresistor options provide flexibility to route power.
Populated: Analog, Reference Clock Inputs for PLL1 (CLKin0, 1). CLKin1 can alternatively be used as
CLKin0, CLKin0*, Input an External Feedback Clock Input (FBCLKin) in 0-delay mode or an RF Input (Fin)
CLKin1* in External VCO mode.
Reference Clock Inputs for PLL1 (CLKin0, 1)
FBCLKin/CLKin1* is configured by default for a single-ended reference clock input
from a 50-ohm source.The non-driven input pin (FBCLKin/CLKin1) is connected to
GND with a 0.1 uF. CLKin0/CLKin0* is configured by default for a differential
reference clock input from a 50-ohm source.
Not Populated: CLKin1* is the default reference clock input selected in CodeLoader. The clock
CLKin1 input selection mode can be programmed on the Bits/Pins tab via the Clock Inputs
control.
External Feedback Input (FBCLKin) for 0-Delay
CLKin1 is shared for use with FBCLKin as an external feedback clock input to PLL1
for 0-delay mode. See the LMK04820 family datasheet (literature number
SNAS605) for more details on using 0-delay mode with the evaluation board and
the evaluation board software.
Populated: Analog, Feedback VCXO clock input to PLL1 and Reference clock input to PLL2.
OSCin, OSCin* Input The single-ended output of the onboard VCXO (U4) drives the OSCin* input of the
device and the OSCin input of the device is connected to GND with 0.1 uF.
A VCXO add-on board may be optionally attached via these SMA connectors with
minor modification to the components going to the OSCin/OSCin* pins of device.
This is useful if the VCXO footprint does not accommodate the desired VCXO
device or if the user desires to use the LMK0482xB in single loop mode.
A single-ended or differential signal may be used to drive the OSCin/OSCin* pins
and must be AC coupled. If operated in single-ended mode, the unused input must
be connected to GND with 0.1 uF.
Refer to the LMK04820 family datasheet section “Electrical Characteristics” for
PLL2 Reference Input (OSCin) specifications (literature number SNAS605).
Test point: Analog, Tuning voltage output from the loop filter for PLL1.
VTUNE1_TP Input If a VCXO add-on board is used, this tuning voltage can be connected to the
voltage control pin of the external VCXO when this SMA connector is installed and
connected through R72 by the user.
Test point: Analog, Tuning voltage output from the loop filter for PLL2.
VTUNE2_TP Input
Test points: CMOS, 10-pin header for SPI programming interface and programmable logic I/O pins for
SDIO Input/Output the LMK0482x.
SCK
CS*
Populated: 10-pin header for SPI programming interface and programmable logic I/O pins for
SPI the LMK0482x.
The programmable logic I/O signals accessible through this header include:
RESET, SYNC, Status_LD1, Status_LD2, CLKin_SEL0, and CLKin_SEL1. These
logic I/O signals also have dedicated SMAs and test points.
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www.ti.com Evaluation Board Inputs and Outputs
Table 5. Description of Evaluation Board Inputs and Outputs (continued)
Connector Name Signal Type, Description
Input/Output
Test point: CMOS, Programmable status output pin. By default, set to output the digital lock detect
Status_LD1_TP Input/Output status signal for PLL1.
In the default CodeLoader modes, LED D5 will illuminate green when PLL1 lock is
detected by the LMK0482x (output is high) and turn off when lock is lost (output is
low).
Status_LD The status output signal for the Status_LD1 pin can be selected on the Bits/Pins
tab via the PLL1_LD_MUX control.
Test point: CMOS, Programmable status output pin. By default, set to output the digital lock detect
Status_LD2_TP Input/Output status signal for PLL2.
In the default CodeLoader modes, LED D4 will illuminate green when PLL1 lock is
detected by the LMK0482x (output is high) and turn off when lock is lost (output is
low).
Status_LD2 The status output signal for the Status_LD1 pin can be selected on the Bits/Pins
tab via the PLL2_LD_MUX control.
Test points: CMOS, Programmable status I/O pins. By default, set as input pins for controlling input
CLKin0_SEL_TP Input/Output clock switching of CLKin0 and CLKin1.
CLKin1_SEL_TP These inputs will not be functional because CLKin_SEL_MODE is set to 0 (CLKin0
Manual) by default in the Bits/Pins tab in CodeLoader. To enable input clock
switching, CLKin_SEL_MODE must be 3 and Status_CLKinX_TYPE must be 0 to 3
(pin enabled as an input).
Input Clock Switching – Pin Select Mode
When CLKin_SEL_MODE is 3, the Status_CLKinX pins select which clock input is
active as follows:
Status_CLKin1 Status_CLKin0 Active Clock
0 0 CLKin0
0 1 CLKin1
1 0 CLKin2
1 1 Holdover
Test point: CMOS, Programmable status I/O pin. By default, set as an input pin for synchronize the
SYNC_TP Input/Output clock outputs with a fixed and known phase relationship between each clock output
selected for SYNC. A SYNC event also causes the digital delay values to take
effect.
SYNC/SYSREF_REQ pin forces the SYSREF_MUX into SYSREF Continuous
mode (0x03) when SYSREF_REQ_EN = 1.
Populated: SYNC/SYSREF_REQ pin can hold outputs in a low state, depending on system
SYNC configuration. SYNC_POL adjusts for active low or active high control.
A SYNC event can also be programmed by toggling the SYNC_POL_INV bit in the
Bits/Pins tab in CodeLoader.
Test point: CMOS, Programmable status I/O pin.
RESET_TP Input/Output
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Recommended Test Equipment www.ti.com
8 Recommended Test Equipment
Power Supply
The Power Supply should be a low noise power supply, particularly when the devices on the board are
being directly powered (onboard LDO regulators bypassed).
Phase Noise / Spectrum Analyzer
To measure phase noise and RMS jitter, an Agilent E5052 Signal Source Analyzer is recommended. An
Agilent E4445A PSA Spectrum Analyzer with the Phase Noise option is also usable although the
architecture of the E5052 is superior for phase noise measurements. At frequencies less than 100 MHz
the local oscillator noise of the E4445A is too high and measurements will reflect the E4445A’s internal
local oscillator performance, not the device under test.
Oscilloscope
To measure the output clocks for AC performance, such as rise time or fall time, propagation delay, or
skew, it is suggested to use a real-time oscilloscope with at least 1 GHz analog input bandwidth (2.5+
GHz recommended) with 50 ohm inputs and 10+ Gsps sample rate. To evaluate clock synchronization or
phase alignment between multiple clock outputs, it’s recommended to use phase-matched, 50-ohm cables
to minimize external sources of skew or other errors/distortion that may be introduced if using oscilloscope
probes.
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www.ti.com Appendix A: CodeLoader Usage
9 Appendix A: CodeLoader Usage
Code Loader is used to program the evaluation board with either an LPT port using the included
CodeLoader cable or with a USB port using the included USB2UWIRE-IFACE.
9.1 Port Setup Tab
Figure 11. Port Setup Tab
On the Port Setup tab, the user may select the type of communication port (USB or Parallel) that will be
used to program the device on the evaluation board. If parallel port is selected, the user should ensure
that the correct port address is entered. If USB mode is selected, identify the correct target device by
clicking the Identify button - the selected USB2ANY will blink the onboard LED 5 times.
The Pin Configuration field is hardware dependent and normally does not need to be changed by the user
(except for pre-release boards). For information on this configuration, refer to Figure 2.
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Appendix A: CodeLoader Usage www.ti.com
9.2 PLL1 Tab
Figure 12. PLL1 Tab
The PLL1 tab allows the user to change the following parameters in Table 6.
Table 6. Registers Controls and Descriptions in PLL1 Tab
Control Name Register Name Description
Reference Oscillator Frequency (MHz) n/a CLKin frequency of the selected reference
clock.
Phase Detector Frequency (MHz) n/a PLL1 Phase Detector Frequency (PDF).
This value is calculated as:
PLL1 PDF = CLKin Frequency / (PLL1_R)
VCO Frequency (MHz) n/a The VCO Frequency should be the OSCin
frequency, except when operating in Dual
PLL with 0-delay feedback. This value is
calculated as:
VCO Freq (OSCin freq) = PLL1 PDF *
PLL1_N.
R Counter PLL1_R PLL1 R Counter value (1 to 16383).
N Counter PLL1_N PLL1 N Counter value (1 to 16383).
Phase Detector Polarity PLL1_CP_POL PLL1 Phase Detector Polarity.
Click on the polarity sign to toggle polarity
“+” or “–”.
Charge Pump Gain PLL1_CP_GAIN PLL1 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (50,150, 250, 1550 uA).
Charge Pump State PLL1_CP_TRI PLL1 Charge Pump State.
Click to toggle between Active and Tri-
State.
18 LMK04826/28 User’s Guide SNAU145A–MAY 2013–Revised JUNE 2013
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9.3 PLL2 Tab
Figure 13. PLL2 Tab
The PLL2 tab allows the user to change the following parameters in Table 7.
Table 7. Registers Controls and Descriptions in PLL2 Tab(1)
Control Name Register Name Description
Reference Oscillator Frequency (MHz) OSCin_FREQ OSCin frequency from the External VCXO
or Crystal.
Phase Detector Frequency (MHz) n/a PLL2 Phase Detector Frequency (PDF).
This value is calculated as:
PLL2 PDF = OSCin Frequency
*(2EN_PLL2_REF_2X) / PLL2_R.
VCO Frequency (MHz) n/a Internal VCO Frequency should be within
the allowable range of the LMK048xxB
device.
This value is calculated as:
VCO Frequency = PLL2 PDF * (PLL2_N *
PLL2_P * VCO divider value).
Doubler EN_PLL2_REF_2X PLL2 Doubler.
0 = Bypass Doubler
1 = Enable Doubler
R Counter PLL2_R PLL2 R Counter value (1 to 4095).
N Counter PLL2_N PLL2 N Counter value (1 to 262143).
PLL Prescaler PLL2_P PLL2 N Prescaler value (2 to 8).
Phase Detector Polarity PLL2_CP_POL PLL2 Phase Detector Polarity.
Click on the polarity sign to toggle polarity
“+” or “–”.
Charge Pump Gain PLL2_CP_GAIN PLL2 Charge Pump Gain.
Left-click/right-click to increase/decrease
charge pump gain (100, 400, 1600, 3200
uA).
Charge Pump State PLL2_CP_TRI PLL2 Charge Pump State.
Click to toggle between Active and Tri-
State.
(1) Changes made on this tab will be reflected in the Clock Outputs tab. The VCO Frequency should conform to the specified
internal VCO frequency range.
19
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9.4 Distribution Tab
Figure 14. Distribution Tab
The Distribution tab allows the user to control the output channel blocks.
Note that the total PLL2 N divider value is the product of the VCO Divider value and the PLL N Prescaler
and N Counter values (shown in the PLL2 tab), and is given by:
PLL2 N Total = PLL2 N Prescaler * PLL2 N Counter (1)
Clicking on the cyan-colored PLL2 block that contains R, PDF and N values will bring the PLL2 tab into
focus where these values may be modified, if needed.
Clicking on the values in the box containing the Internal Loop Filter component (R3, C3, R4, C4) allow one
to step through the possible values. Left click to increase the component value, and right click to decrease
the value. These values can also be changed in the Bits/Pins tab.
20 LMK04826/28 User’s Guide SNAU145A–MAY 2013–Revised JUNE 2013
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