Texas Instruments ADS8168EVM-PDK User manual

1
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
User's Guide
SBAU291–November 2017
ADS8168EVM-PDK
The ADS8168 evaluation module (EVM) performance demonstration kit (PDK) is a platform for evaluating
the performance of the ADS8168 successive approximation register analog-to-digital converter (SAR
ADC). The ADS8168EVM-PDK includes the ADS8168EVM board, the PHI controller board, and
accompanying computer software that enables the user to communicate with the ADC over a universal
serial bus (USB), capture data, and perform data analysis. This user's guide includes complete circuit
descriptions, schematic diagrams, and a bill of materials.
Figure 1. ADS8268EVM-PDK
The following related documents are available through the Texas Instruments web site at www.ti.com.
Related Documentation
Device Literature Number
ADS8168 SBAS817
REF5050 SBOS410
OPA320 SBOS513

www.ti.com
2SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
Contents
1 Overview...................................................................................................................... 4
1.1 ADS8168EVM-PDK Features..................................................................................... 4
1.2 ADS8168EVM Features ........................................................................................... 4
1.3 EVM Main Sections (Circuit Blocks) ............................................................................. 4
2 EVM Analog Interface....................................................................................................... 6
2.1 ADS8168 Internal Reference and EVM Onboard Reference ................................................. 7
3 Digital Interfaces ............................................................................................................. 8
3.1 ADS8168 Digital Interface ......................................................................................... 8
4 Power Supplies .............................................................................................................. 9
5 ADS8168EVM_PDK Initial Setup ........................................................................................ 10
5.1 Default Jumper Settings.......................................................................................... 10
5.2 EVM Graphical User Interface (GUI) Software Installation .................................................. 11
6 ADS8168EVM-PDK Operation ........................................................................................... 15
6.1 EVM GUI Global Settings for ADC Control .................................................................... 16
6.2 Time Domain Display Tool....................................................................................... 17
6.3 Spectral Analysis Tool............................................................................................ 18
6.4 Histogram Tool .................................................................................................... 19
6.5 Linearity Analysis Tool............................................................................................ 20
7 Bill of Materials, PCB Layout, and Schematics......................................................................... 22
7.1 Bill of Materials .................................................................................................... 22
7.2 PCB Layout ........................................................................................................ 24
7.3 Schematics......................................................................................................... 26
List of Figures
1 ADS8268EVM-PDK ......................................................................................................... 1
2 ADS8168EVM Features .................................................................................................... 5
3 REF5050 5.0-V External Reference Source ............................................................................. 7
4 ADS8168EVM Default Jumper Settings ................................................................................ 10
5 Software Installation Prompts ............................................................................................ 12
6 ADS8168 Device Driver Installation Wizard Prompts ................................................................. 13
7 LabVIEW Run-Time Engine Installation................................................................................. 13
8 ADS8168EVM Successful Installation Complete ...................................................................... 14
9 ADS8168 EVM Folder Post-Installation ................................................................................. 14
10 ADS8168EVM-PDK Hardware Setup and LED Indicators............................................................ 15
11 Launch the ADS8168EVM GUI Software............................................................................... 15
12 EVM GUI Global Input Parameters...................................................................................... 16
13 Time Domain Display...................................................................................................... 17
14 Spectral Analysis Tool..................................................................................................... 18
15 Histogram Analysis Tool .................................................................................................. 19
16 Linearity Analysis Tool..................................................................................................... 21
17 ADS8168 EVM PCB: Top Overlay....................................................................................... 24
18 ADS8168 EVM PCB Layer 1: Top Layer ............................................................................... 24
19 ADS8168 EVM PCB Layer 2: GND Plane.............................................................................. 24
20 ADS8168 EVM PCB Layer 3: Power Planes........................................................................... 24
21 ADS8168 EVM PCB Layer 4: Bottom Layer............................................................................ 24
22 ADS8588EVM-PDK Schematic .......................................................................................... 26
23 ADS8588EVM-PDK Schematic .......................................................................................... 27
24 ADS8588EVM-PDK Schematic........................................................................................... 28
List of Tables

www.ti.com
3
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
1 P2 Header Analog Interface Connections................................................................................ 6
2 Digital I/O Connections for Connector J4 ................................................................................ 8
3 Required Modifications for External Power Connection ............................................................... 9
4 Jumper Configuration Details ............................................................................................ 10
5 External Source Requirements for Evaluation of the ADS8168 ..................................................... 18
6 External Source Requirements for ADS8168 Evaluation ............................................................. 20
7 ADS8168EVM-PDK Bill of Materials..................................................................................... 22
Trademarks
Microsoft, Windows are registered trademarks of Microsoft Corporation.
LabVIEW is a trademark of National Instruments.
All other trademarks are the property of their respective owners.

Overview www.ti.com
4SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
1 Overview
The ADS8168EVM-PDK is a platform for evaluating the performance of the ADS8168 SAR ADC, which is
a 8-channel, 16-bit, 1-MSPS device. The evaluation kit includes the ADS8168EVM board and the
precision host interface (PHI) controller board that enables the accompanying computer software to
communicate with the ADC over USB for data capture and analysis.
The ADS8168EVM board includes the ADS8168 SAR ADC, all the peripheral analog circuits, and
components required to demonstrate performance of the ADC.
The PHI board primarily serves three functions:
• Provides a communication interface from the EVM to the computer through a USB port
• Provides the digital input and output signals necessary to communicate with the ADS8168EVM
• Supplies power to all active circuitry on the ADS8168 board
Along with the ADS8168EVM and PHI controller board, this evaluation kit includes an A-to-micro-B USB
cable to connect to a computer.
1.1 ADS8168EVM-PDK Features
The ADS8168EVM-PDK includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of
the ADS8168 ADC
• USB powered—no external power supply is required
• The PHI controller that provides a convenient communication interface to the ADS8168 ADC over a
USB 2.0 (or higher) for power delivery as well as digital input and output
• Easy-to-use evaluation software for Microsoft®Windows®7 and above, 32- and 64-bit operating
systems
• The software suite includes graphical tools for data capture, histogram analysis, spectral analysis, and
linearity analysis. This suite also has a provision for exporting data to a text file for post-processing.
1.2 ADS8168EVM Features
The ADS8168EVM includes the following features:
• SMA connections for two channels plus common inputs, pin header connections for all other channels
• Provision for using the onboard precision 5-V voltage reference or the default ADS8168 internal 4.096-
V reference. (Selectable by device register setting plus jumpers for the hardware.)
1.3 EVM Main Sections (Circuit Blocks)
The ADS8168EVM has the following circuits:
• Input Circuits
– Channel 1 is populated in buffer configuration, can be driven from SMA connection
– Channel 2 is unpopulated
– All channels can be driven by the header pins of P2
– ADC Driver is in buffer configuration
– Power generation circuits
– External reference circuit
– EEPROM for device identification
– Connection for external supplies, if desired

www.ti.com Overview
5
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
Figure 2. ADS8168EVM Features

EVM Analog Interface www.ti.com
6SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
2 EVM Analog Interface
The ADS8168EVM is designed for easy interfacing to analog sources. The 12-position, dual-row, pin
header connector, J3, provides convenient access to channels Ain1–Ain8 and Ain–COM of the device. In
addition, 3 SMA connectors, IN1, IN2, and IN9 provide a high quality connection to channels Ain1, Ain2,
and Ain-COM, respectively. For channels 1 and 2, a high-impedance input signal conditioning driver circuit
is provided. On all channels, a resistor-capacitor combination helps to provide a stable voltage on the
input of the ADS8168 multiplexer inputs.
Table 1. P2 Header Analog Interface Connections
Header Pin Number Signal Description
P2.1, P2.3, P2.5, P2.7, P2.9, P2.11, P2.13,
P2.15, P2.17, P2.19 GND Analog Ground
P2.2 COM ADC input common
P2.4 AIN1 Analog Channel 1
P2.6 AIN2 Analog Channel 2
P2.8 AIN3 Analog Channel 3
P2.10 AIN4 Analog Channel 4
P2.12 AIN5 Analog Channel 5
P2.14 AIN6 Analog Channel 6
P2.16 AIN7 Analog Channel 7
P2.18 AIN8 Analog Channel 8
P2.20, P2.22, P2.24 AVDD Positive analog power supply
P2.21, P2.23 AVSS Negative analog power supply (default connection is GND)

www.ti.com EVM Analog Interface
7
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
2.1 ADS8168 Internal Reference and EVM Onboard Reference
The ADS8168 device incorporates an internal 4.096-V reference. Upon power up, the device uses this
configuration. In order to select the external reference, the user must select the external reference mode
by writing to the configuration register of the ADS8168. Next, power up the external reference by installing
a shunt on JP1, labeled "AVdd"; and connect the reference to the ADS8168 by installing a shunt on JP3,
labeled "Ref". Input is now 0 V to 5 V. In this mode, note that the reference is limited by the internal
reference buffer of the ADS8168 to AVDD – 0.3 V. A 5-V reference voltage is possible due to the operation
of AVDD at 5.3 V.
Figure 3. REF5050 5.0-V External Reference Source

Digital Interfaces www.ti.com
8SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
3 Digital Interfaces
The EVM interfaces with the PHI that, in turn, communicates with the computer over USB. There are two
devices on the EVM with which the PHI communicates: the ADS8168 ADC (over single- or dual-SDO SPI
bus) and the EEPROM (over I2C). The EEPROM comes pre-programmed with the information required to
configure and initialize the ADS8168EVM-PDK platform. Once the hardware is initialized, the EEPROM is
no longer used.
3.1 ADS8168 Digital Interface
The ADS8168EVM-PDK supports SPI and Multi-SPI serial digital interface as detailed in ADS8168 8-
Channel, 16-Bit, 1-MSPS SAR ADC With Easy to Drive Analog Inputs . The PHI controller is configured to
operate at a 3.3-V logic level and is directly connected to the digital I/O lines of the ADC. The digital
interface configuration can be selected by navigating to the ADS8168EVM Interface Configuration Settings
Tab in the GUI. For more information, see Section 6.1.
Connector J4 provides the digital I/O connections between the ADS8168EVM board and the PHI
controller.
Table 2 summarizes the pin-outs for connector J4.
Table 2. Digital I/O Connections for Connector J4
Pin Number Signal Description
J4.1 EVM_REG_5V5 Regulated 5.5 V
J4.2, J4.4 EVM_RAW_5V Power directly from host USB port
J4.16 RESET Resets ADS8168 (active low)
J4.18 SDI Serial data in
J4.22 nCS Active-low chip select
J4.24 SCLK Serial data clock
J4.28 SCLK_RET Data capture serial data clock
J4.30, J4.32, J4.34 RVS Multifunction signal. When nCS is low, this signal reflects conversion status.
J4.38 SDO-0 Serial data out
J4.40 SDO-1 Serial data out
J4.42 Alarm Output of digital comparator
J4.3, J4.60 GND Ground connections
J4.50 EVM_DVdd Power for interface
J4.56 EVM_ID_SDA SDA for EEPROM
J4.58 EVM_ID_SCL SCL for EEPROM
J4.59 ID_POWER Power supply used only to power the EEPROM (U3) in the EVM board

www.ti.com Power Supplies
9
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
4 Power Supplies
The ADS8168 ADC analog supply (AVDD) is provided by a low-noise linear regulator (TPS7A4700). The
regulator uses a 5.5-V supply out of a switching regulator from the PHI controller to generate a quiet and
stable 5.3-V supply output. The 3.3-V supply to the digital supply of the ADS8168 is provided directly by
an LDO from the PHI controller. The power supply for each active component on the EVM is bypassed
with a ceramic capacitor placed close to that component. Additionally, the EVM layout uses thick traces or
large copper filled areas, where possible, between bypass capacitors and their loads to minimize
inductance along the load current path.
CAUTION
In default configuration, the ADS8168EVM is designed to be used in
conjunction with the PHI controller, and in this configuration, all required
voltages are supplied. Do not apply external power sources to the EVM while in
its default configuration.
CAUTION
If external power supply sources are connected, ensure that modifications are
performed according to Table 3.
Table 3. Required Modifications for External Power Connection
External Supply Default Voltage Connection Location Required Modification
AVDD 5.3 V P1.1 Remove R18, labeled "AVdd"
GND 0 V P1.2, P1.5 None
AVSS 0 V P1.3 Remove R10, labeled "AVss"
5.5 V 5.5 V P1.4 Remove R5, labeled "5.5V"
DVdd 3.3 V P1.6 Remove R2, labeled "DVdd"
• 5.5 V is only used for developing AVDD, via U2. If external AVDD is applied, the 5.5-V voltage node is
not necessary. Apply a minimum of AVDD + 0.2 V, and Do not exceed the rated maximum for U2,
TPS7A4700.
• AVDD is the positive rail for the input driver amplifiers and the ADC driver amplifiers and for the
ADS8168. Use caution not to exceed the maximum rated voltage for these components, taking into
account the value of AVSS.
• If an external reference is used for the ADS8168, AVDD must be 0.2 V higher than the external
reference for proper operation of the internal reference buffer of the ADS8168.
• AVSS is used as the negative rail for the input amplifiers and the ADC driver amplifiers. AVSS can be set
to a small negative voltage value in order to allow the amplifiers to drive a signal to a true zero-volt
value.
• AVSS should be limited to AVDD – 5.5 V (nominally, 200 mV) to protect the OPA350 circuits onboard.

ADS8168EVM_PDK Initial Setup www.ti.com
10 SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
5 ADS8168EVM_PDK Initial Setup
This section explains the initial hardware and software setup procedure that must be completed for the
proper operation of the ADS8168EVM-PDK.
5.1 Default Jumper Settings
Jumper JP2 selects the voltage level to be applied to the AIN-COM pin on the ADS8168. The default
position is between pins 1-2, applying GND to the AIN-COM. Other options are Ref/2 (3-4), or an external
connection (5-6). In default configuration, no other jumpers are necessary.
Figure 4. ADS8168EVM Default Jumper Settings
Table 4. Jumper Configuration Details
Jumper Function Default Position Description
JP1 AVDD Open Connects AVDD to U4, a REF5050 5-V reference
JP2 COM GND Applies voltage to AIN-COM
JP3 Ref Open Connects external reference to the ADS8168 REFIO pin
JP4 WrEn Open Enables writing EVM identification information to the onboard EEPROM
CAUTION
ADS8168EVM Default JumperConfiguration

www.ti.com ADS8168EVM_PDK Initial Setup
11
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
5.2 EVM Graphical User Interface (GUI) Software Installation
Download the latest version of the EVM GUI installer from the Tools and Software folder of the
ADS8168EVM-PDK and run the GUI installer to install the EVM GUI software. The user must have
administrator privileges on the PC to be able to install the EVM software. The following steps list the
directions to install the software
CAUTION
It may be necessary to manually disable any anti-virus software running on the
computer before downloading the EVM GUI installer onto the local hard disk.
Otherwise, depending on the anti-virus settings, an error message may appear
or the installer.exe file may be deleted.
Step 1. Download the latest version of the installer from the Tools and Software folder of the
ADS8168 and run the GUI installer. Accept the license agreements and follow the on-screen
instructions to complete the installation.

ADS8168EVM_PDK Initial Setup www.ti.com
12 SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
Figure 5. Software Installation Prompts

www.ti.com ADS8168EVM_PDK Initial Setup
13
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
Step 2. As a part of the ADS8168 EVM GUI installation, a prompt with a Device Driver Installation will
appear on the screen. Click Next to proceed.
Figure 6. ADS8168 Device Driver Installation Wizard Prompts
NOTE: A notice may appear on the screen stating that Widows cannot verify the publisher of this
driver software. Select Install this driver software anyway.
Step 3. The ADS8168EVM-PDK requires LabVIEW™ Run-Time Engine may prompt for the
installation of this software, if not already installed.
Figure 7. LabVIEW Run-Time Engine Installation

ADS8168EVM_PDK Initial Setup www.ti.com
14 SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
Figure 8. ADS8168EVM Successful Installation Complete
Step 4. After these installations, verify that C:\Program Files (x86)\Texas Instruments\ADS8168 EVM
is as shown in Figure 9.
Figure 9. ADS8168 EVM Folder Post-Installation

www.ti.com ADS8168EVM-PDK Operation
15
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
6 ADS8168EVM-PDK Operation
The following instructions are a step-by-step guide to connecting the ADS8168 to the computer and
evaluating the performance of the ADS8168:
1. Connect the ADS8168EVM to the PHI. Install the two screws as indicated in Figure 10.
2. Use the USB cable provided to connect the PHI to the computer.
1. LED D5 on the PHI lights up, indicating that the PHI is powered up.
2. LEDs D1 and D2 on the PHI starts blinking to indicate that the PHI is booted up and
communicating with the PC. The resulting LED indicators are shown in Figure 10.
Figure 10. ADS8168EVM-PDK Hardware Setup and LED Indicators
3. Double click on the ADS8168 EVM.exe file to launch the EVM GUI, as shown in Figure 11.
Figure 11. Launch the ADS8168EVM GUI Software

ADS8168EVM-PDK Operation www.ti.com
16 SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
6.1 EVM GUI Global Settings for ADC Control
Although the EVM GUI does not allow direct access to the voltage levels and timing configuration of the
ADC digital interface, the EVM GUI provide users high-level control over the various interface modes and
frequencies of the ADS8168, as well as the capture and multiplexer sequencing options. In addition, the
EVM GUI provides full low-level control of all register settings.
Figure 12 shows the Device Configuration page, through which various functions of the ADS8168 are
exercised. These are global settings, and they persist across the different GUI tools or GUI pages listed in
the top left plane. The software defaults to operating the ADS8168 in Manual Mode, sampling Channel 0
at 1 MSPS. The digital interface defaults to operating the SCLK at 15 MHz.
Figure 12. EVM GUI Global Input Parameters
Independent of the interface configuration, the user can specify a target SCLK frequency and sampling
frequency (in Hz) and the GUI tries to match this frequency as closely as possible by changing the PHI
PLL settings. The achievable frequencies can differ from the target value displayed. Achievable
frequencies are limited by the various interface modes, and the ADS8168 provide options which allow a
very low SCLK. This pane allows the user to try various settings available on the ADS8168 in an iterative
fashion until the user converges to the best settings for the corresponding test scenario.
The Device Reset button in the GUI functions as a Master RESET to both the ADS8168 EVM and the
GUI. When the button is pressed, the ADC RESETs to the default settings shown in Figure 12

www.ti.com ADS8168EVM-PDK Operation
17
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
6.2 Time Domain Display Tool
The time domain display tool allows visualization of the time domain conversion results given a set of
analog input signals.
If multiple channels are selected, all data is plotted on the same display; however, the user can selectively
display captured data by using the check-box interface on the right.
Figure 13. Time Domain Display

ADS8168EVM-PDK Operation www.ti.com
18 SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
6.3 Spectral Analysis Tool
The spectral analysis tool is intended to evaluate the dynamic performance (SNR, THD, SFDR, SINAD,
and ENOB) of ADS8168 SAR ADC through single-tone sinusoidal signal FFT analysis using the 7-term
Blackman-Harris window setting.
For dynamic performance evaluation, the external differential source must have better specifications than
the ADS8168 itself to ensure that the measured system performance is not limited by the performance of
the signal source. Therefore, the external reference source must meet the source requirements mentioned
in Table 5.
Table 5. External Source Requirements for Evaluation of the ADS8168
Specification Description Specification Value
Signal frequency 2 kHz
External source type Single ended
External source common-mode Vref/2, nominally 2.048 V
Maximum noise 14.5 µVRMS
Minimum SNR 100 dB
Maximum THD –110 dB
Figure 14. Spectral Analysis Tool

www.ti.com ADS8168EVM-PDK Operation
19
SBAU291–November 2017
Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
Finally, the FFT tool includes windowing options that are required to mitigate the effects of non-coherent
sampling (this discussion is beyond the scope of this document). The 7-Term Blackman Harris window is
the default option and has sufficient dynamic range to resolve the frequency components of up to a 24-bit
ADC. Note that the None option corresponds to not using a window (or using a rectangular window) and is
not recommended.
6.4 Histogram Tool
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which
is an indicator of the number of bits of ADC resolution losses resulting from noise generated by the
various sources connected to the ADC when measuring a dc signal. The cumulative effect of noise
coupling to the ADC output from sources such as the input drive circuits, the reference drive circuit, the
ADC power supply, and the ADC itself is reflected in the standard deviation of the ADC output code
histogram that is obtained by performing multiple conversions of a dc input applied to a given channel.
The histogram corresponding to a dc input is displayed after clicking the Capture button, as shown in
Figure 15:
Figure 15. Histogram Analysis Tool

ADS8168EVM-PDK Operation www.ti.com
20 SBAU291–November 2017
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
ADS8168EVM-PDK
6.5 Linearity Analysis Tool
The linearity analysis tool measures and generates the performance DNL and INL plots over code for the
ADS8168. A 2-kHz sinusoidal input signal is required, which is ideally slightly saturated (100–200 mV
outside the full-scale range) with very low distortion. Because the input circuits on the ADS8168 EVM in
their default power configuration do not allow a saturated signal on the negative rail, the linearity algorithm
attempts to report the performance of the codes of the ADC which could be adequately tested. It should
be noted that the results of this test include the nonlinearities of the external signal source, the multiplexer
drive amplifier (if used), and the ADC driver amplifier. For this reason, the external source linearity must
be better than the ADC linearity. To make sure that the DNL and INL of the ADC are correctly measured,
the external source must meet the requirements in Table 6.
Table 6. External Source Requirements for ADS8168 Evaluation
Specification Description Specification Value
Signal frequency 2 kHz
External source type Single ended, referred to GND
External source common mode Vref/2, nominally 2.048 V
Signal amplitude Vref/2(Vp) + 100 mVp
Maximum noise 14.5 µVRMS
Maximum SNR 100 dB
Maximum THD –110 dB
The number-of-hits setting depends on the external noise source. For a 100-dB SNR external source with
approximately 30 µVrms of noise, total number of hits must be 256.
NOTE: This analysis can take a couple of minutes to run and the evaluation board must remain
undisturbed during the complete duration of the analysis.