Texas Instruments TAS5508-5142K7EVM User manual

TAS5508-5142K7EVM User’s GuideEvaluation Module for the TAS5508B Digital Audio PWMProcessor and TAS5142 Digital AmplifierPower Output Stage
User's Guide
June 2006
SLEU071

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Contents
1 Overview ................................................................................................................... 51.1 TAS5508-5142K7EVM Features.................................................................................. 61.2 PCB Key Map ....................................................................................................... 7
2 System Interfaces ...................................................................................................... 92.1 Power Supply (PSU) Interface (J901 and J900) ................................................................ 92.2 PSU Control Interface (J902) .................................................................................... 102.3 Loudspeaker Connectors (J101 …J107) ...................................................................... 102.4 Headphone Connector (J700) ................................................................................... 112.5 Control Interface (J40) ............................................................................................ 112.6 Digital Audio Interface (J60) ..................................................................................... 13
3 Protection ................................................................................................................ 153.1 Short-Circuit Protection and Fault-Reporting Circuitry ....................................................... 153.2 Fault Reporting .................................................................................................... 15
4 Related Documentation From Texas Instruments ......................................................... 174.1 Trademarks ........................................................................................................ 17
Important Notices ............................................................................................................... 18
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List of Figures
1-1 Integrated PurePath Digital™ Amplifier System ......................................................................... 61-2 Physical Structure for TAS5508-5142K7EVM (Rough Outline) ....................................................... 72-1 Recommended Power-Up Sequence ..................................................................................... 92-2 J901 and J900 Pin Numbers ............................................................................................... 92-3 J902 Pin Numbers ......................................................................................................... 102-4 J101 . . . J107 Pin Numbers .............................................................................................. 112-5 J700 Pin Numbers ......................................................................................................... 11
List of Tables
2-1 Recommended Supply Voltages ........................................................................................... 92-2 J901 Pin Description ....................................................................................................... 102-3 J900 Pin Description ....................................................................................................... 102-4 J902 Pin Description ....................................................................................................... 102-5 J101 . . . J107 Pin Description ............................................................................................ 112-6 J700 Pin Description ....................................................................................................... 112-7 J40 Pin Description ........................................................................................................ 112-8 J60 Pin Description ........................................................................................................ 133-1 TAS5142 Warning/Error Signal Decoding .............................................................................. 15
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Chapter 1SLEU071 – June 2006
Overview
The TAS5508-5142K7EVM PurePath Digital™ customer evaluation amplifier moduledemonstrates two audio integrated circuits, TAS5508B and TAS5142, from TexasInstruments (TI).
The TAS5508BPAG is a high-performance 32-bit (24-bit input) multichannel PurePathDigital pulse width modulator (PWM) based on Equibit™ technology, with a fullysymmetrical AD modulation scheme. It accepts an input sample rate from 32 kHz to192 kHz. The device also has digital audio processing (DAP) that provides 48-bit signalprocessing, advanced performance, and a high level of system integration. The devicehas interfaces for headphone output and power supply volume control (PSVC).
The TAS5142DKD is a compact, high-power, digital amplifier power stage designed todrive a 4- Ωloudspeaker up to 100 W/10% THD+N. It contains integrated gate drivers,four matched and electrically isolated enhancement-mode N-channel power DMOStransistors, and protection/fault-reporting circuitry.
The DKD package has a PowerPAD™ on the top side for heat transfer through aheatsink. The heatsink in this design is for evaluation purposes only.
This EVM, together with a TI input-USB board, is a complete 7-channel digital audioamplifier system, which includes digital input (S/PDIF), analog inputs, interface to PC,and DAP features, such as digital volume control, input and output mixers, auto mute,equalization, tone controls, loudness, dynamic range compression, and PSVC output.There are configuration options for stereo line level output, stereo headphone output,and power-stage failure protection.
This 6.1 system is designed for home-theater applications, such as A/V receivers, DVDminicomponent systems, home theater in a box (HTIB), DVD receivers, or plasmadisplay panels (PDPs).
PurePath Digital, Equibit, PowerPAD are trademarks of Texas Instruments.
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1.1 TAS5508-5142K7EVM Features
I2S
Bus
TAS5508-5142K7EVM
MODULE
I2C Bus
Example
TI Input-USB
board
6 Channel
Analog
Input
USB
Interface
Optical
and
Coaxia
lS/PDIF
Input
Control Interface
Power Supply
7 Channel
Speaker Output
2 Channel
Headphone Output
TAS5508-5142K7EVM Features
•7-channel PurePath Digital evaluation module (double-sided plated-through PCB layout)•Stereo channel line output•Stereo headphone output•Self-contained protection system (short circuit and thermal)•Standard I
2
S and I
2
C/control connector for TI input board•Double-sided plated-through PCB layout
Figure 1-1. Integrated PurePath Digital™ Amplifier System
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1.2 PCB Key Map
SPEAKER OUTPUTSSPEAKER OUTPUTS
TAS5508B
OUTPUT STAGE
CHANNEL 1
OUTPUT STAGE
CHANNEL 3
OUTPUT STAGE
CHANNEL 2
OUTPUT STAGE
CHANNEL 4
OUTPUT STAGE
CHANNEL 5
3.3V
Regulator
5V
Regulator
Gate Drive
Regulator
PSU
INTERFACE
(J901)
PSU
CONTROL
(J902)
INPUT SIGNAL
INTERFACE (J60)
CONTROL
INTERFACE (J40)
HEADPHONE
OUTPUT
(J700)
OUTPUT STAGE
CHANNEL 6
OUTPUT STAGE
CHANNEL 7
J101J103J102J104
PSU
INTERFACE
(J900)
J105J106J107
PCB Key Map
Physical structure for the TAS5508-5142K7EVM is illustrated in Figure 1-2 .
Figure 1-2. Physical Structure for TAS5508-5142K7EVM (Rough Outline)
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PCB Key Map
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2.1 Power Supply (PSU) Interface (J901 and J900)
Output stage power supply
RESET
>1ms
System power supply
4
1
2
3
(PCB connector top view)
Chapter 2SLEU071 – June 2006
System Interfaces
This chapter describes the TAS5508-5142K7EVM board in regards to power suppliesand system interfaces.
The TAS5508-5142K7EVM module must be powered from external power supplies. High-end audioperformance requires a stabilized power supply with low ripple voltage and low output impedance.
Note: The length of power-supply cable must be minimized. Increasing length of PSU cable isequal to increasing the distortion for the amplifier at high output levels and lowfrequencies.
Maximum output-stage supply voltage depends of the speaker load resistance. Please check therecommended maximum supply voltage in the TAS5142 data sheet.
Table 2-1. Recommended Supply Voltages
VOLTAGEDESCRIPTION CURRENT RECOMMENDATIONSLIMITATIONS
System power supply 15 V to 20 V 0.3 AOutput-stage power supply 0 V to 32 V 6 A
(1)
(1)
The rated current correspond to 2-channel full scale (80 W each), which most likely is adequate fora standard 8-channel amplifier design.
The recommended TAS5142 power-up sequence is shown in the figure below. For proper TAS5142operation, the RESET signal should be kept low during power up. RESET is pulled low during power upfor 200 ms by the onboard reset generator (U73).
Figure 2-1. Recommended Power-Up Sequence
Figure 2-2. J901 and J900 Pin Numbers
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2.2 PSU Control Interface (J902)
1
2
3
5
4
(PCB connector top view)
2.3 Loudspeaker Connectors (J101 …J107)
PSU Control Interface (J902)
Table 2-2. J901 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 PVDD Output-stage power supply2 SYSTEM System power supply3 GND Ground4 GND Ground
Table 2-3. J900 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 PVDD Extra output-stage power supply2 PVDD Extra output-stage power supply3 GND Extra ground4 GND Extra ground
This interface is used for onboard sensing of output supply voltage and for the power supply volumecontrol (PSVC) signal.
Figure 2-3. J902 Pin Numbers
Table 2-4. J902 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 — Reserved for future use2 PVDD Sense of output power supply3 GND Ground4 RESET System reset (bidirectional)5 PSVC Power supply volume control signal
CAUTION
Both positive and negative speaker outputs are floating and may not beconnected to ground (e.g., through an oscilloscope).
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1
2
(PCB connector top view)
2.4 Headphone Connector (J700)
1
4
2 3
2.5 Control Interface (J40)
Headphone Connector (J700)
Figure 2-4. J101 . . . J107 Pin Numbers
Table 2-5. J101 . . . J107 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 OUT-1 Speaker negative output2 OUT-2 Speaker positive output
Figure 2-5. J700 Pin Numbers
Table 2-6. J700 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 OUT-R Right headphone output2 GND Ground3 — For future use4 OUT-L Left headphone output
This interface connects the TAS5508-5142K7EVM board to a TI input-USB board.
Table 2-7. J40 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 GND Ground2 RESERVED —3 GND Ground4 RESET System reset (bidirectional). ActivateMUTE before RESET for quiet reset.5 BKND-ERR Backend error (or soft reset) providesreduced click and pop reset, withoutresetting I
2
C volume register settings.6 MUTE Ramp volume from any setting tonoiseless soft mute. Mute can also beactivated by I
2
C.7 PDN Power down. TAS5508B will go topower-down state when activated.8 RESERVED —9 RESERVED —10 SDA I
2
C data clock
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Control Interface (J40)
Table 2-7. J40 Pin Description (continued)
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
11 GND Ground12 SCL I
2
C bit clock13 RESERVED —14 RESERVED —15 RESERVED —16 RESERVED —17 GND Ground18 RESERVED —19 RESERVED —20 SD Shutdown error reporting for allchannels. Activated if TAS5142 hashigh current or high temperature. SeeChapter 3, Protection.21 SD Shutdown reporting. Activated if one ormore TAS5142 has high current or hightemperature. Pin 21 connected to Pin20. See Chapter 3, Protection.22 OTW Temperature warning. Activated ifTAS5142 has reached temperaturewarning level.23 OTW Temperature warning. Activated if oneor more TAS5142 has reachedtemperature warning level. Pin 23connected to Pin 22.24 HP-SEL Headphone select. Headphone activewhen LOW and inactive when HIGH. Touse this pin, <100- Ωresistor must beplaced for R50.25 GND Ground26 GND Ground27 RESERVED —28 RESERVED —29 RESERVED —30 RESERVED —31 GND Ground32 GND Ground33 +5V +5Vdc power supply (output)34 +5V +5Vdc power supply (output)
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2.6 Digital Audio Interface (J60)
Digital Audio Interface (J60)
The digital audio interface contains digital audio signal data (I
2
S), clocks, etc. Please see the TAS5508BData Manual for signal timing and details not explained in this document.
Table 2-8. J60 Pin Description
PIN NO. NET-NAME AT SCHEMATICS DESCRIPTION
1 GND Ground2 MCLK Master clock input. Low jitter systemclock for PWM generation andreclocking. Ground connection fromsource to TAS5508B must be a lowimpedance connection.3 GND Ground4 SDIN1 I
2
S data 1, channel 1 and 25 SDIN2 I
2
S data 2, channel 3 and 46 SDIN3 I
2
S data 37 SDIN4 I
2
S data 48 — Reserved9 — Reserved10 GND Ground11 SCLK I
2
S bit clock12 GND Ground13 LRCLK I
2
S left-right clock14 GND Ground15 — Reserved16 GND Ground
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Digital Audio Interface (J60)
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3.1 Short-Circuit Protection and Fault-Reporting Circuitry
3.2 Fault Reporting
Chapter 3SLEU071 – June 2006
Protection
This chapter describes the short-circuit protection and fault-reporting circuitry of theTAS5142 device.
The TAS5142 is a self-protecting device that provides fault reporting (including high-temperatureprotection and short-circuit protection). The TAS5142 is configured in back-end auto-recovery mode and,therefore, resets automatically after all errors (M1, M2, and M3 are set low). This means that the devicewill restart itself after a error occasion and report through the SD error signal.
The OTW and SD outputs from the TAS5142 indicate fault conditions. Please refer to the TAS5142 DataManual for a description of these pins.
Table 3-1. TAS5142 Warning/Error Signal Decoding
OTW SD DEVICE CONDITION
0 0 High-temperature error and/or high-current error0 1 High-temperature warning1 0 Undervoltage lockout or high-current error1 1 Normal operation, no errors/warnings
The temperature warning signals at the TAS5508-5142K7EVM board are wired-OR to one temperaturewarning signal ( OTW – pin 22 in control interface connector). Shutdown signals are wired-OR into oneshutdown signal ( SD – pin 20 in control interface connector).
The shutdown signals, together with the temperature warning signal, give chip state information asdescribed in Table 3-1 . Device fault-reporting outputs are open-drain outputs.
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Fault Reporting
Protection 16 SLEU071 – June 2006Submit Documentation Feedback

4.1 Trademarks
Chapter 4SLEU071 – June 2006
Related Documentation From Texas Instruments
The following is a list of documents that have detailed descriptions of the integrated circuits used in thedesign of the TAS5508-5142K7EVM. This information can be obtained at the URL http://www.ti.com .•TAS5508B data sheet (SLES162 )•TAS5142 data sheet (SLES126 )•TPA112 data sheet (SLOS212 )•TPS3801K33 data sheet (SLVS219 )•LM317M data sheet (SLVS297 )•TPS76733 data sheet (SLVS208 )
Additional documents•TAS5508-5142K7EVM Application Report (SLEA055 )•PC Configuration Tool for TAS5508B (TAS5508 GUI ver. 4.0 or later)•General Application Notes
Equibit, PurePath Digital, and PowerPAD are trademarks of Texas Instruments.
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EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be afinished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods beingprovided are not intended to be complete in terms of required design-, marketing-, and/ormanufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components orcircuit boards. This evaluation board/kit does not fall within the scope of the European Uniondirectives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of thesedirectives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, theboard/kit may be returned within 30 days from the date of delivery for a full refund. THEFOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY,INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULARPURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further,the user indemnifies TI from all claims arising from the handling or use of the goods. Due to theopen construction of the product, it is the user’s responsibility to take any and all appropriateprecautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTYSHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, ORCONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with theuser is not exclusive.TI assumes no liability for applications assistance, customer product design, softwareperformance, or infringement of patents or services described herein.Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’sGuide prior to handling the product. This notice contains important safety information abouttemperatures and voltages. For additional information on TI’s environmental and/or safetyprograms, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering orrelating to any machine, process, or combination in which such TI products or services might beor are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT,DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be afinished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devicespursuant to part 15 of FCC rules, which are designed to provide reasonable protection againstradio frequency interference. Operation of this equipment in other environments may causeinterference with radio communications, in which case the user at his own expense will berequired to take whatever measures may be required to correct this interference.

EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of 0 to 32 V and the outputvoltage range of 15 V to 20 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damageto the EVM. If there are questions concerning the input range, please contact a TI fieldrepresentative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/orpossible permanent damage to the EVM. Please consult the EVM User's Guide prior toconnecting any load to the EVM output. If there is uncertainty as to the load specification, pleasecontact a TI field representative.During normal operation, some circuit components may have case temperatures greater than75°C. The EVM is designed to operate properly with certain components above 75°C as long asthe input and output ranges are maintained. These components include but are not limited tolinear regulators, switching transistors, pass transistors, and current sense resistors. These typesof devices can be identified using the EVM schematic located in the EVM User's Guide. Whenplacing measurement probes near these devices during operation, please be aware that thesedevices may be very warm to the touch.
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