Texas Instruments TLV3607 User manual

EVM User's Guide: TLV3607 TLV3607EVM
TLV3607 Evaluation Module
Description
The TLV3607EVM is an evaluation board designed
to evaluate the high-speed dual channel TLV3607
comparator. The TLV3607EVM has layout options
intended to simply evaluate timing performance
with different measurement tools. The output of
the TLV3607 is designed for low-voltage differential
signals (LVDS), which provide high-speed signals to
interconnect devices such as FPGAs with minimal
power dissipation.
Features
• Low propagation delay
• Low overdrive dispersion
• High toggle frequency
• Narrow pulse width detection capability
• LVDS output
• Low input offset voltage
• RTE Package 16-pin WQFN
TLV3607EVM Board (Top View)
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1 Evaluation Module Overview
1.1 Introduction
This user's guide describes the functionality and set up procedure of the evaluation board TLV3607EVM, which
is designed to evaluate the performance of the high-speed dual channel TLV3607 comparator. Information such
as the contents of the kit, specifications of the device, and recommended equipment for the set up is also
included. Although TLV3607 can be operated in either single or split supply configuration, this user's guide will
assume single supply is used.
+
–
C19
0.1uF
C18
0.1uF
OUT-B
OUT+B
+
–
C16
0.1uF
C17
0.1uF
OUT+A
OUT-A
TLV3607A
TLV3607B
+
–
R4
IN+A
IN-A
IN+A
SENSE SHDNA
LE/HYSA
R6
C5
(50

Option)
R12
IN-B
IN+B
IN+B
SENSE
SHDNB
LE/HYSB
R9
C6
(50

Option)
R7
R5
(Hysteresis
Option)
R8
R10
(Hysteresis
Option)
R3
(Hysteresis
Option)
R11
(Hysteresis
Option)
Figure 1-1. TLV3607EVM Block Diagram
1.2 Kit Contents
The kit comes with the following:
• 1 x TLV3607EVM
• 4 x jumper caps
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1.3 Specification
• Supply Range: +2.4 V to +5.5 V
• Input Common Mode Voltage Range: (VEE - 0.2 V) to (VCCI + 0.2 V)
Table 1-1. TLV3607EVM SMA and Test Point to DUT Pin Mapping
TLV3607EVM CONNECTIONS
SMA J7: IN+A
SMA J5: IN+A SENSE
IN+A (Pin 1)
SMA J10: IN-A IN-A (Pin 2)
SMA J11: IN-B IN-B (Pin 3)
SMA J18: IN+B
SMA J12: IN+B SENSE
IN+B (Pin 4)
Test Point 5: VCCI VCCI (Pin 5)
Test Point 2 and 4: VEE VEE (Pin 6, 14)
SMA J15: LE/HYSB LE/HYSB (Pin 7)
SMA J16: SHDNB SHDNB (Pin 8)
SMA J9: OUT+B OUT+B (Pin 9)
SMA J14: OUT-B OUT-B (Pin 10)
SMA J8: OUT-A OUT-A (Pin 11)
SMA J6: OUT+A OUT+A (Pin 12)
Test point 3: VCCO VCCO (Pin 13)
SMA J4: LE/HYSA LE/HYSA (Pin 15)
SMA J2: SHDNA SHDNA (Pin 16)
Test Points 1 and 6: GND System Ground
Note
There are only sense lines for the non-inverting inputs (IN+A SENSE and IN+B SENSE).
1.4 Device Information
The following device is used in this evaluation module:
• TLV3607RTER
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2 Hardware
2.1 Recommended Equipment Setup
• Power Supply
• High Speed Functional Generator with fast rise/fall time recommended (≤ 500 ps)
• High Speed Oscilloscope with 50-Ω terminations
• SMA Cables/adapters
– All sensed input signals and output signals must have matched cable lengths
• IN+A SENSE, IN+B SENSE, OUT+A, OUT-A, OUT+B, OUT-B
2.2 Board Setup
2.2.1 Power Supplies
The TLV3607EVM can operate from +2.4V to +5.5V in either single or split supply configuration. Connect VCCI
and VCCO to TP5 and TP3, respectively. For single supply configuration, connect system ground to TP1 and
TP6; use J3 and J17 to connect VEE to GND. This user's guide assumes single supply configuration is used.
If split supply configuration is desired, then connect VEE to TP2 and TP4; connect GND to TP1 and TP6. This
configuration can be desirable if the reference voltage is at GND or if there is a need to zoom into the amplitude
of the input as much as possible.
Figure 2-1. TLV3607EVM Power Supplies Connection
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2.2.2 Inputs
Resistors R4 and R12 are 0-Ω resistors. The non-inverting input terminals (IN+A and IN+B) have corresponding
sense lines so that the inputs to the device can be terminated on the lines with 50-Ω to an oscilloscope.
This allows the input signals to be observed with minimal loading and distortion. There are also optional input
resistors (R6 and R9) for direct 50-Ω termination if required by the input signal generator, otherwise the input
resistors can be left uninstalled.
+
–
R4
IN+A
IN-A
IN+A
SENSE
R6
C5
Option for 50

termination
TLV3607A
+
–
R12
IN-B
IN+B
IN+B
SENSE
R9
C6
Option for 50

termination
TLV3607B
Figure 2-2. Input Side Block Diagram
The TLV3607 can be put in either active or shutdown mode through the SHDNA and SHDNB pins. Each channel
of the TLV3607 is in shutdown mode when their respective shutdown pins are tied to VEE though jumpers J1
and J13; otherwise the pins can be left open or tied to VCCO. If necessary to dynamically control when the
device shutdowns, then a pulsing signal can be applied to SMA connectors J2 and J16.
The TLV3607 utilizes pins LE/HYSA and LE/HYSB to adjust the internal hysteresis of the comparator through
the attachment of a external resistors R2 and R14 connecting to VEE. R2 and R14 are 150-kΩ resistors to allow
for 30 mV of internal hysteresis, but these resistors can be replaced accordingly to desired amount of hysteresis.
C4 and C7 are 100 pF capacitors for extra filtering.
Alternatively, these pins also have a latch functionality. If the pin is connected to VEE, then the device holds
the output state for as long as the pin remains connected to that voltage. If the pin is connected to VCC, then
the device functions normally with no hysteresis. However, if necessary to dynamically control when the device
latches, then a pulsing signal can be applied to SMA connectors J4 and J15.
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+
–
SHDNA
LE/HYSA
TLV3607A
+
–
SHDNB
LE/HYSB
TLV3607B
R2
C4
VEE
R1
VEE
VCCO
R13
C7
VEE
R14
VEE
VCCO
J13
J1
Figure 2-3. SHDN and LE/HYS Side Block Diagram
2.2.3 Outputs
C16, C17, C18, and C19 are installed with 0.1-uF capacitors. If a 100-Ω differential probe is unavailable to
measure the LVDS output, then these capacitors allow for the AC portion of the signal to be seen on a 50-Ω
terminated scope. Keep in mind that any duty cycle other than 50% results in a DC portion of the signal that
is not halfway between VOH and VOL. As mentioned earlier, this is due to the charging and discharging of the
capacitors. A higher duty cycle results in a higher DC output voltage because the capacitors are charging more
than the capacitors are discharging.
+
–
C19
0.1uF
C18
0.1uF
OUT-B
OUT+B
+
–
C16
0.1uF
C17
0.1uF
OUT+A
OUT-A
TLV3607A
TLV3607B
Figure 2-4. Output Side Block Diagram
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2.2.4 Hysteresis
The TLV3607 utilizes pins LE/HYSA and LE/HYSB to adjust the internal hysteresis of the comparator through
the attachment of a external resistors R2 and R14 connecting to VEE. These resistors can be replaced
accordingly to desired amount of hysteresis. A curve of hysteresis versus resistance is provided below to provide
guidance in setting the desired amount.
Figure 2-5. VHYST (mV) vs. RHYST (kΩ)
The TLV3607EVM is also able to support external hysteresis for each non-inverting input. Input resistors R7
and R8 are 0-Ω resistors but can be replaced accordingly for desired amount of hysteresis. For channel A,
the feedback resistor is the combination of R5 and R3. Likewise, for channel B, the feedback resistor is the
combination of R10 and R11. All resistors must be populated. If no external hysteresis is required, then these
optional feedback resistors can be left uninstalled.
+
–
C19
0.1uF
C18
0.1uF
OUT-B
OUT+B
+
–
C16
0.1uF
C17
0.1uF
OUT+A
OUT-A
R3 R11
R10
R8
R5
R7
IN+A
IN-A
IN-B
IN+B
TLV3607A
TLV3607B
Optional Feedback
Resistors
RFeedback = R10 + R11
RFeedback = R5 + R3
Optional Feedback
Resistors
Input Resistor
Input Resistor
Figure 2-6. Hysteresis Block Diagram
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2.3 Quick-Start Procedure
Note
Do not turn on power supply until all connections to the device are made to the board.
The procedures listed below are the steps for a quick-start set-up using channel A.
1. Set VCCI/VCCO Power Supply to 5.0 V and disable the power supply output.
2. Since the same power supply is used for both VCCI and VCCO, connect positive terminal supply to TP5 and
TP3, and negative terminal to TP6.
3. Connect VEE and GND via jumper J17 and J3.
4. Connect SHDNA to VCCO via jumper J1 and SHDNB to VEE via jumper J13. This sets Channel A in active
mode and Channel B in shutdown mode.
5. Verify that cables connecting to IN+A SENSE, OUT+A, and OUT-A are matched length and impedance.
Perform any de-skewing if necessary. Set the function generator (50-Ω terminated) to produce a square
wave output with 400mVpp at 10 MHz, with a DC offset of 0.300 V. Disable the signal generator output.
Connect the output to IN+A.
6. Set one of the outputs of the DC power supply to 300 mV. Disable the power supply output. Connect the
output to IN-A.
7. Connect OUT+A and OUT-A to a 50-Ω terminated channel on the oscilloscope.
8. Connect IN+A SENSE, to another 50-Ω terminated scope channel.
9. Enable the VCCI/VCCO power supply.
10. Verify the total supply current is < 18 mA.
11. Enable the signal generator.
12. Monitor and verify the inputs from IN+A SENSE.
13. Monitor and verify the outputs for OUT+A and OUT-A.
DC Power Supply
+0.3V GND +5V
BNC-SMA
Note: The INA+ Sense
(J5) cable and OUT+A
(J6), OUT-A (J8) cables
should be length
matched
High Speed Oscilloscope
(50 Ohm Termina  ons)
CH. 1 CH. 2 CH. 3
BNC-SMA
BNC-SMA
BNC-SMA
High Speed Pulse Generator
(<500 ps Rise/Fall Time)
BNC-SMA
BANANA-GRABBER
CH. 1
BANANA-GRABBER
Figure 2-7. TLV3607EVM Quick Start Setup
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Next, is a scope shot capture of the inputs and outputs described in the quick-start procedure.
IN+A
OUT-A
OUT+A
Figure 2-8. Quick-Start Example
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3 Hardware Design Files
3.1 Schematic
Figure 3-1. TLV3607EVM Schematic
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