Texas Instruments OPA928 User manual

User’s Guide
OPA928 Evaluation Module
ABSTRACT
This user’s guide describes the operation and use of the OPA928 evaluation module (EVM). The user's guide
provides information on how to set up the EVM and describes different circuit configurations that can be used to
evaluate the performance of the OPA928 femtoampere, input-bias-current op amp. Throughout this document,
the terms evaluation board, evaluation module, and EVM are synonymous with the OPA928EVM. This document
also includes an electrical schematic, simplified schematics of OPA928 applications circuits, a printed circuit
board (PCB) layout drawing, and a parts list for the EVM.
Note
For best possible performance, make sure to review the Section 1.1 before handling the EVM board.
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Table of Contents
1 Read This First........................................................................................................................................................................3
1.1 EVM Cleanliness Guidelines..............................................................................................................................................3
2 Overview..................................................................................................................................................................................4
2.1 Guarding and Shielding......................................................................................................................................................4
3 Getting Started........................................................................................................................................................................5
3.1 Related Documentation From Texas Instruments.............................................................................................................. 5
3.2 Electrostatic Discharge Caution......................................................................................................................................... 5
4 EVM Circuit Description.........................................................................................................................................................6
4.1 High-Impedance Amplifier Circuit.......................................................................................................................................6
4.2 Transimpedance Amplifier Circuit...................................................................................................................................... 7
5 Cleaning the EVM..................................................................................................................................................................13
5.1 Ultrasonic Wash............................................................................................................................................................... 13
5.2 Manual Cleaning Procedure.............................................................................................................................................13
6 Schematic, PCB Layout, and Bill of Materials................................................................................................................... 13
6.1 EVM Schematic................................................................................................................................................................14
6.2 PCB Layout...................................................................................................................................................................... 16
6.3 Bill of Materials.................................................................................................................................................................20
List of Figures
Figure 4-1. HI-Z Circuit Schematic (Simplified)............................................................................................................................6
Figure 4-2. TIA Circuit Schematic (Simplified).............................................................................................................................7
Figure 4-3. T-Switch Timing Diagram.......................................................................................................................................... 9
Figure 4-4. T-Switch Logic Low (Normal Operation)..................................................................................................................10
Figure 4-5. T-Switch Logic Low Equivalent Circuit (Normal Operation).....................................................................................10
Figure 4-6. T-Switch Logic High (Discharge Feedback).............................................................................................................11
Figure 4-7. T-Switch Logic High Equivalent Circuit (Discharge Feedback)................................................................................11
Figure 4-8. Guarded Diode Limiter............................................................................................................................................ 12
Figure 6-1. OPA928EVM Hi-Z Schematic..................................................................................................................................14
Figure 6-2. OPA928EVM TIA Schematic................................................................................................................................... 15
Figure 6-3. Top Overlay............................................................................................................................................................. 16
Figure 6-4. Top Solder Mask......................................................................................................................................................16
Figure 6-5. Top Layer PCB Layout............................................................................................................................................ 17
Figure 6-6. Internal Power Layer PCB Layout........................................................................................................................... 17
Figure 6-7. Internal Guard Layer PCB Layout........................................................................................................................... 18
Figure 6-8. Bottom Layer PCB Layout.......................................................................................................................................18
Figure 6-9. Bottom Solder Mask................................................................................................................................................ 19
Figure 6-10. Bottom Overlay......................................................................................................................................................19
List of Tables
Table 4-1. TIA Jumper Block Connections...................................................................................................................................8
Table 4-2. TIA Pin Socket Configurations.................................................................................................................................... 8
Table 6-1. OPA928EVM Bill of Materials....................................................................................................................................20
Trademarks
All trademarks are the property of their respective owners.
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1 Read This First
1.1 EVM Cleanliness Guidelines
Applications requiring femtoampere-level performance are extremely sensitive to contamination. Contaminants
in the form of solder flux, salts, oils, organic acids, and more can form conductive paths over PCB traces that
allow small currents to leak into input traces or other sensitive nodes, thus degrading performance. For best
possible performance, make sure to keep the OPA928EVM as clean as possible.
The following list of best practices helps prevent the EVM from becoming contaminated:
• Always wear a fresh, clean pair of powder-free gloves or finger cots when handling the OPA928EVM.
• When handling the EVM, always hold the board by the edges.
• Avoid touching the surface of the PCB, especially near sensitive nodes or input traces.
• Be cautious when breathing, speaking, sneezing, and so on, to prevent moisture or saliva from contacting the
EVM.
• Do not allow direct airflow from cooling fans or ionizers onto the board. Moving air can blow dust and
moisture onto sensitive nodes. Additionally, airflow introduces moving charges that present as a small current
at the input.
• When not in use, place the EVM in ESD bag or other enclosure to prevent dust and other contaminants from
settling on the board.
• When configuring through-hole components in the TIA feedback path, handle the components by the wire
leads only. Avoid touching the component package.
The OPA928EVM undergoes a rigorous cleaning protocol before shipping to customers, providing femtoampere-
level performance directly out of the box. Follow the cleaning procedures detailed in Section 5 to maintain best
performance. The EVM must be cleaned per these instructions anytime the board is soldered or modified near
sensitive nodes, or if these nodes become contaminated by other means.
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2 Overview
The OPA928 is a 16-V, femtoampere input-bias-current operational amplifier (op amp) optimized for extremely
low current and high-impedance applications. The internally guarded ESD structure and special package pinout
isolates the amplifiers inputs from the output and power supply pins. The internal guard buffer is accessible
through the guard pin, allowing the guard structure to be extended to the input traces and feedback components.
The OPA928EVM is a four-layer PCB using a hybrid stack-up of Rogers 4350B and FR-4. The EVM uses
advanced guarding and shielding techniques to maintain femtoampere-level PCB layout performance. Both high-
impedance (Hi-Z) buffer (see Section 4.1) and transimpedance amplifier (TIA, see Section 4.2) configurations
are featured to evaluate the OPA928 in common application circuits. These configurations are separated into
two independent circuits on the board. By default, 0-Ω resistor Rgnd is populated on the bottom of the board,
connecting the analog ground of the two circuits.
The two OPA928 amplifiers, U1 and U2, are located on the bottom side of the EVM and are enclosed within
grounded RF shields to protect from contamination, noise, and electromagnetic interference (EMI). The top side
of the EVM features a variety of pin sockets, jumpers, and other components that provide easy configuration,
while limiting the potential for performance-degrading contamination at sensitive nodes.
2.1 Guarding and Shielding
Every insulator, including PCB material, has a finite resistance that becomes a potential path for current to
leak into the high-impedance traces. Copper guard traces are laid out around all the high-impedance input
and feedback nodes to protect the signal path from current leaking through the board material. The guard
presents a low-impedance path equipotential to the input traces. Any current leaking towards the input prefers
the low-impedance guard path over the high-impedance input path. The guard and input are of equal potential;
therefore, theoretically, no current flows between these nodes, and the input is protected.
The OPA928EVM PCB layout places the input traces and all sensitive feedback components within a perimeter
of guard copper that is then enclosed by a grounded RF shield. The solder mask has been removed from the
guard traces to reduce surface charge accumulation. Three-dimensional leakage protection is achieved through
guard copper on internal PCB layers and guard-potential via fences surrounding sensitive nodes.
High-impedance, femtoampere-level circuits are highly sensitive to electromagnetic interference (EMI). To help
reduce the effects of EMI in the OPA928EVM, three RF shields are connected to the board by surface-mounted
shield clips. These shields fully enclose all exposed high-impedance traces and reduce external noise and EMI
by shunting the noise to ground. Unless actively configuring or cleaning the EVM, keep these shields installed
to reduce EMI and prevent contaminants from entering sensitive nodes. Some user configurations require the
top shield to be removed during operation. For best EMI performance, operate the assembly within a shielded
enclosure that is connected to ground.
There are three RF shields connected to the board by surface-mounted shield clips. These shields protect from
external noise and EMI by shunting the noise to ground. The OPA928EVM is designed to fully enclose all
exposed high-impedance traces within grounded RF shields during operation. The Hi-Z circuit has one shield on
the bottom side of the EVM. The TIA circuit has two shields, one on the bottom of the EVM and one on the top.
Keep these shields installed at all times unless actively configuring or cleaning the EVM.
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3 Getting Started
The OPA928EVM is powered from a ±2.25-V to ±8-V dual supply. The high-impedance and transimpedance
amplifier circuits have separate power-supply terminals located at terminal blocks J3 and J8, respectively. The
TIA circuit has an additional terminal block (J7) requiring two independently-controlled 5-V channels to drive a
T-switch that discharges the feedback loop (see Section 4.2.2.1). The EVM can be used without this function, in
which case J7 can be ignored.
3.1 Related Documentation From Texas Instruments
Document Literature Number
OPA928 product data sheet SBOSA77
3.2 Electrostatic Discharge Caution
CAUTION
Some components on the OPA928EVM are susceptible to damage from electrostatic discharge
(ESD). Customers are advised to observe proper ESD handling precautions when unpacking and
handling the EVM, including the use of a grounded wrist strap at an approved ESD workstation.
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4 EVM Circuit Description
This section describes the circuit configurations and operation of the OPA928EVM.
4.1 High-Impedance Amplifier Circuit
The high-impedance amplifier (Hi-Z) circuit features the OPA928 in a noninverting buffer configuration designed
as a front end for high-impedance sensors. The Hi-Z circuit is located on the upper half of the EVM. The
sensitive input traces are guarded from leakage currents using the techniques described in Section 2.1.
The input path consists of CBJ70 triaxial (or triax) connector (J1) and 0-Ω series resistor (R1) connected to the
noninverting input of the OPA928 (U1). A triax connector is similar to a BNC connector, but includes a guarded
enclosure between the center (signal) conductor and the outer shield. The J1 triax connector has three index
lugs and is incompatible with standard BNC connectors.
Riso1
J2
J1
Guard 50

C1
100 nF
C2
V–
Rg
0

R3
DNP
Vref
100 nF
TP2
JP1
1 2
Triax
Guard
C3
3.3 pF
C4
DNP
0

R1
0

TP1
DNP
TP4
Vref
J4
1 2 3
V–
J3
1 2 3
V+
SH8
SH9
SH10
Rgnd
0

Hi-Z
GND
TIA
GND
TP5 TP7
TP3
V+
OPA928
+
–
C5
R2
Figure 4-1. HI-Z Circuit Schematic (Simplified)
The high-impedance input traces are surrounded by a copper guard plane driven by the OPA928 internal guard
buffer. The guard buffer tracks the potential of the amplifier input as the common-mode input voltage changes.
The guard pin of the OPA928 can be connected to the triax cable guard by installing a shunt jumper at JP1. If
the guard of the triax connector is not driven by another source, install the jumper at JP1. The amplifier and input
traces are located on the bottom of the PCB and are fully enclosed by a grounded RF shield to prevent noise
and EMI from coupling into the signal path.
The HI-Z circuit feedback loop is not sensitive to leakage currents or EMI, and has been extended out of the
shielded enclosure on the top layer for configurability. If done carefully, the feedback circuitry (Rg, R3, C4) can
be soldered and desoldered without requiring a rigorous cleaning protocol (see Section 1.1). The long feedback
traces add some parasitics to the loop; therefore, a small feedback capacitor (C3) is installed inside the shielded
enclosure to maintain stability.
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4.2 Transimpedance Amplifier Circuit
The transimpedance amplifier (TIA) circuit is located on the lower half of the OPA928EVM. This configuration
functions as a front end to convert femtoampere-level input currents into voltage outputs. The input path consists
of BNC connector (J5) and 0-Ω series resistor (R4) connected to the inverting input of the OPA928 (U2). The
inverting input can be accessed directly through pin sockets P1 and P2.
Riso2 J6
Guard 50

V+
C1
100 nF
C2
V–
RF
10 G

R9
100 k

Bias
100 nF
TP9
JP4
1
2
CF
100 pF
0

R4
0

TP8
DNP
TP10
Bias
J9
12
3
V–
J8
12 3
V+
SH5
SH6
SH7
Rgnd
0

TIA
GND
Hi-Z
GND
TP11
SH1
SH2
SH4
SH3
D1
12
J7
R13
0

3.6 V
K1
K2
JP2a
JP3a
JP2b
JP3b
P3
P1 P2
P4 P5
0

Rgb
DNP
10 k

100 pF
100 k

100 k

P6 P7
DGND DGND
R10
0

TIA
GND DGND
TP7
J5
R7
750

R8
750

OPA928
+
–
R6
Rga
C5
C9
R5
R12 R11
C8
1 pF
Figure 4-2. TIA Circuit Schematic (Simplified)
The noninverting input of the TIA is tied directly to the analog ground of the TIA circuit. The guard copper
surrounding the TIA is grounded as well, which provides very good leakage performance because the offset
voltage of a guard driver is not present between the input and guard traces. When using grounded guard traces
in a PCB layout, make sure to keep power and digital grounds separate from the guard and prevent ground
loops from occurring.
The default feedback path for the TIA consists of a 10-GΩ surface mount resistor (RF) in a resistive
transimpedance configuration. The feedback loop can be configured through the pin sockets, or by installing
and removing jumpers across certain jumper blocks. Section 4.2.1 describes how to configure the feedback path
and other functions of the TIA circuit.
The sensitive input traces and feedback components of the TIA are guarded from leakage currents using the
techniques described in Section 2.1. The amplifier, input traces, and SMD feedback components are placed
on the bottom of the PCB and are fully enclosed by a grounded RF shield to prevent noise and EMI from
coupling into the signal path. For configurability, sensitive input and feedback nodes are also exposed on the top
layer at P1, P2, JP2a, and JP3a. The top-side shield encloses these nodes and is sized to accommodate large
through-hole components inserted between the TIA pin sockets. If using through-hole components enclosed
within the top-side shield, make sure that the component and leads do not come into contact with the shield.
The TIA circuit features two additional functions described in Section 4.2.2. The first function is a low-leakage
T-switch that discharges the feedback path to reset measurements in the integrator configuration. The second
function uses the OPA928 internal guard buffer in a guarded diode limiter to protect the TIA from overcurrent
events. For a detailed description and configuration of these functions, see Section 4.2.2.
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4.2.1 Configure the TIA
The TIA is configured through the pin sockets, or by installing and removing jumpers across certain jumper
blocks. JP2 and JP3 are separated into single-pin jumper blocks JP2a/JP2b and JP3a/JP3b. Separating these
jumper blocks prevents current from leaking through the jumper block material when the jumpers are uninstalled,
and allows space for guard copper between the output and any disconnected feedback components. A special
length shunt jumper is included in the EVM to connect across JP2 or JP3. The default configuration installs the
shunt jumper at JP2, placing the 10-GΩ resistor in the feedback path.
Terminal block J7 and jumper block JP4 control the additional functions described in Section 4.2.2.
Table 4-1 lists the components and connections associated with each jumper block.
Table 4-1. TIA Jumper Block Connections
Designator Component Connection With Jumper Shunt Installed
JP2a/JP2b RF (10 GΩ) RF in series between IN– and Vout (TIA
configuration)
JP3a/JP3b CF (100 pF) CF in series between IN– and Vout
(integrator configuration)
JP4 D1 D1 in series between Vout and Guard. Limits
output voltage. See Section 4.2.2.2
J7 K1, K2 Drives K1, K2 MOS FET relays to discharge
feedback. See Section 4.2.2.1
Pin sockets allow easy configuration with through-hole components, such as photodiodes at the input or large
value resistors in the feedback path. P3 is a surface-mounted pin socket array that allows through-hole sensors
of various sizes to be easily configured at the input. P3 can be driven by the Sensor Bias terminal located at J9.
Table 4-2 lists the nodes associated with each pin socket.
Table 4-2. TIA Pin Socket Configurations
Designator Node
P1, P2 Inverting Input (U2)
P3 Sensor Bias (J9)
P4, P5 Vout (U2)
P6, P7 Analog Ground (GND)
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4.2.2 TIA Functions
The following sections provide a detailed description of the T-switch and guarded diode limiter functions, and
how to configure them.
4.2.2.1 T-Switch
The T-switch consists of two MOSFET relays (K1, K2) and one 10-kΩ resistor (R5). To drive the relays, connect
two individually controlled 5-V power-supply channels to J7. Figure 4-3 shows the timing diagram for driving
K1 and K2 in a break-before-make configuration. From Figure 4-3, t1, t2, and t4 are based on the maximum on
and off time of the relays. Follow this timing to prevent the input from being connected directly to ground, which
drives the output into the rail. The discharge time (t3) varies and must be defined by the user.
t4
tt3t
t1
t1= 1000 µs
t2= 500 µs
t2
t3=
defined
by user
t4= 200 µs
K1
K2
Figure 4-3. T-Switch Timing Diagram
• Logic low (GND) is normal TIA operation
• Logic high (5V) drives the relays, closing the T-switch and discharging the feedback loop
When the pins of J7 are not actively driven, the control logic is pulled to ground by R11 and R12, resulting in a
default logic low for normal TIA operation.
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Figure 4-4 shows the simplified T-switch circuit in an integrator configuration during normal operation (logic low).
The input current source shown is a reverse-biased photodiode. K2 is connected to the input of the integrator
and is normally open. K1 is normally closed and connects K2 and R5 to ground. When the T-switch is not active,
R5 is a 10-kΩ load to ground at the output of the amplifier. The Omron G3VM-81PR(TR05) MOS FET relay
was chosen for K2 for the high insulation resistance and low open-switch capacitance. When K1 is closed and
K2 is open, the potential across K2 is nearly 0 V, and the high insulation resistance limits any leakage current
to negligible levels. Figure 4-5 shows the functionally equivalent circuit (ignoring switch nonidealities) when the
T-switch is logic low.
Riso2
50

CF
100 pF
+
–
Bias
K2 K1
10 k

J6
DGND
DGND 750

750

Sensor
R5
R8 R7
OPA928
+
–
Figure 4-4. T-Switch Logic Low (Normal Operation)
Riso2
50

+
–
Bias
10 k

J6
CF
100 pF
Sensor
R5
OPA928
+
–
Figure 4-5. T-Switch Logic Low Equivalent Circuit (Normal Operation)
When the T-switch is logic low, the integrating capacitor, CF, accumulates charge that appears as a ramping
voltage at the amplifier output. The average current for any measurement period is calculated the following
equation.
I=CdV
dt (1)
where
• I is the average current across the measurement period.
• C is the feedback capacitance.
• dV is the change in voltage across the measurement period.
• dt is the measurement period.
In the case of a unidirectional current source at the input, the integrating capacitor continues to accumulate
charge until the amplifier output is driven into the rail and feedback is lost. To prevent the amplifier from railing,
drive the T-switch high to discharge the capacitor and reset the measurement.
Figure 4-6 shows the simplified T-switch circuit when the logic is driven high and the feedback is discharged. K1
opens and K2 closes, switching 10-kΩ resistor R5 into the feedback parallel to CF. This 10-kΩ resistor provides
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a path for CF to discharge, and the output voltage settles to the level defined by Equation 2. The settling time
depends on the output voltage and the RC time constant of the circuit.
V=IR (2)
where
• V is the output voltage.
• I is the sensor current.
• R is the resistance of the feedback network; in this case, 10 kΩ.
Riso2
50

+
–
Bias
K2 K1
10 k

J6
DGND
DGND 750

750

+
–
+
–
5V 5V
CF
100 pF
Sensor
R5
R8 R7
OPA928
+
–
Figure 4-6. T-Switch Logic High (Discharge Feedback)
Figure 4-7 shows the functionally equivalent circuit (ignoring switch nonidealities) when the T-switch is logic high.
When K2 is closed and K1 is open, switch K1 presents 100 pF of capacitance at the input of the amplifier. An
additional capacitor, C9, is populated in parallel to R5 to maintain stability when the T-switch is active.
Riso2
50

+
–
Bias
R5
10 k

J6
CF
100 pF
Sensor OPA928
+
–
Figure 4-7. T-Switch Logic High Equivalent Circuit (Discharge Feedback)
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4.2.2.2 Guarded Diode Limiter
Diode limiter circuits are commonly implemented to prevent the output voltage from exceeding a certain level.
These circuits are particularly useful in high-gain applications that are vulnerable to input transients, such
as low-level current measurements. On the OPA928EVM, the default TIA configuration is set in a gain of
10,000,000,000 V/A by the 10-GΩ feedback resistor, RF. When using ±5-V supplies, input current spikes greater
than 500 pA drive the TIA output into the rail, and feedback is lost.
A typical diode limiter protects a TIA from input overcurrent events by adding a parallel Zener diode in the
feedback path. This diode provides an alternate path for large input currents when the output voltage reaches
the reverse breakdown voltage of the diode. The reverse breakdown voltage is selected to be less than the
maximum output voltage swing of the amplifier, so that the output clips before reaching the rail, and feedback
is never lost. The downside of the typical diode limiter circuit is that the Zener diode introduces a leakage path
back into the input traces. Instead, the circuit shown in Figure 4-8 takes advantage of the OPA928 internal guard
buffer and the internal ESD protection to implement a guarded diode limiter.
The internal guard buffer maintains the input common-mode potential on both sides of the internal ESD diodes.
In a fault condition, overcurrent is directed though the ESD diodes and Zener diode, D1, to the output. During
normal operation, any leakage current through D1 is directed away from the high-impedance input traces as a
load on the guard buffer.
D1
ILEAK
IFAULT
IFAULT
10 G

1 pF
Riso
+
–
OPA928
Guard
Guard
Buffer
ESD
Diodes
VOUT
ISENSE
ISENSE
ISENSE
ISENSE
+IN
–IN
+
–
Bias
ILEAK
ILEAK
IFAULT
IFAULT
IFAULT
ILEAK
JP4
1
2
Sensor
Figure 4-8. Guarded Diode Limiter
To enable this feature on the OPA928EVM, install a shunt jumper at JP4. D1 has a reverse breakdown voltage of
3.6 V. Assuming a maximum voltage of 0.7 V across the internal ESD diodes during the fault condition, and 3.6
V across D1, by Kirchoff's law, the output is limited to a maximum of 4.3 V. To remove the limiter function from
the TIA circuit, leave the shunt at JP4 uninstalled, which takes D1 out of the feedback path.
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5 Cleaning the EVM
Follow these cleaning instructions whenever the EVM is suspected of contamination within the guard area and
performance is degraded.
The recommended cleaning procedure requires access to an ultrasonic bath. If an ultrasonic bath is not
available, a manual cleaning procedure is detailed below. The ultrasonic wash produces the best and most
consistent outcomes and is preferred over manual cleaning.
Remove all RF shields from the EVM before cleaning and follow the instructions for handling the board as
described in the Section 1.1.
5.1 Ultrasonic Wash
1. Place the EVM in the ultrasonic cleaner and fill with fresh deionized (DI) water.
2. Run the ultrasonic cleaner for 30 minutes at 85°C.
3. Remove the EVM from the ultrasonic cleaner and bake for two hours at 100°C
5.2 Manual Cleaning Procedure
1. Flush contaminants from the EVM.
a. Hold the board by the edges and flush the top and bottom using a combination of fresh isopropyl alcohol
(IPA) and fresh DI water. Focus on the input traces, guard copper, and feedback components.
2. Scrub contaminants from top side of the EVM.
a. Hold the board by the edges with the top layer facing up. Flood sensitive input and feedback areas with
fresh IPA.
b. Use a toothbrush to gently scrub for 30–60 seconds. Focus on the areas surrounding P1, P2, JP2, JP3,
SH1, and the area directly right of J1.
c. Flush the scrubbed areas with fresh DI water, tilting the board to allow runoff to flow away from the input
areas.
3. Scrub contaminants from the bottom layer TIA input.
a. Hold the board by the edges with the bottom layer facing up. Flood sensitive input and feedback areas
with fresh IPA.
b. Use a toothbrush to gently scrub for 30–60 seconds. Focus on areas surrounding U2, R4, Rf, Cf, K2, K1,
U1, R1, and all input and guard traces.
c. Flush the scrubbed areas with fresh DI water, tilting the board to allow runoff to flow away from the input
areas.
4. Remove moisture from the PCB.
a. Bake the EVM for two hours at 100°C.
6 Schematic, PCB Layout, and Bill of Materials
This section provides the OPA928EVM hardware schematics, PCB layout and bill of materials.
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6.1 EVM Schematic
Figure 6-1 shows the OPA928EVM Hi-Z schematic.
OPA928
Guard 2
Guard 7
+IN
1
-IN
8
NC
3
Out 6 V+
5
V- 4
U1
2
3 4 5 6
1
J1
CBJ70
GND HI-Z
Triax Guard
Rg
V+ HI-Z
V- HI-Z
R3
DNP
1
2 3 4 5
J2
5413631-2
GND HI-Z
V+ HI-Z
V- HI-Z
GND HI-Z
GND HI-Z
TP3
5016
TP2
5016
VREF HI-Z
VREF HI-ZGND HI-Z
TP4
5016
VOUT HI-Z
R1
HCJ0603ZT0R00
GUARD HI-Z
50V
1000pF
C5
DNP
GND HI-Z
49.9
Riso1
1
2
JP1
HTSW-102-07-G-S
GUARD HI-Z
NC HI-Z
1
2 3
J4
OSTTE030161
1
2
3
J3
OSTTE030161
GND HI-Z
R2
HCJ0603ZT0R00
TP1
5016
TP7
5016
GND HI-Z
TP5
5016
GND HI-Z
TP6
5016
GND TIA
Rgnd
100nF
50V
C1
100nF
50V
C2
100pF
50V
C4
DNP
50V
3.3pF
C3
SH8
S1711-46R
SH9
S1711-46R
GND HI-Z
GND HI-Z
SH10
S1711-46R
Figure 6-1. OPA928EVM Hi-Z Schematic
Schematic, PCB Layout, and Bill of Materials www.ti.com
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Figure 6-2 shows the OPA928EVM TIA schematic.
1
P2
0338-0-15-15-15-27-10-0
OPA928
Guard 2
Guard 7
+IN
1
-IN
8
NC
3
Out 6 V+
5
V- 4
U2
GUARD TIA
V+ TIA
V- TIA
1
2 3 4 5
J5
5413631-2
1
P4
0338-0-15-15-15-27-10-0
1
2 3 4 5
J6
5413631-2
GND TIA
1
P5
0338-0-15-15-15-27-10-0
1
P1
0338-0-15-15-15-27-10-0
1
P6
0338-0-15-15-15-27-10-0
1
P7
0338-0-15-15-15-27-10-0
GND TIA GND TIA
GND TIA
GND TIA
RF
HVF2512T1008FE
50V
1pF
C8
TP10
5016
R4
HCJ0603ZT0R00
100pF
100V
CF
50V
1000pF
C10
DNP
GND TIA
Rga
Rgb
DNP GND TIA
49.9
Riso2
1
JP2b
HTSW-101-07-G-S
1
JP2a
HTSW-101-07-G-S
1
JP3a
HTSW-101-07-G-S
1
JP3b
HTSW-101-07-G-S
V+ TIA
V- TIA
2 1
D1
PZU3.6B1A,115
VOUT TIA
NC TIA
GND TIA
GND TIA
GND TIA
1
2
4 3
K2
G3VM-81PR(TR05)
1
2
4 3
K1
G3VM-63G(TR05)
10.0k
R5
GND TIA
DGND
DGND
GND TIA
1
2
3
4
P3
399-41-004-21-300000
1
2 3
J9
OSTTE030161
Bias
Bias
750
R8
750
R7
100k
R9
GND TIA
R6
HCJ0603ZT0R00
SH1
S1711-46R
SH2
S1711-46R
GND TIA
GND TIA
TP9
5016
TP8
5016
TP11
5016
GND TIA
1
2
JP4
HTSW-102-07-G-S
100nF
50V
C6
100nF
50V
C7
50V
100pF
C9
DGND GND TIA
R10
100k
R12
SH5
S1711-46R
SH6
S1711-46R
SH3
S1711-46R
SH4
S1711-46R
SH7
S1711-46R
1
2
J7
HTSW-102-07-G-S
100k
R11
GND TIA
1
2
3
J8
OSTTE030161
R13
Figure 6-2. OPA928EVM TIA Schematic
www.ti.com Schematic, PCB Layout, and Bill of Materials
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6.2 PCB Layout
The OPA928EVM is a four-layer PCB. Figure 6-3 to Figure 6-10 show the PCB layer illustrations. The top layer
consists of the configuration circuitry and output signal traces and is poured with a solid ground plane. The
second layer routes the power supply connections. The third layer provides an additional layer of guard copper
directly above all guard copper on the bottom layer for three-dimensional guarding. The bottom layer consists of
the sensitive input traces, sensitive feedback circuitry, and guard traces and is poured with a solid ground plane.
The top and bottom solder mask layers are included to show where the solder mask was removed from guard
copper and RF shield mount areas.
Figure 6-3. Top Overlay
Figure 6-4. Top Solder Mask
Schematic, PCB Layout, and Bill of Materials www.ti.com
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Figure 6-5. Top Layer PCB Layout
Figure 6-6. Internal Power Layer PCB Layout
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Figure 6-7. Internal Guard Layer PCB Layout
Figure 6-8. Bottom Layer PCB Layout
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Figure 6-9. Bottom Solder Mask
Figure 6-10. Bottom Overlay
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6.3 Bill of Materials
Table 6-1 lists the bill of materials (BOM) used for the OPA928EVM.
Table 6-1. OPA928EVM Bill of Materials
Designator Quantity Value Description Package Reference PartNumber Manufacturer
C1, C2, C6, C7 4 100 nF 0.1 µF ±10% 50V Ceramic Capacitor X7R
0603 (1608 Metric)
0603 C0603C104K5RAC7081 KEMET
C3 1 3.3 pF CAP, CERM, 3.3 pF, 50 V, +/- 8%, C0G/
NP0, 0805
0805 08055A3R3CAT2A AVX
C8 1 1 pF CAP, CERM, 1 pF, 50 V, +/- 25%, C0G/
NP0, 0805
0805 08055A1R0CAT2A AVX
C9 1 100 pF CAP, CERM, 100 pF, 50 V, +/- 5%, C0G/
NP0, 0805
0805 CL21C101JBANNNC Samsung Electro-Mechanics
CF 1 100 pF CAP, CERM, 100 pF, 100 V, +/- 1%, C0G/
NP0, 0805
0805 08051A101FAT2A AVX
D1 1 Zener Diode 3.6 V 320 mW ±2% Surface
Mount SOD-323
SOD-323 PZU3.6B1A,115 Nexperia
H1, H2, H3, H4 4 Machine Screw, Round, #4-40 x 1/4,
Nylon, Philips panhead
Screw NY PMS 440 0025 PH B&F Fastener Supply
H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone
J1 1 Connector Jack, TH Connector Jack, TH CBJ70 Cinch Connectivity
J2, J5, J6 3 Connector, TH, BNC Right angle, 50 ohm
gold
5413631-2 5413631-1 AMP
J3, J4, J8, J9 4 Terminal Block, 3.5mm, 3x1, Tin, R/A, TH Terminal Block, 3.5mm,
3x1, TH
OSTTE030161 On-Shore Technology
J7, JP1, JP4 3 Header, 100mil, 2x1, Gold, TH Header, 100mil, 2x1, TH HTSW-102-07-G-S Samtec
JP2a, JP2b,
JP3a, JP3b
4 Header, 2.54mm, 1x1, Gold, TH Header, 2.54mm, 1x1,
TH
HTSW-101-07-G-S Samtec
K1 1 Relay, SPST-NC (1 Form B), 0.5 A, SMD SMD, 4.4x2.1x3.9mm G3VM-63G(TR05) Omron Electronic Components
K2 1 Relay, SPST-NO (1 Form A), 0.12 A, SMD SMD, 2.85x2.2mm G3VM-81PR(TR05) Omron Electronic Components
LBL1 1 Thermal Transfer Printable Labels, 0.650"
W x 0.200" H - 10,000 per roll
PCB Label 0.650 x
0.200 inch
THT-14-423-10 Brady
MP1 1 Standard RF Shield 1.0 x 2.0 x 0.75 RF_SHIELD 1.0 x 2.0 x 0.75 Fotofab
MP2, MP3 2 Standard RF Shield 1.0 x 1.5 x 0.25 RF_SHIELD 1.0 x 1.5 x 0.25 Fotofab
Schematic, PCB Layout, and Bill of Materials www.ti.com
20 OPA928 Evaluation Module SBOU282A – DECEMBER 2022 – REVISED MARCH 2023
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