
3 Setup........................................................................................................................................................................................4
3.1 Connection Diagram.......................................................................................................................................................... 4
3.2 Power Supply..................................................................................................................................................................... 4
3.3 Reference Clock.................................................................................................................................................................4
3.4 RF Output...........................................................................................................................................................................4
3.5 Programming......................................................................................................................................................................4
3.6 Evaluation Software........................................................................................................................................................... 5
4 Typical Measurement..............................................................................................................................................................6
4.1 Default Configuration......................................................................................................................................................... 6
4.2 Additional Tests.................................................................................................................................................................. 8
5 Schematic..............................................................................................................................................................................10
6 PCB Layout and Layer Stack-Up.........................................................................................................................................12
6.1 PCB Layer Stack-Up........................................................................................................................................................ 12
6.2 PCB Layout...................................................................................................................................................................... 12
7 Bill of Materials..................................................................................................................................................................... 15
8 Troubleshooting Guide.........................................................................................................................................................16
A Using Different Reference Clock........................................................................................................................................ 17
B USB2ANY Firmware Upgrade..............................................................................................................................................18
C Revision History...................................................................................................................................................................20
List of Figures
Figure 3-1. EVM Connection Diagram.........................................................................................................................................4
Figure 3-2. Select Device in TICS Pro.........................................................................................................................................5
Figure 3-3. Default Mode............................................................................................................................................................. 5
Figure 4-1. Loop Filter................................................................................................................................................................. 6
Figure 4-2. Default Output........................................................................................................................................................... 7
Figure 4-3. SYSREF Pulsed Mode Setting..................................................................................................................................8
Figure 4-4. Offset Mixing With PFDIN Pin Setting....................................................................................................................... 8
Figure 4-5. External VCO Mode Setting...................................................................................................................................... 9
Figure 4-6. Register Readback....................................................................................................................................................9
Figure 5-1. LMX2820EVM Schematic (Page 1).........................................................................................................................10
Figure 5-2. LMX2820EVM Schematic (Page 2).........................................................................................................................11
Figure 6-1. PCB Layer Stack-Up............................................................................................................................................... 12
Figure 6-2. Top Layer.................................................................................................................................................................12
Figure 6-3. RF GND Layer.........................................................................................................................................................13
Figure 6-4. Signal GND Layer................................................................................................................................................... 13
Figure 6-5. Bottom Layer........................................................................................................................................................... 14
Figure 8-1. Troubleshooting Guide............................................................................................................................................ 16
Figure B-1. Firmware Requirement........................................................................................................................................... 18
Figure B-2. Firmware Loader.....................................................................................................................................................18
Figure B-3. BSL Button..............................................................................................................................................................18
Figure B-4. Update Firmware.................................................................................................................................................... 19
Figure B-5. Firmware Update Complete.................................................................................................................................... 19
Figure B-6. USB Communications.............................................................................................................................................20
List of Tables
Table 4-1. Loop Filter Configuration.............................................................................................................................................6
Table 7-1. Bill of Materials..........................................................................................................................................................15
Table A-1. Reference Clock Input Configuration........................................................................................................................17
1 Trademarks
PLLatinum™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
Trademarks www.ti.com
2LMX2820EVM Evaluation Module SNAU246A – JUNE 2020 – REVISED JANUARY 2021
Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated