Texas Instruments TPD2S701-Q1 User manual

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TPD2S701-Q1 Evaluation Module
User's Guide
SLVUAU3–January 2017
TPD2S701-Q1 Evaluation Module
This user's guide describes the characteristics, operation, and use of the TPD2S701-Q1 USB 2.0 Data
Line Overvoltage Protection Evaluation Module (EVM). The TPD2S701-Q1 is a 2-Channel Data Line
Short-to-Battery, Short-to-VBUS, and IEC61000-4-2 ESD protection device for automotive high-speed
interfaces like USB2.0. This EVM contains multiple TPD2S701-Q1 devices in various configurations to
allow the user to test the operation of the TPD2S701-Q1 overvoltage protection and ESD protection in
their own system. This user's guide includes setup instructions, schematic diagrams, a bill of materials,
and printed circuit board layout drawings for the EVM.
Contents
1 Introduction ................................................................................................................... 2
2 Board Setup .................................................................................................................. 2
2.1 Device Information.................................................................................................. 2
2.2 Passthrough Evaluation............................................................................................ 3
2.3 Bandwidth Evaluation .............................................................................................. 4
2.4 IEC ESD Evaluation................................................................................................ 4
3 Schematics ................................................................................................................... 6
4 Layout ......................................................................................................................... 7
5 Bill of Materials............................................................................................................... 8
List of Figures
1 TPD2S701-Q1 EVM......................................................................................................... 2
2 Passthrough Evaluation Configuration.................................................................................... 3
3 Bandwidth Evaluation Configuration ...................................................................................... 4
4 ESD Evaluation Configuration ............................................................................................. 5
5 Schematic Page 1 ........................................................................................................... 6
6 Schematic Page 2 ........................................................................................................... 6
7 Schematic Page 3 ........................................................................................................... 6
8 TPD2S701-Q1 Top Layer .................................................................................................. 7
9 TPD2S701-Q1 Bottom Layer............................................................................................... 7
List of Tables
1 Bill of Materials............................................................................................................... 8

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1 Introduction
Texas Instrument’s TPD2S701-Q1 evaluation module helps designers evaluate the operation and
performance of the TPD2S701-Q1 device. The TPD2S701-Q1 contains two data line nFET switches which
ensure safe data communication while protecting the internal system circuits from any over-voltage
conditions at the VD+ and VD– pins. See Figure 1. On these pins, this device can handle over-voltage
protection up to 18-V DC. This provides sufficient protection for shorting the data lines to the car battery
as well as the USB VBUS rail. This EVM allows the user to evaluate the operation of this device in a pass-
through application, as well as to measure the ESD response and bandwidth of the device. In addition,
this EVM offer, contains the device in both the DSK and DGS package offering, so that the device can be
evaluated regardless of the preferred package option.
Figure 1. TPD2S701-Q1 EVM
2 Board Setup
The TPD2S701-Q1 EVM consists of 5 devices allowing for three different test setups.
2.1 Device Information
To power the EVM, apply 5 V to the pin labeled '+5V' on the EVM. If the user is testing a device in Mode
0, they will need to apply an additional voltage to the pin labeled 'Vref', but if testing is done in Mode 1
then the 'Vref' pin can be left unused. The functional devices modes are discussed in greater depth later,
but for detailed information see the device data sheet.
Each TPD2S701-Q1 in this EVM contains headers for enabling the device and a mode switch to enable
each mode of operation. Before using any of the devices, ensure that the particular device has a header
between the center pin and the pin labeled 'On' for the corresponding set of pins. It is recommended that
any devices not currently in use be disabled by moving the header between the center pin and the 'Off'
pin.
In addition, the EVM allows testing of each device in either functional mode 0 or functional mode 1 by
moving the switch corresponding to the device. The functional mode changes how the overvoltage set
point of the TPD2S701-Q1 is determined. In order to operate properly, the device must be power-cycled
when changing functional modes. We recommend only changing device modes while there is no power
applied to the '+5V' board power to ensure that the device works properly.
In functional mode 0 the overvoltage set point is determined by an external voltage applied to the 'Vref' pin
on the EVM. The correlation between the Vref voltage and the overvoltage set point is determined by a
formula that can be found in the device datasheet. The voltage applied to the 'Vref' pin applies to all
TPD2S701-Q1 devices on the EVM that are currently enabled and in mode 0.

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If the switch is placed in position 1, the overvoltage set point is determined instead by external resistors
and an internal voltage reference. In this mode, the device can operate with no external voltage applied to
the 'Vref' pin. The EVM is designed with external resistors to always have a 3.6 V overvoltage set point in
mode 1.
Each device also contains a yellow test point that allows the user to measure the corresponding devices
FLT output. Measure the voltage on this pin to record when the device goes into an undervoltage,
overvoltage, or thermal shutdown state to ensure that the device operates as expected.
2.2 Passthrough Evaluation
Devices U1 and U2 are in a configured to allow for USB 2.0 pass-through testing. The two devices are in
a DSK and DGS package respectively, but otherwise are functionality identical. Each has a male and
female USB port that can be plugged into any system with a USB 2.0 port to ensure that the device can
protect existing systems. Plug J9 or J13 into a USB port and then plug a peripheral into J10 or J14 to
ensure that during typical operation the TPD2S701-Q1 has no effect on standard USB operations. While
plugged in, use a probe to apply a voltage above the overvoltage setpoint to one of the data lines and
observe that the TPD2S701-Q1 isolates the system, preventing any data pass-through. After the voltage is
removed, the TPD2S701-Q1 must remove the isolation and quickly re-allow data communications. See
Figure 2.
By taking advantage of this pass-through evaluation, the user can quickly determine whether the
TPD2S701-Q1 is optimal for their existing system without requiring any board changes or non-optimal test
setups. There is an additional USB 2.0 pass-through setup at the bottom of the board that is designed for
calibration. The board and trace add some parasitics and bandwidth loss that do not reflect how the
TPD2S701-Q1 operates when designed into a system. This additional pass-through allows for calibration
to account for those and get a more accurate picture of the TPD2S701-Q1.
Figure 2. Passthrough Evaluation Configuration

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2.3 Bandwidth Evaluation
Devices U3 and U4 are configured to allow for precise bandwidth measurements. The two devices are in a
DSK and DGS package respectively, but otherwise are functionally identical. Each device has SMA
connectors on both the connector and system side of the USB 2.0 Data line pins that offer a low
attenuation way to connect a network analyzer and ensure that during typical operation the TPD2S701-Q1
capacitance and inductance do not impede signal speed past where the maximum line signal speed is. In
addition, when U3 and U4 are placed into a fault state the bandwidth can be measured to ensure that the
DC fault voltage is significantly attenuated. See Figure 3.
There is an additional bandwidth setup that is designed for calibration. The board and trace add some
parasitics and bandwidth loss that do not reflect how the TPD2S701-Q1 operates when designed into a
system. This additional pass-through allows for calibration to account for those and get a more accurate
picture of the bandwidth of the TPD2S701-Q1.
Figure 3. Bandwidth Evaluation Configuration
2.4 IEC ESD Evaluation
Device U5 is configured to be an optimal place to test the TPD2S701-Q1 IEC ESD strike response. This
configuration contains the TPD2S701-Q1 in only the DSK package as there is no difference in the
performance between the DSK and DGS packages. Test points VD+ and VD– offer strike points that can
targeted with an external ESD simulator on the protected data lines. By measuring with attenuated scope
probes on the SMB connecters labeled D+ and D– during an ESD strike, the user can capture a waveform
of what the protected system is exposed to during an ESD strike. Resistors R7 and R9 are 150-Ωresistors
in series with the ESD pulse to provide a 4x attenuation with the 50-Ωoscilloscope probe impedance. In
addition to this, to ensure that the oscilloscope is not harmed a 10x attenuation probe must be used. See
Figure 4.
For more information about Texas Instruments recommended ESD test setup, see the application report,
IEC 61000-4-x Tests for TI’s Protection Devices.

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Figure 4. ESD Evaluation Configuration

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3 Schematics
Figure 5. Schematic Page 1
Figure 6. Schematic Page 2
Figure 7. Schematic Page 3

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4 Layout
The TPD2S701-Q1 EVM is a 4 layer board of FR4 with measurements of 7.92 inches by 1.9 inches with a
thickness of 62 mil. Only the top and bottom layers are shown below, as the middle two layers are both
ground planes.
Figure 8. TPD2S701-Q1 Top Layer
Figure 9. TPD2S701-Q1 Bottom Layer

Bill of Materials www.ti.com
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5 Bill of Materials
(1) Unless otherwise noted in the Alternate PartNumber and/or Alternate Manufacturer columns, all parts may be substituted with equivalents.
Table 1. Bill of Materials
Designator Quantity Value Description Package
Reference Part Number Manufacturer Alternate PartNumber(1) Alternate Manufacturer
PCB 1 Printed Circuit Board HVL147 Any — —
C1, C8,
C13 3 1 uF CAP, CERM, 1 µF, 100 V, ±10%, X7R, AEC-Q200 Grade 1, 1206_190 1206_190 GCM31CR72A105K A03 MuRata
C2, C3,
C4, C5,
C6, C7,
C9, C10,
C11, C12
10 1 uF CAP, CERM, 1 µF, 10 V,±10%, X7S,
AEC-Q200 Grade 1, 0402 0402 GCM155C71A105KE 38D MuRata
J1 1 Standard Banana Jack, Uninsulated, 5.5
mm Keystone_575-4 575-4 Keystone
J2, J5, J6,
J7, J8 5 Header, 100 mil, 3×1, Tin, TH Header, 3 PIN, 100 mil, Tin PEC03SAAN Sullins Connector Solutions
J3, J4 2 Connector, SMB,Vertical RCP 0-4 GHz,
50 Ω, TH 236×293×236mil 131-3701-261 Emerson Network Power
J9, J11,
J13 3 Connector, USB Type A, 4POS R/A, SMD USB Type A right angle 0480371000 Molex
J10, J12,
J14 3 Connector, Receptacle, USB TYPE A, 4POS SMD USB TYPE A CONNECTOR
RECEPTACLE
4POS SMD
896-43-004-00-
000000 Mill-Max
J15, J16,
J17, J18,
J19, J20,
J21, J22,
J23, J24,
J25, J26
12 SMA Straight PCB Socket Die Cast, 50
Ω, TH SMA Straight PCB Socket Die
Cast, TH
5-1814832-1 TE Connectivity
L1, L2, L3,
L4, L5, L6,
L7, L8
8 10 nH Inductor, Multilayer, Air Core, 10 nH,
0.3A, 0.26 Ω, SMD 0402 polarized LQG15HS10NJ02D MuRata
LBL1 1 Thermal Transfer Printable Labels,
1.250" W × 0.250" H - 10,000 per roll PCB Label 1.25 × 0.250 inch THT-13-457-10 Brady
R1, R8,
R11, R17,
R19
5 0 RES, 0, 5%, 0.063 W, 0402 0402 RC0402JR-070RL Yageo America
R2, R10,
R12, R18,
R20
5 10k RES, 10 k, 5%, 0.063 W, 0402 0402 CRCW040210K0JN
ED Vishay-Dale

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Table 1. Bill of Materials (continued)
Designator Quantity Value Description Package
Reference Part Number Manufacturer Alternate PartNumber(1) Alternate Manufacturer
R3, R13,
R14, R21,
R22
5 140k RES, 140 k, 1%, 0.1 W, AEC-Q200
Grade 0, 0402 0402 ERJ-2RKF1403X Panasonic
R4, R15,
R16, R23,
R24
5 24.9k RES, 24.9 k, 1%, 0.063 W, 0402 0402 CRCW040224K9FK
ED Vishay-Dale
R5, R6 2 45.3 RES, 45.3, 1%, 0.1 W, 0603 0603 CRCW060345R3FK
EA Vishay-Dale
R7, R9 2 150 RES, 150, 1%, 0.1 W, 0603 0603 RC0603FR-07150RL Yageo America
S1, S2, S3,
S4, S5 5 SLIDE SWITCH DPDT .1A, SMT SWITCH, 5.4×2.5×3.9 mm CAS-220TA Copal Electronics
SH-J2, SH-
J5, SH-J6,
SH-J7, SH-
J8
5 Shunt, 2.54 mm, Gold, Black Shunt, 2.54 mm,
Black 60900213421 Wurth Elektronik
T1, T2, T3,
T4 4 SMT Common Mode Choke mcf12102g900 Taiyo Yuden None None
TP1, TP4,
TP5, TP6,
TP7
5 Test Point, Compact, Yellow, TH Yellow Compact
Testpoint 5009 Keystone
TP2 1 Test Point, Compact, Red, TH Red Compact
Testpoint 5005 Keystone
TP3 1 Orange Test Point, Compact, Orange, TH Orange Compact
Testpoint 5008 Keystone
U1, U3, U5 3 Automotive USB 2-Ch Date Line Short-
to-Battery, Short-to-VBUS, and IEC
ESD pritection, DSK0010A
DSK0010A TPD2S701QDSKRQ
1Texas Instruments Texas Instruments
U2, U4 2 Automotive USB 2-Ch Date Line Short-
to-Battery, Short-to-VBUS, and IEC
ESD pritection, DGS0010A
DGS0010A TPD2S701QDGSRQ
1Texas Instruments Texas Instruments
FID1, FID2,
FID3 0 Fiducial mark. There is nothing to buy or mount Fiducial N/A N/A

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