Texas Instruments TPS23755EVM-894 User manual

User’s Guide
TPS23755EVM-894 Evaluation Module
ABSTRACT
This user’s guide describes the TPS23755 evaluation module (EVM). The TPS23755 evaluation module
(TPS23755EVM-894) contains evaluation and reference circuitry for the TPS23755 device. The TPS23755
device is an IEEE 802.3at Type 1 compliant, powered-device (PD) controller and power supply controller
optimized for primary side regulation flyback converter topologies. TPS23755EVM-894 is targeted for a 12-V
diode-rectified high efficiency 13-W PD solution.
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Features............................................................................................................................................................................. 2
1.2 Applications........................................................................................................................................................................2
2 Electrical Specifications........................................................................................................................................................ 2
3 Description.............................................................................................................................................................................. 2
4 Schematic................................................................................................................................................................................4
5 General Configuration and Description................................................................................................................................5
5.1 Physical Access................................................................................................................................................................. 5
6 TPS23755EVM-894 Performance Data.................................................................................................................................. 5
6.1 Startup to PSE and DCDC Startup.................................................................................................................................... 5
6.2 Transient Response........................................................................................................................................................... 6
6.3 Efficiency............................................................................................................................................................................8
6.4 Load Regulation................................................................................................................................................................. 8
6.5 Recovery from VOUT Short............................................................................................................................................... 9
6.6 Slew Rate Adjust................................................................................................................................................................9
7 EVM Assembly Drawings and Layout Guidelines............................................................................................................. 12
7.1 PCB Drawings..................................................................................................................................................................12
7.2 Layout Guidelines............................................................................................................................................................ 16
7.3 EMI Containment............................................................................................................................................................. 17
8 Bill of Materials..................................................................................................................................................................... 18
Revision History.......................................................................................................................................................................23
List of Figures
Figure 4-1. TPS23755EVM-894 Schematic.................................................................................................................................4
Figure 6-1. Startup Response When Connected to a PoE PSE (TPS23861) and DCDC Startup.............................................. 6
Figure 6-2. Transient Response from 100 mA to 1 A for a 48-V Input.........................................................................................7
Figure 6-3. Efficiency of the TPS23755EVM-894........................................................................................................................ 8
Figure 6-4. TPS23755EVM-894 Load Regulation....................................................................................................................... 8
Figure 6-5. DCDC Recovery From Output Short......................................................................................................................... 9
Figure 6-6. SRF = 0 Ω..................................................................................................................................................................9
Figure 6-7. SRF = 100 Ω............................................................................................................................................................10
Figure 6-8. SRR = 0 Ω............................................................................................................................................................... 10
Figure 6-9. SRR = 15 Ω............................................................................................................................................................. 11
Figure 7-1. Top-Side Component Placement.............................................................................................................................12
Figure 7-2. Layer 2 Routing....................................................................................................................................................... 13
Figure 7-3. Layer 3 Routing....................................................................................................................................................... 14
Figure 7-4. Bottom-Side Routing............................................................................................................................................... 15
List of Tables
Table 2-1. TPS23755EVM-894 Electrical and Performance Specifications at 25°C....................................................................2
Table 5-1. Connector Functionality.............................................................................................................................................. 5
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Table 5-2. Test Points.................................................................................................................................................................. 5
Table 8-1. TPS23755EVM-894 BOM.........................................................................................................................................18
Trademarks
All trademarks are the property of their respective owners.
1 Introduction
The TPS23755EVM-894 allows reference circuitry evaluation of the TPS23755 device. It contains input and
output power connectors and an array of onboard test points for circuit evaluation.
1.1 Features
• IEEE802.3at Type 1 compliant PoE PD
• Class 3 12V/1A Primary Side Regulated CCM Flyback
• Advanced Startup
• Programmable Slew Rate and Frequency Dithering for EMI Reduction
• Secondary-side adapter priority control with smooth transition
1.2 Applications
• IP cameras
• Access Points
• Point-of-Sale
• Barcode Readers
• IP Phones
• Wireless LAN – wireless access points
2 Electrical Specifications
Table 2-1. TPS23755EVM-894 Electrical and Performance Specifications at 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER INTERFACE
Input voltage Applied to the power pins of connectors J1 37 57 V
Applied to the power pins of connectors J5 12 V
Input UVLO, POE input J2 Rising input voltage 36 V
Falling input voltage 30
Detection voltage At device terminals 2.7 10.1 V
Classification voltage At device terminals 14.5 20.5 V
Classification current RCLASS = 45.3 Ω 26.5 29.3 mA
Inrush current-limit 140 mA
Operating current-limit 550 mA
DC-TO-DC CONVERTER
Output voltage VIN = 48 V, ILOAD ≤ ILOAD (max) 12 V
Output current 37 V ≤ VIN ≤ 57 V 1 A
Output ripple voltage peak-to-peak VIN = 48 V, ILOAD = 1 A 50 mV
Efficiency, end-to-end
VIN = 48 V, ILOAD= 100 mA 78
%VIN = 48 V, ILOAD = 500 mA 86
VIN = 48 V, ILOAD = 1 A 87
Switching frequency 250 kHz
3 Description
The TPS23755EVM-894 enables full evaluation of the TPS23755 device. Refer to the schematic shown in
Figure 4-1. Ethernet power is applied from J1 and is dropped to the bridge rectifier (D1, D2). The Power over
Ethernet (PoE) transformer needed to transfer power or data is T1 . The Bob Smith Terminations help balance
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the Ethernet cable impedance and are critical for ESD and EMI or EMC performance. The EMI or EMC filter and
transient protection for the TPS23755 device are at the output of the diode bridge.
Input power can also be applied at J5 from a DC source when power at J1 is not present.
The TPS23755 (U1) PD and DC-to-DC converter circuitry is shown in Figure 4-1. R17 provides the detection
signature and R20 provides the classification (class 3) signature. The switched side of the PD controller is to the
right of U1. The TPS23755 RTN pin provides inrush limited turn on and charge of the bulk capacitor, C12.
The DC-to-DC converter is a high-efficiency diode rectified primary-side regulated flyback converter.
Output voltage feedback is provided with R16 and R21 on the bias winding. R14 provides a means for error
injection to measure the frequency response of the converter.
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4 Schematic
Figure 4-1. TPS23755EVM-894 Schematic
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5 General Configuration and Description
5.1 Physical Access
Table 5-1 lists the EVM connector functionality. Table 5-2 describes the test point availability and jumper
functionality.
Table 5-1. Connector Functionality
Connector Label Description
J1 PWR+DATA PoE input; connect to PSE power and data source.
J2 DATA Ethernet data passthrough; connect to downstream Ethernet device.
J3 Output Output connector to loadx.
J5 Adapter Input DC-to-DC converter input bypassing the PoE converter; connect a 12-V adapter.
J4 LED Jump J4 to visually indicate the output voltage.
J6 FREQ Jump to 'Fixed' for fixed frequency. Jump to 'Dither' to enable spread spectrum dithering.
Table 5-2. Test Points
Test Point Label Description
TP1 BS Bob Smith Termination
TP2, TP7 PGND Primary ground
TP3 VOUT Output voltage
TP4 VCC Bias voltage
TP5 GND Secondary ground
TP6 VSS PoE input return ground
TP8 VPD Input voltage
6 TPS23755EVM-894 Performance Data
6.1 Startup to PSE and DCDC Startup
Figure 6-1 shows the startup response of the TPS23755EVM-894.
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IIN
VDD-VSS
RTN-VSS
Figure 6-1. Startup Response When Connected to a PoE PSE (TPS23861) and DCDC Startup
6.2 Transient Response
Figure 6-2 shows the transient response of the TPS23755EVM-894.
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Figure 6-2. Transient Response from 100 mA to 1 A for a 48-V Input
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6.3 Efficiency
Figure 6-3 shows the efficiency of the TPS23755EVM-894.
Output Current (A)
Efficiency
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
D001D001
PoE
DC-DC
Figure 6-3. Efficiency of the TPS23755EVM-894
6.4 Load Regulation
Output Current (A)
Output Voltage (V)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
11.5
12
12.5
13
13.5
14
D002
Figure 6-4. TPS23755EVM-894 Load Regulation
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6.5 Recovery from VOUT Short
Figure 6-5. DCDC Recovery From Output Short
6.6 Slew Rate Adjust
Figure 6-6. SRF = 0 Ω
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Figure 6-7. SRF = 100 Ω
Figure 6-8. SRR = 0 Ω
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Figure 6-9. SRR = 15 Ω
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7 EVM Assembly Drawings and Layout Guidelines
7.1 PCB Drawings
Figure 7-1 to Figure 7-4 show the component placement and layout of the TPS23755EVM-894.
Figure 7-1. Top-Side Component Placement
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Figure 7-2. Layer 2 Routing
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Figure 7-3. Layer 3 Routing
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Figure 7-4. Bottom-Side Routing
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7.2 Layout Guidelines
The layout of the PoE frontend should follow power and EMI or ESD best-practice guidelines. A basic set of
recommendations includes:
• Pin 22 of the TPS23755 is omitted from the IC to ensure high voltage clearance from Pin 24 (DRAIN).
Therefore, the Pin 22 footprint should be removed when laying out the TPS23755.
• It is recommended having at least 8 vias (VSS) connecting the exposed thermal pad through a top layer
plane (2 oz copper recommended) to a bottom VSS plane (2 oz copper recommended) to help with thermal
dissipation.
• The Pin 24 of the TPS23755 should be near the power transformer and the current sense resistor should be
close to Pin 1 of the TPS23755 to minimize the primary loop.
• Parts placement must be driven by power flow in a point-to-point manner; RJ-45, Ethernet transformer, diode
bridges, TVS and 0.1-μF capacitor, and TPS23755 converter input bulk capacitor.
• Make all leads as short as possible with wide power traces and paired signal and return.
• No crossovers of signals from one part of the flow to another are allowed.
• Spacing consistent with safety standards like IEC60950 must be observed between the 48-V input voltage
rails and between the input and an isolated converter output.
• Use large copper fills and traces on SMT power-dissipating devices, and use wide traces or overlay copper
fills in the power path.
The DC-to-DC converter layout benefits from basic rules such as:
• Having at least 4 vias (VDD) near the power transformer pin connected to VDD through multiple layer planes
to help with thermal dissipation of the power transformer.
• Having at least 6 vias (secondary ground) near the power transformer pin connected to secondary ground
through multiple layer planes to help with thermal dissipation of the power transformer.
• Pair signals to reduce emissions and noise, especially the paths that carry high-current pulses, which include
the power semiconductors and magnetics.
• Minimize the trace length of high current power semiconductors and magnetic components.
• Use the ground plane for the switching currents carefully.
• Keep the high-current and high-voltage switching away from low-level sensing circuits including those outside
the power supply.
• Proper spacing around the high-voltage sections of the converter.
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7.3 EMI Containment
• Use compact loops for dv/dt and di/dt circuit paths (power loops and gate drives).
• Use minimal, yet thermally adequate, copper areas for heat sinking of components tied to switching nodes
(minimize exposed radiating surface). Hide copper associated with switching nodes under shielded
magnetics, where possible.
• Use copper ground planes (possible stitching) and top-layer copper floods (surround circuitry with ground
floods)
• Use a 4-layer PCB, if economically feasible (for better grounding).
• Minimize the amount of copper area associated with input traces (to minimize radiated pickup).
• Heat sink the quiet side of components instead of the switching side, where possible (like the output side of
inductor).
• Use Bob Smith terminations, Bob Smith EFT capacitor, and Bob Smith plane. Use Bob Smith plane as a
ground shield on input side of PCB (creating a phantom or literal earth ground).
• Use LC filter at DC-to-DC input.
• Dampen high-frequency ringing on all switching nodes, if present (allow for possible snubbers).
• Control rise times with gate-drive resistors and possibly snubbers.
• Switching frequency considerations.
• Use of EMI bridge capacitor across isolation boundary (isolated topologies).
• Observe the polarity dot on inductors (embed noisy end).
• Use of ferrite beads on input (allow for possible use of beads or 0-Ω resistors).
• Maintain physical separation between input-related circuitry and power circuitry (use ferrite beads as
boundary line).
• Balance efficiency versus acceptable noise margin.
• Possible use of common-mode inductors.
• Possible use of integrated RJ-45 jacks (shielded with internal transformer and Bob Smith terminations).
• End-product enclosure considerations (shielding).
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8 Bill of Materials
Table 8-1. TPS23755EVM-894 BOM
Designator Quantity Value Description PackageReference PartNumber Manufacturer Alternate
PartNumber
Alternate
Manufacturer
!PCB1 1 Printed Circuit
Board PWR894 Any - -
C1, C2, C14 3 1000 pF
CAP, CERM, 1000
pF, 100 V, +/- 10%,
X7R, 0603
0603 GRM188R72A10
2KA01D MuRata
C3, C4 2 1000 pF
CAP, CERM, 1000
pF, 2000 V, +/-
10%, X7R, 1812
1812 GR443QR73D10
2KW01L MuRata
C5, C6, C29, C30 4 0.01 uF
CAP, CERM, 0.01
µF, 100 V, +/- 10%,
X7R, 0603
0603 GRM188R72A10
3KA01D MuRata
C7, C24, C31, C32 4 2200 pF
CAP, CERM, 2200
pF, 2000 V, +/-
10%, X7R, 1812
1812 C4532X7R3D222
K130KA TDK
C8, C10 2 22 uF
CAP, CERM, 22 µF,
25 V,+/- 20%, X5R,
1812
1812 C4532X5R1E226
M250KA TDK
C9, C22 2 1 uF
CAP, CERM, 1 µF,
25 V, +/- 10%, X7R,
0805
0805 GRM21BR71E10
5KA99L MuRata
C12 1 10 uF
CAP, AL, 10 µF,
100 V, +/- 20%,
AEC-Q200 Grade
3, SMD
SMT Radial E EEE-2AA100UP Panasonic
C13 1 680 pF
CAP, CERM, 680
pF, 100 V, +/- 10%,
X7R, 0603
0603 06031C681KAT2
AAVX
C15, C16 2 2.2 uF
CAP, CERM, 2.2
µF, 100 V, +/- 10%,
X7R, 1210
1210 GRM32ER72A22
5KA35L MuRata
C17, C20 2 0.1 uF
CAP, CERM, 0.1
µF, 100 V, +/- 10%,
X7R, 0805
0805 C2012X7R2A104
K125AA TDK
C18 1 2.00 k
RES, 2.00 k, 1%,
0.125 W, AEC-
Q200 Grade 0,
0603
0603 RNCP0603FTD2
K00
Stackpole
Electronics Inc
C19 1 0.1 uF
CAP, CERM, 0.1
µF, 25 V,+/- 10%,
X7R, 0603
0603 06033C104KAT2
AAVX
Bill of Materials www.ti.com
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Table 8-1. TPS23755EVM-894 BOM (continued)
Designator Quantity Value Description PackageReference PartNumber Manufacturer Alternate
PartNumber
Alternate
Manufacturer
C21 1 100 pF
CAP, CERM, 100
pF, 50 V,+/- 5%,
C0G/NP0, 0402
0402 885012005061 Wurth Elektronik
C23 1 0.01 uF
CAP, CERM, 0.01
µF, 100 V,+/- 20%,
X7R, 0603
0603 06031C103MAT2
AAVX
C25 1 2200 pF
CAP, CERM, 2200
pF, 50 V, +/- 10%,
X7R, 0603
0603 GRM188R71H22
2KA01D MuRata
C26 1 0.1 uF
CAP, CERM, 0.1
µF, 25 V, +/- 10%,
X7R, 0603
0603 C1608X7R1E104
K080AA TDK
C27, C28 2 0.1 uF
CAP, CERM, 0.1
µF, 50 V,+/- 10%,
X7R, 0603
0603 06035C104KAT2
AAVX
D1, D2 2 400 V
Diode, Switching-
Bridge, 400 V, 0.8
A, MiniDIP
MiniDIP HD04-T Diodes Inc.
D3 1 60 V Diode, Schottky, 60
V, 3 A, PowerDI5 PowerDI5 PDS360-13 Diodes Inc.
D4, D5, D11 3 100 V
Diode, Switching,
100 V, 0.2 A,
SOD-123
SOD-123 MMSD4148T1G ON Semiconductor
D6 1 Yellow LED, Yellow, SMD LED_0603 150060YS75000 Wurth Elektronik
D7 1 200 V
Diode, Ultrafast,
200 V, 1 A,
SOD-123
SOD-123 RF071M2S Rohm
D8 1 30 V Diode, Schottky, 30
V, 2 A, SMB SMB B230-13-F Diodes Inc.
D9 1 58 V Diode, TVS, Uni, 58
V, 400 W, SMA SMA SMAJ58A Diodes Inc.
D10 1 6.8 V Diode, Zener, 6.8 V,
500 mW, SOD-123 SOD-123 MMSZ5235B-7-F Diodes Inc.
D13 1 6.2 V Diode, Zener, 6.2 V,
500 mW, SOD-123 SOD-123 MMSZ5234B-7-F Diodes Inc.
H1, H2, H3, H4 4
Bumpon,
Hemisphere, 0.375
X 0.235, Black
Black Bumpon SJ61A2 3M
J1, J2 2 RJ-45, No LED, tab
up, R/A, TH 16.26 x 14.54 x 15.75 1-406541-1 TE Connectivity
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Table 8-1. TPS23755EVM-894 BOM (continued)
Designator Quantity Value Description PackageReference PartNumber Manufacturer Alternate
PartNumber
Alternate
Manufacturer
J3, J5 2
Terminal Block, 6 A,
3.5-mm Pitch, 2-
Pos, TH
7.0 x 8.2 x 6.5 mm ED555/2DS On-Shore
Technology
J4 1
Header, 2.54 mm, 2
x 1, Gold, R/A,
SMT
Header, 2.54 mm, 2 x
1, R/A, SMT 0878980204 Molex
J6 1 Header, 100 mil, 3
x 1, Gold, TH 3 x 1 Header TSW-103-07-G-S Samtec
L1, L2, L5, L7 4 30 ohm
1.5 A Ferrite Bead,
30 ohm @ 100
MHz, SMD
0805 MMZ2012R300A TDK MMZ2012R300AT0
00
L3 1 3.3 uH
Inductor, Drum
Core, Ferrite, 3.3
µH, 1.6 A, 0.14
ohm, SMD
ME3220 ME3220-332MLB Coilcraft
Q1 1 60 V MOSFET, N-CH, 60
V, 115 A, SOT-23 SOT-23 2N7002 Fairchild Semiconductor
None
R1, R2, R3, R4,
R32, R33 6 75.0 RES, 75.0 ohm, 1%, 0.1 W, 0603 0603 CRCW060375R0 FKEA Vishay-Dale
R5 1 24 RES, 24, 5%, 0.25
W, 1206 1206 CRCW120624R0 JNEA Vishay-Dale
R6 1 10.0 RES, 10.0, 1%,
0.125 W, 0805 0805 RC0805FR-0710 RL Yageo America
R7 1 4.02 k RES, 4.02 k, 1%,
0.1 W, 0603 0603 CRCW06034K02 FKEA Vishay-Dale
R8 1 39 k RES, 39k ohm, 5%,
0.125 W, 0805 0805 CRCW080539K0 JNEA Vishay-Dale
R9 1 8.06 k RES, 8.06 k, 1%,
0.1 W, 0603 0603 CRCW06038K06 FKEA Vishay-Dale
R10 1 100
RES, 100, 5%, 1 W,
AEC-Q200 Grade
0, 2512
2512 CRCW2512100R
JNEG Vishay-Dale
R11 1 11.5 k RES, 11.5 k, 1%,
0.1 W, 0603 0603 CRCW060311K5 FKEA Vishay-Dale
R12 1 10.0 k RES, 10.0 k, 1%,
0.1 W, 0603 0603 CRCW060310K0 FKEA Vishay-Dale
R13, R15 2 0.91 RES, 0.91, 1%,
0.25 W, 0805 0805 CRM0805-FX- R910ELF Bourns
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