Texas Instruments TPS54KC23EVM User manual

User's Guide
TPS54KC23EVM Step-Down Converter Evaluation Module
ABSTRACT
This user’s guide contains information for the TPS54KC23EVM evaluation module and the TPS54KC23
DC/DC converter. Also included are the performance characteristics, schematic, and bill of materials for the
TPS54KC23EVM.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Background........................................................................................................................................................................ 3
1.2 Before You Begin............................................................................................................................................................... 3
1.3 Performance Characteristics Summary............................................................................................................................. 4
2 Configurations and Modifications.........................................................................................................................................5
2.1 Output Voltage................................................................................................................................................................... 5
2.2 Frequency and Operation Mode Setting (MSEL Pin).........................................................................................................5
3 Test Setup and Results.......................................................................................................................................................... 6
3.1 Input/Output Connections.................................................................................................................................................. 7
3.2 Efficiency............................................................................................................................................................................9
3.3 Output Voltage Regulation............................................................................................................................................... 10
3.4 Load Transient and Loop Response................................................................................................................................ 11
3.5 Output Voltage Ripple...................................................................................................................................................... 12
3.6 Start-up and Shutdown with EN....................................................................................................................................... 13
3.7 Thermal Performance...................................................................................................................................................... 13
4 Board Layout.........................................................................................................................................................................14
4.1 Layout.............................................................................................................................................................................. 14
5 Schematic and Bill of Materials...........................................................................................................................................17
5.1 Schematic........................................................................................................................................................................ 17
5.2 Bill of Materials.................................................................................................................................................................19
List of Figures
Figure 3-1. TPS54KC23EVM.......................................................................................................................................................6
Figure 3-2. U1 Efficiency – Skip-Mode (Default)..........................................................................................................................9
Figure 3-3. U2 Efficiency – Skip-Mode (Default)..........................................................................................................................9
Figure 3-4. U2 Efficiency - FCCM vs Skip-Mode......................................................................................................................... 9
Figure 3-5. U2 Efficiency – FCCM............................................................................................................................................... 9
Figure 3-6. U1 Load Regulation.................................................................................................................................................10
Figure 3-7. U1 Line Regulation..................................................................................................................................................10
Figure 3-8. U2 Load Regulation.................................................................................................................................................10
Figure 3-9. U2 Line Regulation..................................................................................................................................................10
Figure 3-10. U1 Transient Response......................................................................................................................................... 11
Figure 3-11. U2 Transient Response......................................................................................................................................... 11
Figure 3-12. U1 Bode Plot – 15-A Load.....................................................................................................................................11
Figure 3-13. U2 Bode Plot – 15-A Load.....................................................................................................................................11
Figure 3-14. U1 Output Ripple – 10-mA Load, Skip-Mode........................................................................................................ 12
Figure 3-15. U1 Output Ripple – 30-A Load.............................................................................................................................. 12
Figure 3-16. U2 Output Ripple – 10-mA Load, Skip-Mode........................................................................................................ 12
Figure 3-17. U2 Output Ripple – 30-A Load.............................................................................................................................. 12
Figure 3-18. U2 Start-up with EN – 30-A Load.......................................................................................................................... 13
Figure 3-19. U2 Shutdown with EN – 30-A Load.......................................................................................................................13
Figure 3-20. U1 Thermal Performance – 30-A Load and U2 off................................................................................................13
Figure 3-21. U2 Thermal Performance – 30-A Load and U1 off................................................................................................13
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Figure 4-1. Top-Side Composite View....................................................................................................................................... 14
Figure 4-2. Bottom-Side Composite View (Viewed From Bottom).............................................................................................14
Figure 4-3. Top Layer Layout.....................................................................................................................................................15
Figure 4-4. Mid Layer 1 Layout..................................................................................................................................................15
Figure 4-5. Mid Layer 2 Layout..................................................................................................................................................15
Figure 4-6. Mid Layer 3 Layout..................................................................................................................................................15
Figure 4-7. Mid Layer 4 Layout..................................................................................................................................................16
Figure 4-8. Bottom Layer Layout............................................................................................................................................... 16
Figure 5-1. U1 Schematic.......................................................................................................................................................... 17
Figure 5-2. U2 Schematic.......................................................................................................................................................... 18
List of Tables
Table 1-1. Input Voltage and Output Current Summary...............................................................................................................3
Table 1-2. TPS54KC23EVM Small Size (U1) Performance Characteristics Summary............................................................... 4
Table 1-3. TPS54KC23EVM High Efficiency (U2) Performance Characteristics Summary.........................................................4
Table 2-1. MSEL Pin Selection.................................................................................................................................................... 5
Table 3-1. Connectors and Jumpers............................................................................................................................................7
Table 3-2. Test Points.................................................................................................................................................................. 7
Table 3-3. Efficiency Measurement Test Points........................................................................................................................... 9
Table 5-1. TPS54KC23EVM Bill of Materials.............................................................................................................................19
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
1.1 Background
The TPS54KC23 DC/DC converter are synchronous buck converters designed to provide up to a 30-A output.
Rated input voltage and output current range for the evaluation module are given in Table 1-1.
The high-side and low-side MOSFETs are incorporated inside the TPS54KC23 package along with the gate-
drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS54KC23 to achieve high
efficiencies and helps to keep the junction temperature low at the rated output current. An external divider allows
for an adjustable output voltage. The TPS54KC23 MSEL pin provides selectable switching frequency, light load
operation mode, and internal compensation. Current limit setting and soft start configuration are set via ILIM and
SS pins respectively. Lastly, the TPS54KC23 includes an enable pin and a power good output which can be
used for sequencing multiple regulators.
This evaluation module includes two designs with the TPS54KC23. The first design (U1) is designed to
demonstrate the small printed-circuit-board areas that can be achieved when designing with the TPS54KC23
regulator. The small area design fits within 250 mm2. The second design (U2) is designed to demonstrate the
high efficiency that can be achieved when designing with the TPS54KC23 regulator. The second design also
includes jumpers that can be used to easily evaluate the features of the TPS54KC23.
Table 1-1. Input Voltage and Output Current Summary
EVM RELATED IC INPUT VOLTAGE RANGE OUTPUT CURRENT
RANGE
TPS54KC23EVM U1 VIN = 8 V to 16 V 0 A to 30 A
TPS54KC23EVM U2 VIN = 4.5 V to 16 V 0 A to 30 A
1.2 Before You Begin
The following warnings and cautions are noted for the safety of anyone using or working close to the
TPS54KC23EVM. Observe all safety precautions.
WARNING
The TPS54KC23EVM can become hot during operation due to dissipation of power
in some operating conditions. Avoid contact with the board. Follow all applicable
safety procedures applicable to your laboratory.
WARNING
The circuit module has signal traces, components, and component leads on the bottom of the board
and can result in exposed voltages, hot surfaces or sharp edges. Do not reach under the board
during operation.
CAUTION
Some power supplies can be damaged by application of external voltages. If using more than
1 power supply, check your equipment requirements and use blocking diodes or other isolation
techniques, as needed, to prevent damage to your equipment.
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1.3 Performance Characteristics Summary
A summary of the TPS54KC23EVM performance characteristics is provided in Table 1-2 and Table 1-3. The
TPS54KC23EVM is designed and tested for VIN = 8 V to 16 V for U1 and VIN = 4.5 V to 16 V for U2.
Characteristics are given for an input voltage of VIN = 12 V and output voltage of 0.8 V, unless otherwise
specified. The ambient temperature is room temperature (20°C to 25°C) for all measurements, unless otherwise
noted.
Table 1-2. TPS54KC23EVM Small Size (U1) Performance Characteristics Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 8 12 16 V
Input current VIN = 8 V, IO = 30 A 3.9 A
VIN start voltage Set by EN pin resistor divider 7.18 V
VIN stop voltage Set by EN pin resistor divider 5.98 V
Output voltage setpoint 0.802 V
Output current range VIN = 8 V to 16 V 0 30 A
Line and load regulation VIN = 8 V to 16 V, IOUT = 0 A to 30 A ±0.31 %
Load transient response
IOUT = 5 A to 20 A Voltage change -15 mV
Recovery time 68 µs
IOUT = 5 A to 20 A Voltage change 20 mV
Recovery time 64 µs
Input ripple voltage IOUT = 30 A 864 mVPP
Output ripple voltage IOUT = 30 A 20 mVPP
Output rise time Set by SS pin capacitor 139 μs
Current limit Set by ILIM pin resistor 30.6 A
Switching frequency (fSW) Set by MSEL pin resistor 1400 kHz
Peak efficiency IOUT = 15 A 83.3 %
IC case temperature IOUT = 30 A, 15-minute soak 128 °C
Table 1-3. TPS54KC23EVM High Efficiency (U2) Performance Characteristics Summary
SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT
VIN voltage range 4.5 12 16 V
Input current VIN = 4.5 V, IOUT = 30 A 6.5 A
VIN start voltage Set by EN pin resistor divider 3.84 V
VIN stop voltage Set by EN pin resistor divider 3.20 V
Output voltage setpoint 0.802 V
Output current range VIN = 4.5 V to 16 V 0 30 A
Line and load regulation VIN = 4.5 V to 16 V, IOUT = 0 A to 30 A ±0.4%
Load transient response
IOUT = 5 A to 20 A Voltage change –4 mV
Recovery time 54 µs
IOUT = 5 A to 20 A Voltage change 4 mV
Recovery time 55 µs
Input ripple voltage IOUT = 30 A 472 mVPP
Output ripple voltage IOUT = 30 A 4.8 mVPP
Output rise time Set by SS pin capacitor 944 μs
Current limit Set by ILIM pin resistor 30.6 A
Switching frequency (fSW) Set by MSEL pin resistor, J8 short pins 3 and 4 800 kHz
Peak efficiency IOUT = 8 A 89.1 %
IC case temperature IOUT = 30 A, 15-minute soak 97 °C
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2 Configurations and Modifications
These evaluation modules are designed to provide access to the features of the TPS54KC23. The U2 design
provides jumpers for testing different configurations. Jumper selections must be made prior to enabling the
TPS54KC23.
If a desired configuration is not available, then some modifications can be made to this module. When
modifications are made to the components on the EVM, the internal compensation option selected with the
MSEL pin resistor needs to be changed. Changes to the fSW, output voltage, output inductor, and output
capacitors can require a change in the compensation. TPS54KC23 data sheet equations or WEBENCH can be
used to calculate the output capacitor value, compensation, fSW, and inductance. Verify that all components have
sufficient voltage and current ratings.
2.1 Output Voltage
In the U1 design, the output voltage is set by the resistor divider network of R2 (RFBT) and R6 (RFBB). R6 is fixed
at 8.25 kΩ to set the FB divider current at approximately 61 µA. The output voltage is set to 0.8V as default.
To change the output voltage of the EVM, the value of resistor R2 must change. Changing the value of R2
can change the output voltage above the 0.5-V reference voltage (VREF). The value of R2 for a specific output
voltage can be calculated using Equation 1.
In the U2 design, the output voltage is set by the resistor divider network of R15 (RFBT) and R12 (RFBB). R15 is
fixed at 8.25 kΩ to set the FB divider current at approximately 61 µA. The output voltage is set to 0.8V as default.
To change the output voltage of the EVM, the value of resistor R12 must change. Changing the value of R12
can change the output voltage above the 0.5-V reference voltage (VREF). The value of R12 for a specific output
voltage can be calculated using Equation 1. After changing R12, the feed forward capacitor (C51) also needs to
be changed.
RFBT =RFBB ×
VOUT
VREF
−1(1)
2.2 Frequency and Operation Mode Setting (MSEL Pin)
In the U2 design, jumper J8 can change between MSEL pin selections shown in Table 2-1. If the desired option
is unavailable, then change one of the resistors to the value that sets the desired option.
In the U1 design, change the MSEL resistor to the value which sets the desired option.
Table 2-1. MSEL Pin Selection
JUMPER SETTING MSEL RESISTOR (kΩ) OPERATION UNDER
LIGHT LOAD
SWITCHING
FREQUENCY (fSW) (kHz) RAMP
1 to 2 pin shorted 0 FCCM 800 RAMP4
3 to 4 pin shorted 4.99 FCCM 800 RAMP3
5 to 6 pin shorted 7.50 FCCM 800 RAMP2
7 to 8 pin shorted 10.5 FCCM 800 RAMP1
9 to 10 pin shorted 56.2 Skip-mode 800 RAMP4
11 to 12 pin shorted 64.9 Skip-mode 800 RAMP3
13 to 14 pin shorted(1) 75.0 Skip-mode 800 RAMP2
15 to 16 pin shorted 86.6 Skip-mode 800 RAMP1
(1) Default Setting
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3 Test Setup and Results
This section describes how to properly connect, set up, and use the TPS54KC23EVM evaluation module.
The section also includes test results typical for the evaluation module and covers efficiency, output voltage
regulation, load transients, loop response, output ripple, input ripple, start-up, and current limit modes.
Measurements are taken with the following conditions unless otherwise noted.
• 12-V input
• Room temperature (20°C to 25°C)
• U1 with the default setting output voltage of 0.802 V, switching frequency of 1400 kHz, and maximum current
limit setting
• U2 with the default setting output voltage of 0.802 V, switching frequency of 800 kHz, and maximum current
limit setting
• With the other converter disabled
Figure 3-1. TPS54KC23EVM
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3.1 Input/Output Connections
The TPS54KC23EVM is provided with input connectors, output connectors, and test points as shown in Table
3-1 and Table 3-2.
To support the minimum input voltage with the full rated load on both outputs with the default EVM, a power
supply capable of supplying greater than 10 A must be connected to the VIN and PGND terminal blocks (J1 for
U1, and J3 for U2) through a pair of 18-AWG wires or better.
For U1, the load must be connected to J2 and for U2, the load must be connected to J4. A pair of 10-AWG wires
or better must be used for each connection. With the maximum current limit setting, the maximum load current
capability is near 33 A before the TPS54KC23 goes into current limit. Wire lengths must be minimized to reduce
losses in the wires.
Table 3-1. Connectors and Jumpers
REFERENCE
DESIGNATOR NAME RELATED IC FUNCTION
J1 VIN1 U1 VIN screw terminal to connect input voltage (see Table 1-1 for VIN range)
J2 VOUT1 U1 VOUT screw terminal to connect load to output
J3 VIN2 U2 VIN screw terminal to connect input voltage (see Table 1-1 for VIN range)
J4 VOUT2 U2 VOUT screw terminal to connect load to output
J5 EN2 U2
EN pin selection header:
Open = (EN pin shorted to AGND)
Short = (EN pin connected to VIN pin through resistor divider)
J8 - U2 MSEL selection header. Use shunt to select MSEL resistor (see Table 2-1 for
MSEL pin selection)
Table 3-2. Test Points
REFERENCE
DESIGNATOR NAME RELATED IC FUNCTION
TP1 VIN1 U1 VIN test point. Use this for efficiency measurements.
TP2 SW1 U1 SW node test point
TP3 VOUT1 U1 VOUT test point
TP4 REG_GND1 U1 PGND test point. Use this for efficiency measurements.
TP5 VCC1 U1 VCC test point
TP6 PG1 U1 PGOOD output test point (pulled up to VCC pin through a 10-kΩ resistor)
TP7 BODE1 U1 Test point between voltage divider network and output voltage. Used for Bode
plot measurements.
TP8 REG_VOUT1 U1 VOUT test point. Use this for efficiency, output regulation, and bode plot
measurements.
TP9 PGND1 U1 PGND test point. Use this for efficiency measurements.
TP10 AGND1 U1 AGND test point
TP11 VOUT_U1 U1
SMB connector to measure output voltage. When using this test point, set the
scope for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is
created.
TP12 VIN2 U2 VIN test point
TP13 VOUT2 U2 VOUT test point
TP14 SW2 U2 SW test point
TP15 EN2 U2 EN test point
TP16 VCC2 U2 VCC test point
TP17 REG_GND2 U2 PGND test point. Use this for efficiency measurements.
TP18 PG2 U2 PGOOD output test point (pulled up to VCC pin through a 10-kΩ resistor)
TP19 BODE2 U2 Test point between voltage divider network and output voltage. Used for Bode
plot measurements.
TP20 REG_VOUT2 U2 VOUT test point. Use this for efficiency, output regulation, and bode plot
measurements.
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Table 3-2. Test Points (continued)
REFERENCE
DESIGNATOR NAME RELATED IC FUNCTION
TP21 SS2 U2 SS test point
TP22 ILIM2 U2 ILIM test point
TP23 MSEL2 U2 MSEL test point
TP24 PGND2 U2 PGND test point. Use this for efficiency measurements.
TP25 AGND2 U2 AGND test point
TP28 SW_U2 U2
SMB connector to measure SW node. When using this test point, set the scope
for 50-Ω termination. The combination of 50-Ω termination and 450-Ω series
resistance creates a 10:1 attenuation.
TP29 VOUT_U2 U2
SMB connector to measure output voltage. When using this test point, set the
scope for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is
created.
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3.2 Efficiency
Figure 3-2 through Figure 3-5 show the efficiency for both designs on the TPS54KC23EVM. The test points
listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of
PCB parasitic power loss to the measured power loss.
The following are some additional test setup considerations to minimize external sources of power dissipation.
• Disable the other regulator to avoid including the switching quiescent current of the other regulator in the
efficiency measurement.
• Do not measure the SW pin of U2 with TP28 while measuring the efficiency of U2. Measuring the SW pin
with this test point loads this node with 500 Ω and the efficiency measurement includes the power lost in this
external resistance.
Table 3-3. Efficiency Measurement Test Points
RELATED IC TEST POINT NAME REFERENCE
DESIGNATOR FUNCTION
U1
VIN1 TP1 Input voltage test point connected near pins of U1
PGND1 TP9 PGND reference test point for input voltage
REG_VOUT1 TP8 Output voltage test point near output inductor of U1
REG_GND1 TP4 PGND reference test point for output voltage
U2
VIN2 TP12 Input voltage test point connected near pins of U2
PGND2 TP24 PGND reference test point for input voltage
REG_VOUT2 TP20 Output voltage test point near output inductor of U2
REG_GND2 TP17 PGND reference test point for output voltage
Output Current (A)
Efficiency (%)
0 5 10 15 20 25 30
60
65
70
75
80
85
90
95
100
Vin = 12 V
Vin = 8 V
Vin = 16 V
Figure 3-2. U1 Efficiency – Skip-Mode (Default)
Output Current (A)
Efficiency (%)
0 5 10 15 20 25 30
60
65
70
75
80
85
90
95
100
Vin = 12 V
Vin = 8 V
Vin = 16 V
Figure 3-3. U2 Efficiency – Skip-Mode (Default)
Output Current (A)
Efficiency (%)
0.001 0.005 0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 3030
0
10
20
30
40
50
60
70
80
90
100
FCCM, Vin = 12V
FCCM, Vin = 8V
FCCM, Vin = 16V
Skip-mode, Vin = 12V
Skip-mode, Vin = 8V
Skip-mode, Vin = 16V
Figure 3-4. U2 Efficiency - FCCM vs Skip-Mode
Output Current (A)
Efficiency (%)
0 5 10 15 20 25 30
60
65
70
75
80
85
90
95
100
Vin = 12 V
Vin = 8 V
Vin = 16 V
Figure 3-5. U2 Efficiency – FCCM
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3.3 Output Voltage Regulation
Figure 3-6 and Figure 3-7 show the load and line regulation for U1. Figure 3-8 and Figure 3-9 show the load and
line regulation for U2.
Output Current (A)
Output Voltage (V)
0 5 10 15 20 25 30
0.793
0.794
0.795
0.796
0.797
0.798
0.799
0.8
0.801
Vin = 12 V
Vin = 8 V
Vin = 16 V
Figure 3-6. U1 Load Regulation
Input Voltage (V)
Output Voltage (V)
8 9 10 11 12 13 14 15 16
0.793
0.794
0.795
0.796
0.797
0.798
0.799
0.8
Iout = 15 A
Iout = 30 A
Figure 3-7. U1 Line Regulation
Output Current (A)
Output Voltage (V)
0 5 10 15 20 25 30
0.796
0.797
0.798
0.799
0.8
0.801
0.802
0.803
Vin = 12 V
Vin = 8 V
Vin = 16 V
Figure 3-8. U2 Load Regulation
Input Voltage (V)
Output Voltage (V)
4 5 6 7 8 9 10 11 12 13 14 15 16
0.795
0.796
0.797
0.798
0.799
0.8
0.801
0.802
Iout = 15 A
Iout = 30 A
Figure 3-9. U2 Line Regulation
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3.4 Load Transient and Loop Response
Figure 3-10 and Figure 3-11 show the response to load transients for both designs. The current step is from 5 A
to 20 A and the current step slew rate is 1 A/µs. An electronic load is used to provide a DC 5-A load and the load
transient circuit on the EVM is used to provide a 15-A step. The VOUT voltage is measured using TP11 for U1
and TP29 for U2.
Figure 3-12 and Figure 3-13 show the loop characteristics for both designs. Gain and phase plots are shown for
VIN voltage of 12 V and a 15-A load.
Figure 3-10. U1 Transient Response Figure 3-11. U2 Transient Response
Frequency (Hz)
Gain (dB)
Phase (°)
1000 2000 5000 10000 20000 50000 100000200000 1000000
-80 -200
-60 -150
-40 -100
-20 -50
0 0
20 50
40 100
60 150
80 200
Gain
Phase
Figure 3-12. U1 Bode Plot – 15-A Load
Frequency (Hz)
Gain (dB)
Phase (°)
1000 2000 5000 10000 20000 50000 100000200000 1000000
-80 -200
-60 -150
-40 -100
-20 -50
0 0
20 50
40 100
60 150
80 200
Gain
Phase
Figure 3-13. U2 Bode Plot – 15-A Load
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3.5 Output Voltage Ripple
Figure 3-14 through Figure 3-17 show the TPS54KC23EVM output voltage ripple. The load currents are 10-mA
and 30 A. VIN = 12 V. The VOUT voltage is measured using TP11 for U1 and TP29 for U2.
Figure 3-14. U1 Output Ripple – 10-mA Load, Skip-
Mode
Figure 3-15. U1 Output Ripple – 30-A Load
Figure 3-16. U2 Output Ripple – 10-mA Load, Skip-
Mode
Figure 3-17. U2 Output Ripple – 30-A Load
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3.6 Start-up and Shutdown with EN
Figure 3-18 and Figure 3-19 show the start-up and shutdown waveforms for U2 with EN. In Figure 3-18, the
input voltage is initially applied and the output is inhibited by pulling EN to GND using an external function
generator. When the EN voltage is increased above the enable-threshold voltage, the start-up sequence begins
and the output voltage ramps up to the externally set value. In Figure 3-19, the external function generator pulls
EN to ground and the TPS54KC23 shuts down.
Figure 3-18. U2 Start-up with EN – 30-A Load Figure 3-19. U2 Shutdown with EN – 30-A Load
3.7 Thermal Performance
Figure 3-20 through Figure 3-21 show the temperature rise of the TPS54KC23 ICs at full 30-A load. Figure 3-20
and Figure 3-21 have only one TPS54KC23 on and loaded. A minimum of 10 minutes for soak time was used
before taking each measurement.
Figure 3-20. U1 Thermal Performance – 30-A Load
and U2 off
Figure 3-21. U2 Thermal Performance – 30-A Load
and U1 off
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4 Board Layout
This section provides a description of the TPS54KC23EVM board layout and layer illustrations.
4.1 Layout
The board layout for the TPS54KC23EVM is shown in Figure 4-1 through Figure 4-8. The top-side layer of the
EVM is laid out in a manner typical of a user application. The top, bottom, and internal layers are 2-oz. copper.
The small size U1 circuit takes up an area of only approximately 250 mm2 as shown on the silkscreen.
Figure 4-1. Top-Side Composite View Figure 4-2. Bottom-Side Composite View (Viewed
From Bottom)
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Figure 4-3. Top Layer Layout Figure 4-4. Mid Layer 1 Layout
Figure 4-5. Mid Layer 2 Layout Figure 4-6. Mid Layer 3 Layout
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Figure 4-7. Mid Layer 4 Layout Figure 4-8. Bottom Layer Layout
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5 Schematic and Bill of Materials
This section presents the TPS54KC23EVM schematic and bill of materials.
5.1 Schematic
Figure 5-1 is the schematic for U1. Figure 5-2 is the schematic for U2.
4V
47µF
C9
4V
47µF
C10
4V
47µF
C11
0.1uF
C12
0.1uF
C6
0.1uF
C7
+
330uF
C1
0.18uH
L1
1µF
C5
1µF
C4
10µF
C3
10µF
C2
4V
47µF
C8
16V
1uF
C14 10.0
R3
NT3
10nF
C15
182k
R8
4.32k
R7
4.99k
R2
8.25k
R6
NT2
NT1
1
2
TP11
VOUT_U1
49.9
R10
VOUT1
VOUT Mu lti-purpos e 1:1 Measure ment
50 -oh m s e ries term / 50-ohm ca ble / Scope Te rm. = 1Mohm
Output: 0.8 V at 30 A
TP3
VOUT1
TP9
P GND1
Input: 8 V to 16 V
10.0k
R4
TP1
VIN1
453k
R1
100k
R5 TP 6
PG1 TP 7
BODE1
TP8
RE G_ VOUT1
TP2
SW1
J _P GND1
D30 82-05
5.10
R9
560pF
100V
C16
SW1
SW1
TP10
AGND1
1
2
2A
1A
J1
VIN1
1
2
2A
1A
J2
VOUT1
VOUT1
1.4MHz Skip-Mode
TP5
VCC1
TP4
RE G_GND1
0.01uF
C13
EN
1
ILIM
12
MSEL
11
PG
10
VCC
7
VIN
3
VIN
9
AGND 2
BOOT 5
FB 14
GOSNS 13
PGND 16
SW 6
SS
15
PGND 4
PGND 8
TPS54KC23RZRR
U1
Figure 5-1. U1 Schematic
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4V
47µF
C41
4V
47µF
C42
4V
47µF
C43
4V
47µF
C44
4V
47µF
C45
0.1uF
C48
0.1uF
C22
0.1uF
C23
10µF
C19
10µF
C18
+
330uF
C32 +
6.3V
220uF
C46 +
6.3V
220uF
C47
0.15uH
L2
1µF
C21
1µF
C20
10µF
C33
10µF
C17
4V
47µF
C40
10µF
C35
10µF
C34
16V
1uF
C50
0.1uF
C38
0.1uF
C39
1µF
C37
1µF
C36
4V
47µF
C24
4V
47µF
C25
4V
47µF
C26
4V
47µF
C27
4V
47µF
C28
4V
47µF
C29 +
6.3V
220uF
C30 +
6.3V
220uF
C31
10.0
R13
NT6
200k
R11
68nF
C52
4.32k
R17
4.99k
R12
8.25k
R15
15pF
C51
VOUT2
MSEL P in S e ttings :
1-2 : FCCM 800kHz RAMP 4 (2.1 x)
3-4 : FCCM 800kHz RAMP 3 (1.6 x)
5-6 : FCCM 800kHz RAMP 2 (1.3 x)
7-8 : FCC M 800 kHz RAMP1 (1x)
9-1 0: Skip-m ode 800kHz RAMP4 (2.1x)
11-12: S kip-mode 800kHz RAMP3 (1.6x)
13 -14: S kip-mode 80 0kHz RAMP 2 (1.3x)
15 -16: S kip-mode 80 0kHz RAMP 1 (1x) (Default)
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
J8
P EC 08 DAAN
4.99k
R20
7.50k
R21
10.5k
R22
56.2k
R23
64.9k
R24
75.0k
R25
86.6k
R26
NT4
1
2
TP28
S W_U2 1
2
TP29
VOUT_U2
49.9
R34
VOUT2
66.5k
R33
453
R29
SW2
S W High F re que ncy 10:1 Meas ureme n t
45 0ohm / SMB to 50-o hm ca ble / S cope Te rm . = 50ohm
VOUT Mu lti-p urpose 1:1 Meas ureme n t
50 -ohm series term / 50 -ohm ca ble / Scope Te rm. = 1Mohm
Input: 4.5 V to 16 V Output: 0.8 V at 30 A
TP24
P GND2
TP13
VOUT2
TP19
BODE2
TP20
REG_VOUT2
TP15
EN2
TP21
SS 2 TP22
ILIM2 TP 23
MSEL2
TP18
PG2
TP14
SW2
0
R19
J _P G ND2
D30 82 -05
5.10
R18
560pF
100V
C53
SW2
SW2
TP12
VIN2
10.0k
R14
100k
R16
TP25
AGND2
TP16
VCC2
1
2
2A
1A
J3
VIN2
1
2
2A
1A
J4
VOUT2
TP17
REG_GND2
1
3 5 6
4 2
7 9 10
8 1211 1413 1615 1817 2019
J9
HS E C8-11 0-0 1-S -DV-A
VOUT2
0.01uF
C49
NT5
EN
1
ILIM
12
MSEL
11
PG
10
VCC
7
VIN
3
VIN
9
AGND 2
BOOT 5
FB 14
GOSNS 13
PGND 16
SW 6
SS
15
PGND 4
PGND 8
TPS54KC23RZRR
U2
1 2
J5
Figure 5-2. U2 Schematic
Schematic and Bill of Materials www.ti.com
18 TPS54KC23EVM Step-Down Converter Evaluation Module SLVUCU8 – JANUARY 2024
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5.2 Bill of Materials
Table 5-1 details the bill of materials for the TPS54KC23EVM.
Table 5-1. TPS54KC23EVM Bill of Materials
DESIGNATOR QTY VALUE DESCRIPTION PACKAGE REFERENCE PART NUMBER MANUFACTURER
!PCB1 1 Printed Circuit Board BSR225 Any
C1, C32 2 330µF Cap Aluminum Polymer 330uF 25V
20% Solder Cylindrical 19m Ohm
2325mA 2000 hr 125°C T/R
SMT_CAP_8MM3_8MM3 A768KS337M1ELAE019 KEMET
C2, C3, C17, C18, C19,
C33, C34, C35
8 10uF CAP, CERM, 10 µF, 25 V,+/- 10%,
X7R, AEC-Q200 Grade 1, 1206
1206 CGA5L1X7R1E106K160A
E
TDK
C4, C5, C20, C36 4 1uF CAP, CERM, 1 µF, 25 V,+/- 20%,
X5R, 0402
402 GRM155R61E105MA12D MuRata
C6, C7, C12, C22, C38,
C48
6 0.1uF CAP, CERM, 0.1 uF, 35 V, +/- 10%,
X5R, 0402
402 GMK105BJ104KV-F Taiyo Yuden
C8, C9, C10, C11, C24,
C25, C26, C27, C28, C29,
C40, C41, C42, C43, C44,
C45
16 47uF CAP, CERM, 47 µF, 4 V,+/- 20%,
X6S, 0805
805 GRM21BC80G476ME15L MuRata
C14, C50 2 1uF CAP, CERM, 1 uF, 16 V, +/- 10%,
X6S, 0402
402 C1005X6S1C105K050BC TDK
C15 1 0.01uF CAP, CERM, 0.01 uF, 25 V, +/-
10%, X7R, 0402
402 GCM155R71E103KA37D MuRata
C52 1 0.068uF CAP, CERM, 0.068 uF, 10 V, +/-
10%, X7R, 0402
402 GRM155R71A683KA01D MuRata
FID1, FID2, FID3, FID4 4 Fiducial mark. There is nothing to
buy or mount.
N/A N/A N/A
H1, H2, H3, H4 4 Bumpon, Hemisphere, 0.44 X 0.20,
Clear
Transparent Bumpon SJ-5303 (CLEAR) 3M
J1, J2, J3, J4 4 Terminal Block, 60A, 10.16mm
Pitch, 2-Pos, TH
21.8x30x19 mm 399100102 Molex
J5 1 Header, 100mil, 2x1, Gold, TH 2x1 Header TSW-102-07-G-S Samtec
J8 1 Header, 2.54 mm, 8x2, Tin, Vertical,
TH
Header, 2.54 mm, 8x2, TH PEC08DAAN Sullins Connector Solutions
J9 1 Card Edge Socket, 0.8mm, 10x2,
SMT
Card Edge Socket, 0.8mm,
10x2, SMT
HSEC8-110-01-S-DV-A Samtec
J_PGND1, J_PGND2 2 1mm Uninsulated Shorting Plug,
10.16mm spacing, TH
Shorting Plug, 10.16mm
spacing, TH
D3082-05 Harwin
L1 1 0.18uH 180 nH Shielded Molded Inductor
25.3 A 1.2mOhm Max Nonstandard
SMT_IND_6MM51_6MM71 XGL6030-181MEC Coilcraft
L2 1 0.15uH 150 nH Shielded Drum Core,
Wirewound Inductor 65 A
0.15mOhm Nonstandard
SMT2_10MM2_8MM1 7443082015A Wurth Electronics
LBL1 1 Thermal Transfer Printable Labels,
0.650" W x 0.200" H - 10,000 per
roll
PCB Label 0.650 x 0.200 inch THT-14-423-10 Brady
R1 1 453k RES, 453 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402
402 CRCW0402453KFKED Vishay-Dale
R2, R12 2 4.99k RES, 4.99 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402
402 CRCW04024K99FKED Vishay-Dale
R3, R13 2 10 RES, 10.0, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402
402 CRCW040210R0FKED Vishay-Dale
R4, R14 2 10.0k RES, 10.0 k, 1%, 0.1 W, 0402 402 ERJ-2RKF1002X Panasonic
R5, R16 2 100k RES, 100 k, 1%, 0.1 W, 0402 402 ERJ-2RKF1003X Panasonic
R6, R15 2 8.25k RES, 8.25 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402
402 CRCW04028K25FKED Vishay-Dale
R7, R17 2 4.32k RES, 4.32 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402
402 CRCW04024K32FKED Vishay-Dale
R8 1 182k RES, 182 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402
402 CRCW0402182KFKED Vishay-Dale
R10, R34 2 49.9 RES, 49.9, 1%, 0.1 W, 0603 603 RC0603FR-0749R9L Yageo
R11 1 200k RES, 200 k, 1%, 0.063 W, AEC-
Q200 Grade 0, 0402
402 CRCW0402200KFKED Vishay-Dale
R19 1 0 RES, 0, 5%, 0.1 W, AEC-Q200
Grade 0, 0603
603 CRCW06030000Z0EA Vishay-Dale
R20 1 4.99k RES, 4.99 k, 0.1%, 0.1 W, 0603 603 RT0603BRD074K99L Yageo America
R21 1 7.50k RES, 7.50 k, 1%, 0.1 W, 0603 603 ERJ-3EKF7501V Panasonic
R22 1 10.5k RES, 10.5 k, 0.1%, 0.1 W, 0603 603 RG1608P-1052-B-T5 Susumu Co Ltd
R23 1 56.2k RES, 56.2 k, 1%, 0.1 W, 0603 603 RC0603FR-0756K2L Yageo
www.ti.com Schematic and Bill of Materials
SLVUCU8 – JANUARY 2024
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Table 5-1. TPS54KC23EVM Bill of Materials (continued)
DESIGNATOR QTY VALUE DESCRIPTION PACKAGE REFERENCE PART NUMBER MANUFACTURER
R24 1 64.9k RES, 64.9 k, 1%, 0.1 W, 0603 603 RC0603FR-0764K9L Yageo
R25 1 75.0k RES, 75.0 k, 1%, 0.1 W, 0603 603 RC0603FR-0775KL Yageo
R26 1 86.6k RES, 86.6 k, 1%, 0.1 W, 0603 603 RC0603FR-0786K6L Yageo
R29 1 453 RES, 453, 1%, 0.1 W, 0603 603 RC0603FR-07453RL Yageo
R33 1 66.5k RES, 66.5 k, 1%, 0.1 W, 0603 603 RC0603FR-0766K5L Yageo
SH-J1, SH-J2 2 1x2 Shunt, 100mil, Gold plated, Black Shunt SNT-100-BK-G Samtec
TP1, TP2, TP3, TP5, TP6,
TP7, TP8, TP12, TP13,
TP14, TP15, TP16, TP18,
TP19, TP20, TP21, TP22,
TP23
18 Test Point, Multipurpose, Red, TH Red Multipurpose Test point 5010 Keystone
TP4, TP9, TP10, TP17,
TP24, TP25
6 Test Point, Multipurpose, Black, TH Black Multipurpose Test point 5011 Keystone Electronics
TP11, TP28, TP29 3 Connector, Receptacle, 50 ohm, TH SMB Connector SMBR004D00 JAE Electronics
U1, U2 2 4-V to 16-V Input, 25-A, Remote
Sense, D-CAP4 Synchronous Buck
Converter
WQFN-FCRLF16 TPS54KC23RZRR Texas Instruments
C13 0 0.01uF CAP, CERM, 0.01 uF, 16 V, +/-
10%, X5R, 0402
402 GRM155R61C103KA01D MuRata
C16, C53 0 560pF CAP, CERM, 560 pF, 100 V, +/-
10%, X7R, 0603
603 GRM188R72A561KA01D MuRata
C21, C37 0 1uF CAP, CERM, 1 µF, 25 V,+/- 20%,
X5R, 0402
402 GRM155R61E105MA12D MuRata
C23, C39 0 0.1uF CAP, CERM, 0.1 uF, 35 V, +/- 10%,
X5R, 0402
402 GMK105BJ104KV-F Taiyo Yuden
C30, C31, C46, C47 0 220µF Molded Tantalum Polymer
Capacitor 220uF 20% 6.3V life
1000Hours SMD 2917
2917 6TCF220M5L Panasonic
C49 0 0.01uF CAP, CERM, 0.01 uF, 50 V, +/-
10%, X7R, AEC-Q200 Grade 1,
0402
402 CGA2B3X7R1H103K050
BB
TDK
C51 0 15pF CAP, CERM, 15 pF, 50 V,+/- 5%,
C0G/NP0, AEC-Q200 Grade 1,
0402
402 CGA2B2C0G1H150J050
BA
TDK
R9, R18 0 5.1 RES, 5.10, 1%, 0.5 W, 1210 1210 RC1210FR-075R1L Yageo
Schematic and Bill of Materials www.ti.com
20 TPS54KC23EVM Step-Down Converter Evaluation Module SLVUCU8 – JANUARY 2024
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