Texas instruments Tps54kc23evm User manual

User's Guide

TPS54KC23EVM Step-Down Converter Evaluation Module

ABSTRACT

This user’s guide contains information for the TPS54KC23EVM evaluation module and the TPS54KC23

DC/DC converter. Also included are the performance characteristics, schematic, and bill of materials for the

TPS54KC23EVM.

Table of Contents

1 Introduction.............................................................................................................................................................................3

1.1 Background........................................................................................................................................................................ 3

1.2 Before You Begin............................................................................................................................................................... 3

1.3 Performance Characteristics Summary............................................................................................................................. 4

2 Configurations and Modifications.........................................................................................................................................5

2.1 Output Voltage................................................................................................................................................................... 5

2.2 Frequency and Operation Mode Setting (MSEL Pin).........................................................................................................5

3 Test Setup and Results.......................................................................................................................................................... 6

3.1 Input/Output Connections.................................................................................................................................................. 7

3.2 Efficiency............................................................................................................................................................................9

3.3 Output Voltage Regulation............................................................................................................................................... 10

3.4 Load Transient and Loop Response................................................................................................................................ 11

3.5 Output Voltage Ripple...................................................................................................................................................... 12

3.6 Start-up and Shutdown with EN....................................................................................................................................... 13

3.7 Thermal Performance...................................................................................................................................................... 13

4 Board Layout.........................................................................................................................................................................14

4.1 Layout.............................................................................................................................................................................. 14

5 Schematic and Bill of Materials...........................................................................................................................................17

5.1 Schematic........................................................................................................................................................................ 17

5.2 Bill of Materials.................................................................................................................................................................19

List of Figures

Figure 3-1. TPS54KC23EVM.......................................................................................................................................................6

Figure 3-2. U1 Efficiency – Skip-Mode (Default)..........................................................................................................................9

Figure 3-3. U2 Efficiency – Skip-Mode (Default)..........................................................................................................................9

Figure 3-4. U2 Efficiency - FCCM vs Skip-Mode......................................................................................................................... 9

Figure 3-5. U2 Efficiency – FCCM............................................................................................................................................... 9

Figure 3-6. U1 Load Regulation.................................................................................................................................................10

Figure 3-7. U1 Line Regulation..................................................................................................................................................10

Figure 3-8. U2 Load Regulation.................................................................................................................................................10

Figure 3-9. U2 Line Regulation..................................................................................................................................................10

Figure 3-10. U1 Transient Response......................................................................................................................................... 11

Figure 3-11. U2 Transient Response......................................................................................................................................... 11

Figure 3-12. U1 Bode Plot – 15-A Load.....................................................................................................................................11

Figure 3-13. U2 Bode Plot – 15-A Load.....................................................................................................................................11

Figure 3-14. U1 Output Ripple – 10-mA Load, Skip-Mode........................................................................................................ 12

Figure 3-15. U1 Output Ripple – 30-A Load.............................................................................................................................. 12

Figure 3-16. U2 Output Ripple – 10-mA Load, Skip-Mode........................................................................................................ 12

Figure 3-17. U2 Output Ripple – 30-A Load.............................................................................................................................. 12

Figure 3-18. U2 Start-up with EN – 30-A Load.......................................................................................................................... 13

Figure 3-19. U2 Shutdown with EN – 30-A Load.......................................................................................................................13

Figure 3-20. U1 Thermal Performance – 30-A Load and U2 off................................................................................................13

Figure 3-21. U2 Thermal Performance – 30-A Load and U1 off................................................................................................13

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TPS54KC23EVM Step-Down Converter Evaluation Module 1

Figure 4-1. Top-Side Composite View....................................................................................................................................... 14

Figure 4-2. Bottom-Side Composite View (Viewed From Bottom).............................................................................................14

Figure 4-3. Top Layer Layout.....................................................................................................................................................15

Figure 4-4. Mid Layer 1 Layout..................................................................................................................................................15

Figure 4-5. Mid Layer 2 Layout..................................................................................................................................................15

Figure 4-6. Mid Layer 3 Layout..................................................................................................................................................15

Figure 4-7. Mid Layer 4 Layout..................................................................................................................................................16

Figure 4-8. Bottom Layer Layout............................................................................................................................................... 16

Figure 5-1. U1 Schematic.......................................................................................................................................................... 17

Figure 5-2. U2 Schematic.......................................................................................................................................................... 18

List of Tables

Table 1-1. Input Voltage and Output Current Summary...............................................................................................................3

Table 1-2. TPS54KC23EVM Small Size (U1) Performance Characteristics Summary............................................................... 4

Table 1-3. TPS54KC23EVM High Efficiency (U2) Performance Characteristics Summary.........................................................4

Table 2-1. MSEL Pin Selection.................................................................................................................................................... 5

Table 3-1. Connectors and Jumpers............................................................................................................................................7

Table 3-2. Test Points.................................................................................................................................................................. 7

Table 3-3. Efficiency Measurement Test Points........................................................................................................................... 9

Table 5-1. TPS54KC23EVM Bill of Materials.............................................................................................................................19

Trademarks

All trademarks are the property of their respective owners.

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1 Introduction

1.1 Background

The TPS54KC23 DC/DC converter are synchronous buck converters designed to provide up to a 30-A output.

Rated input voltage and output current range for the evaluation module are given in Table 1-1.

The high-side and low-side MOSFETs are incorporated inside the TPS54KC23 package along with the gate-

drive circuitry. The low drain-to-source on-resistance of the MOSFET allows the TPS54KC23 to achieve high

efficiencies and helps to keep the junction temperature low at the rated output current. An external divider allows

for an adjustable output voltage. The TPS54KC23 MSEL pin provides selectable switching frequency, light load

operation mode, and internal compensation. Current limit setting and soft start configuration are set via ILIM and

SS pins respectively. Lastly, the TPS54KC23 includes an enable pin and a power good output which can be

used for sequencing multiple regulators.

This evaluation module includes two designs with the TPS54KC23. The first design (U1) is designed to

demonstrate the small printed-circuit-board areas that can be achieved when designing with the TPS54KC23

regulator. The small area design fits within 250 mm2. The second design (U2) is designed to demonstrate the

high efficiency that can be achieved when designing with the TPS54KC23 regulator. The second design also

includes jumpers that can be used to easily evaluate the features of the TPS54KC23.

Table 1-1. Input Voltage and Output Current Summary

EVM RELATED IC INPUT VOLTAGE RANGE OUTPUT CURRENT

RANGE

TPS54KC23EVM U1 VIN = 8 V to 16 V 0 A to 30 A

TPS54KC23EVM U2 VIN = 4.5 V to 16 V 0 A to 30 A

1.2 Before You Begin

The following warnings and cautions are noted for the safety of anyone using or working close to the

TPS54KC23EVM. Observe all safety precautions.

WARNING

The TPS54KC23EVM can become hot during operation due to dissipation of power

in some operating conditions. Avoid contact with the board. Follow all applicable

safety procedures applicable to your laboratory.

WARNING

The circuit module has signal traces, components, and component leads on the bottom of the board

and can result in exposed voltages, hot surfaces or sharp edges. Do not reach under the board

during operation.

CAUTION

Some power supplies can be damaged by application of external voltages. If using more than

1 power supply, check your equipment requirements and use blocking diodes or other isolation

techniques, as needed, to prevent damage to your equipment.

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1.3 Performance Characteristics Summary

A summary of the TPS54KC23EVM performance characteristics is provided in Table 1-2 and Table 1-3. The

TPS54KC23EVM is designed and tested for VIN = 8 V to 16 V for U1 and VIN = 4.5 V to 16 V for U2.

Characteristics are given for an input voltage of VIN = 12 V and output voltage of 0.8 V, unless otherwise

specified. The ambient temperature is room temperature (20°C to 25°C) for all measurements, unless otherwise

noted.

Table 1-2. TPS54KC23EVM Small Size (U1) Performance Characteristics Summary

SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT

VIN voltage range 8 12 16 V

Input current VIN = 8 V, IO = 30 A 3.9 A

VIN start voltage Set by EN pin resistor divider 7.18 V

VIN stop voltage Set by EN pin resistor divider 5.98 V

Output voltage setpoint 0.802 V

Output current range VIN = 8 V to 16 V 0 30 A

Line and load regulation VIN = 8 V to 16 V, IOUT = 0 A to 30 A ±0.31 %

Load transient response

IOUT = 5 A to 20 A Voltage change -15 mV

Recovery time 68 µs

IOUT = 5 A to 20 A Voltage change 20 mV

Recovery time 64 µs

Input ripple voltage IOUT = 30 A 864 mVPP

Output ripple voltage IOUT = 30 A 20 mVPP

Output rise time Set by SS pin capacitor 139 μs

Current limit Set by ILIM pin resistor 30.6 A

Switching frequency (fSW) Set by MSEL pin resistor 1400 kHz

Peak efficiency IOUT = 15 A 83.3 %

IC case temperature IOUT = 30 A, 15-minute soak 128 °C

Table 1-3. TPS54KC23EVM High Efficiency (U2) Performance Characteristics Summary

SPECIFICATION TEST CONDITIONS MIN TYP MAX UNIT

VIN voltage range 4.5 12 16 V

Input current VIN = 4.5 V, IOUT = 30 A 6.5 A

VIN start voltage Set by EN pin resistor divider 3.84 V

VIN stop voltage Set by EN pin resistor divider 3.20 V

Output voltage setpoint 0.802 V

Output current range VIN = 4.5 V to 16 V 0 30 A

Line and load regulation VIN = 4.5 V to 16 V, IOUT = 0 A to 30 A ±0.4%

Load transient response

IOUT = 5 A to 20 A Voltage change –4 mV

Recovery time 54 µs

IOUT = 5 A to 20 A Voltage change 4 mV

Recovery time 55 µs

Input ripple voltage IOUT = 30 A 472 mVPP

Output ripple voltage IOUT = 30 A 4.8 mVPP

Output rise time Set by SS pin capacitor 944 μs

Current limit Set by ILIM pin resistor 30.6 A

Switching frequency (fSW) Set by MSEL pin resistor, J8 short pins 3 and 4 800 kHz

Peak efficiency IOUT = 8 A 89.1 %

IC case temperature IOUT = 30 A, 15-minute soak 97 °C

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2 Configurations and Modifications

These evaluation modules are designed to provide access to the features of the TPS54KC23. The U2 design

provides jumpers for testing different configurations. Jumper selections must be made prior to enabling the

TPS54KC23.

If a desired configuration is not available, then some modifications can be made to this module. When

modifications are made to the components on the EVM, the internal compensation option selected with the

MSEL pin resistor needs to be changed. Changes to the fSW, output voltage, output inductor, and output

capacitors can require a change in the compensation. TPS54KC23 data sheet equations or WEBENCH can be

used to calculate the output capacitor value, compensation, fSW, and inductance. Verify that all components have

sufficient voltage and current ratings.

2.1 Output Voltage

In the U1 design, the output voltage is set by the resistor divider network of R2 (RFBT) and R6 (RFBB). R6 is fixed

at 8.25 kΩ to set the FB divider current at approximately 61 µA. The output voltage is set to 0.8V as default.

To change the output voltage of the EVM, the value of resistor R2 must change. Changing the value of R2

can change the output voltage above the 0.5-V reference voltage (VREF). The value of R2 for a specific output

voltage can be calculated using Equation 1.

In the U2 design, the output voltage is set by the resistor divider network of R15 (RFBT) and R12 (RFBB). R15 is

fixed at 8.25 kΩ to set the FB divider current at approximately 61 µA. The output voltage is set to 0.8V as default.

To change the output voltage of the EVM, the value of resistor R12 must change. Changing the value of R12

can change the output voltage above the 0.5-V reference voltage (VREF). The value of R12 for a specific output

voltage can be calculated using Equation 1. After changing R12, the feed forward capacitor (C51) also needs to

be changed.

RFBT =RFBB ×

VOUT

VREF

−1(1)

2.2 Frequency and Operation Mode Setting (MSEL Pin)

In the U2 design, jumper J8 can change between MSEL pin selections shown in Table 2-1. If the desired option

is unavailable, then change one of the resistors to the value that sets the desired option.

In the U1 design, change the MSEL resistor to the value which sets the desired option.

Table 2-1. MSEL Pin Selection

JUMPER SETTING MSEL RESISTOR (kΩ) OPERATION UNDER

LIGHT LOAD

SWITCHING

FREQUENCY (fSW) (kHz) RAMP

1 to 2 pin shorted 0 FCCM 800 RAMP4

3 to 4 pin shorted 4.99 FCCM 800 RAMP3

5 to 6 pin shorted 7.50 FCCM 800 RAMP2

7 to 8 pin shorted 10.5 FCCM 800 RAMP1

9 to 10 pin shorted 56.2 Skip-mode 800 RAMP4

11 to 12 pin shorted 64.9 Skip-mode 800 RAMP3

13 to 14 pin shorted(1) 75.0 Skip-mode 800 RAMP2

15 to 16 pin shorted 86.6 Skip-mode 800 RAMP1

(1) Default Setting

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3 Test Setup and Results

This section describes how to properly connect, set up, and use the TPS54KC23EVM evaluation module.

The section also includes test results typical for the evaluation module and covers efficiency, output voltage

regulation, load transients, loop response, output ripple, input ripple, start-up, and current limit modes.

Measurements are taken with the following conditions unless otherwise noted.

• 12-V input

• Room temperature (20°C to 25°C)

• U1 with the default setting output voltage of 0.802 V, switching frequency of 1400 kHz, and maximum current

limit setting

• U2 with the default setting output voltage of 0.802 V, switching frequency of 800 kHz, and maximum current

limit setting

• With the other converter disabled

Figure 3-1. TPS54KC23EVM

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3.1 Input/Output Connections

The TPS54KC23EVM is provided with input connectors, output connectors, and test points as shown in Table

3-1 and Table 3-2.

To support the minimum input voltage with the full rated load on both outputs with the default EVM, a power

supply capable of supplying greater than 10 A must be connected to the VIN and PGND terminal blocks (J1 for

U1, and J3 for U2) through a pair of 18-AWG wires or better.

For U1, the load must be connected to J2 and for U2, the load must be connected to J4. A pair of 10-AWG wires

or better must be used for each connection. With the maximum current limit setting, the maximum load current

capability is near 33 A before the TPS54KC23 goes into current limit. Wire lengths must be minimized to reduce

losses in the wires.

Table 3-1. Connectors and Jumpers

REFERENCE

DESIGNATOR NAME RELATED IC FUNCTION

J1 VIN1 U1 VIN screw terminal to connect input voltage (see Table 1-1 for VIN range)

J2 VOUT1 U1 VOUT screw terminal to connect load to output

J3 VIN2 U2 VIN screw terminal to connect input voltage (see Table 1-1 for VIN range)

J4 VOUT2 U2 VOUT screw terminal to connect load to output

J5 EN2 U2

EN pin selection header:

Open = (EN pin shorted to AGND)

Short = (EN pin connected to VIN pin through resistor divider)

J8 - U2 MSEL selection header. Use shunt to select MSEL resistor (see Table 2-1 for

MSEL pin selection)

Table 3-2. Test Points

REFERENCE

DESIGNATOR NAME RELATED IC FUNCTION

TP1 VIN1 U1 VIN test point. Use this for efficiency measurements.

TP2 SW1 U1 SW node test point

TP3 VOUT1 U1 VOUT test point

TP4 REG_GND1 U1 PGND test point. Use this for efficiency measurements.

TP5 VCC1 U1 VCC test point

TP6 PG1 U1 PGOOD output test point (pulled up to VCC pin through a 10-kΩ resistor)

TP7 BODE1 U1 Test point between voltage divider network and output voltage. Used for Bode

plot measurements.

TP8 REG_VOUT1 U1 VOUT test point. Use this for efficiency, output regulation, and bode plot

measurements.

TP9 PGND1 U1 PGND test point. Use this for efficiency measurements.

TP10 AGND1 U1 AGND test point

TP11 VOUT_U1 U1

SMB connector to measure output voltage. When using this test point, set the

scope for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is

created.

TP12 VIN2 U2 VIN test point

TP13 VOUT2 U2 VOUT test point

TP14 SW2 U2 SW test point

TP15 EN2 U2 EN test point

TP16 VCC2 U2 VCC test point

TP17 REG_GND2 U2 PGND test point. Use this for efficiency measurements.

TP18 PG2 U2 PGOOD output test point (pulled up to VCC pin through a 10-kΩ resistor)

TP19 BODE2 U2 Test point between voltage divider network and output voltage. Used for Bode

plot measurements.

TP20 REG_VOUT2 U2 VOUT test point. Use this for efficiency, output regulation, and bode plot

measurements.

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Table 3-2. Test Points (continued)

REFERENCE

DESIGNATOR NAME RELATED IC FUNCTION

TP21 SS2 U2 SS test point

TP22 ILIM2 U2 ILIM test point

TP23 MSEL2 U2 MSEL test point

TP24 PGND2 U2 PGND test point. Use this for efficiency measurements.

TP25 AGND2 U2 AGND test point

TP28 SW_U2 U2

SMB connector to measure SW node. When using this test point, set the scope

for 50-Ω termination. The combination of 50-Ω termination and 450-Ω series

resistance creates a 10:1 attenuation.

TP29 VOUT_U2 U2

SMB connector to measure output voltage. When using this test point, set the

scope for 1-MΩ termination. When using 50-Ω termination, a 2:1 divider is

created.

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3.2 Efficiency

Figure 3-2 through Figure 3-5 show the efficiency for both designs on the TPS54KC23EVM. The test points

listed in Table 3-3 are used for the efficiency measurement. Use these test points to minimize the contribution of

PCB parasitic power loss to the measured power loss.

The following are some additional test setup considerations to minimize external sources of power dissipation.

• Disable the other regulator to avoid including the switching quiescent current of the other regulator in the

efficiency measurement.

• Do not measure the SW pin of U2 with TP28 while measuring the efficiency of U2. Measuring the SW pin

with this test point loads this node with 500 Ω and the efficiency measurement includes the power lost in this

external resistance.

Table 3-3. Efficiency Measurement Test Points

RELATED IC TEST POINT NAME REFERENCE

DESIGNATOR FUNCTION

VIN1 TP1 Input voltage test point connected near pins of U1

PGND1 TP9 PGND reference test point for input voltage

REG_VOUT1 TP8 Output voltage test point near output inductor of U1

REG_GND1 TP4 PGND reference test point for output voltage

VIN2 TP12 Input voltage test point connected near pins of U2

PGND2 TP24 PGND reference test point for input voltage

REG_VOUT2 TP20 Output voltage test point near output inductor of U2

REG_GND2 TP17 PGND reference test point for output voltage

Output Current (A)

Efficiency (%)

0 5 10 15 20 25 30

100

Vin = 12 V

Vin = 8 V

Vin = 16 V

Figure 3-2. U1 Efficiency – Skip-Mode (Default)

Output Current (A)

Efficiency (%)

0 5 10 15 20 25 30

100

Vin = 12 V

Vin = 8 V

Vin = 16 V

Figure 3-3. U2 Efficiency – Skip-Mode (Default)

Output Current (A)

Efficiency (%)

0.001 0.005 0.02 0.05 0.1 0.20.3 0.5 1 2 3 4 5 7 10 20 3030

100

FCCM, Vin = 12V

FCCM, Vin = 8V

FCCM, Vin = 16V

Skip-mode, Vin = 12V

Skip-mode, Vin = 8V

Skip-mode, Vin = 16V

Figure 3-4. U2 Efficiency - FCCM vs Skip-Mode

Output Current (A)

Efficiency (%)

0 5 10 15 20 25 30

100

Vin = 12 V

Vin = 8 V

Vin = 16 V

Figure 3-5. U2 Efficiency – FCCM

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3.3 Output Voltage Regulation

Figure 3-6 and Figure 3-7 show the load and line regulation for U1. Figure 3-8 and Figure 3-9 show the load and

line regulation for U2.

Output Current (A)

Output Voltage (V)

0 5 10 15 20 25 30

0.793

0.794

0.795

0.796

0.797

0.798

0.799

0.8

0.801

Vin = 12 V

Vin = 8 V

Vin = 16 V

Figure 3-6. U1 Load Regulation

Input Voltage (V)

Output Voltage (V)

8 9 10 11 12 13 14 15 16

0.793

0.794

0.795

0.796

0.797

0.798

0.799

0.8

Iout = 15 A

Iout = 30 A

Figure 3-7. U1 Line Regulation

Output Current (A)

Output Voltage (V)

0 5 10 15 20 25 30

0.796

0.797

0.798

0.799

0.8

0.801

0.802

0.803

Vin = 12 V

Vin = 8 V

Vin = 16 V

Figure 3-8. U2 Load Regulation

Input Voltage (V)

Output Voltage (V)

4 5 6 7 8 9 10 11 12 13 14 15 16

0.795

0.796

0.797

0.798

0.799

0.8

0.801

0.802

Iout = 15 A

Iout = 30 A

Figure 3-9. U2 Line Regulation

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