Texas Instruments TPS7H4002EVM-CVAL User manual

User’s Guide
TPS7H4002EVM-CVAL Evaluation Module
ABSTRACT
The TPS7H4002EVM-CVAL is the evaluation module (EVM) for the TPS7H4002-SP and provides a platform to
electrically evaluate its features. This user's guide provides details about the EVM, its configuration, schematics,
and BOM.
Figure 1-1. TPS7H4002EVM-CVAL
Table of Contents
1 TPS7H4002EVM-CVAL Overview...........................................................................................................................................3
2 TPS7H4002EVM-CVAL Default Configuration...................................................................................................................... 3
3 TPS7H4002EVM-CVAL Initial Setup...................................................................................................................................... 4
4 TPS7H4002EVM-CVAL Testing.............................................................................................................................................. 5
5 TPS7H4002EVM-CVAL EVM Schematic..............................................................................................................................15
6 TPS7H4002EVM-CVAL Bill of Materials (BOM).................................................................................................................. 16
7 Board Layout.........................................................................................................................................................................18
List of Figures
Figure 1-1. TPS7H4002EVM-CVAL.............................................................................................................................................1
Figure 4-1. Output Voltage Regulation........................................................................................................................................ 5
Figure 4-2. Output Voltage Ripple VIN = 5 V, VOUT = 2.5 V, IOUT = 3 A................................................................................... 6
Figure 4-3. Output Soft Start Voltage, VIN = 5 V, VOUT = 2.5 V, IOUT = 3 A............................................................................. 7
Figure 4-4. Transient Response to Load Step 0 A to 3 A at 1 A/µs.............................................................................................8
Figure 4-5. Transient Response to Load Step 3 A to 0 A at 1 A/µs.............................................................................................9
Figure 4-6. Input Voltage Ripple, VIN = 5 V, VOUT = 2.5 V, IOUT = 3 A...................................................................................10
Figure 4-7. EVM Modification to Measure Frequency Response...............................................................................................11
Figure 4-8. Frequency Response Test Setup............................................................................................................................ 12
Figure 4-9. Frequency Response IOUT = 3 A........................................................................................................................... 12
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Figure 4-10. Frequency Response IOUT = 0 A......................................................................................................................... 13
Figure 4-11. High-Side Current Limiting.....................................................................................................................................14
Figure 5-1. TPS7H4002EVM-CVAL EVM Schematic................................................................................................................ 15
Figure 7-1. Top Overlay............................................................................................................................................................. 18
Figure 7-2. Top Solder............................................................................................................................................................... 18
Figure 7-3. Layer 1 -Top Layer.................................................................................................................................................. 19
Figure 7-4. Layer 2- GND.......................................................................................................................................................... 19
Figure 7-5. Layer Three - Signal................................................................................................................................................20
Figure 7-6. Layer Four -Bottom Layer....................................................................................................................................... 20
Figure 7-7. Bottom Solder..........................................................................................................................................................21
Figure 7-8. Bottom Overlay........................................................................................................................................................21
Figure 7-9. Drill Drawing............................................................................................................................................................ 22
Figure 7-10. Drill Table...............................................................................................................................................................22
Figure 7-11. Board Dimensions................................................................................................................................................. 23
List of Tables
Table 2-1. Default EVM Configuration......................................................................................................................................... 3
Table 3-1. Summary of Connections............................................................................................................................................4
Table 6-1. TPS7H4002EVM-CVAL Bill of Materials (BOM)....................................................................................................... 16
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1 TPS7H4002EVM-CVAL Overview
The TPS7H4002-SP is a radiation hardened, 3-V to 5.5-V, 3-A synchronous step-down converter with integrated
high-side and low-side MOSFETs. High efficiency and efficient usage of space are achieved through low
resistance MOSFETs and a current mode control implementation.
The EVM is configured in a default state to accept a 5-V input but can be modified to disable or change the
undervoltage lock out (UVLO) protection, allowing for any input voltage from 3 V to 5.5 V. The EVM is also
configured for a 2.5-V output at a maximum peak output current of 3 A. Again, the regulated output voltage can
be modified by changing one resistor on the board. The TSP7H4002-SP has a dedicated soft start, enable, and
power good pins providing design flexibility to meet specific application requirements.
1.1 Features
• 0.807-V ±1.5% voltage reference overtemperature, radiation, and line and load regulation
• Adjustable soft start
• Adjustable input enable and undervoltage lockout (UVLO)
• Power good indicator pin
• Maximum output current of 3 A
1.2 Applications
• Point of load regulation
• Supports harsh environment applications
• Space satellite point of load supply for FPGAs, microcontrollers, data converters, and ASICs
• Space satellite payloads
• Radiation hardened applications
2 TPS7H4002EVM-CVAL Default Configuration
Table 2-1 describes the default configuration of the TPS7H4002EVM-CVAL listing the external components that
define the converter design.
Table 2-1. Default EVM Configuration
Parameter Specifications Description
Input power supply 5 V Bound by UVLO enable circuit (R13, R15)
Regulated output voltage 2.5 V R7 (RTOP) = 10 kΩ, R5 (RBOTTOM) = 4.7 kΩ
LOUT 2.2 µH Chosen to meet inductor ripple current of 40% (Kind = 0.4)
COUT 330 µF
Chosen for (1) ESR = 6 mΩ to set output voltage ripple;
(2) value used during single event effects testing ensuring regulation maintained
with single event upset to switching
Output current 0 to 3 A By design
Switching frequency 500 kHz Set by R10 (RT) = 95.3 kΩ
Soft start time constant ≈ 3.2 ms Set by C1 (Css) = 10 nF
UVLO enable rising ≈ 4.432 V Set by R13 = 10 kΩ and R15 = 3.4 kΩ
UVLO enable falling ≈ 4.284 V Set by R13 = 10 kΩ and R15 = 3.4 kΩ
Loop bandwidth ≈ 30 kHz
Set by operational transconductance amplifier (OTA) compensation circuit: R14
(RCOMP) = 11.8 kΩ, C14 (CCOMP) = 22 nF, C6 (CHF) = 22 pF
Loop phase margin ≈ 60°
Gain margin ≈ –25 dB
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3 TPS7H4002EVM-CVAL Initial Setup
This section provides the test instruments required and the connections to the EVM.
1. Input DC power supply
a. Set for 5-V DC, 3-A current limit.
b. Connect the positive output of the DC supply to connector J2 (PVIN) and the negative terminal of the
supply to connector J5 for ground.
Note
For more precise measurements, eliminating the IR voltage drop in the input cables is
achieved by using a power supply source with sensing ports and connecting between TP6
to PVIN and TP23 to GND.
2. DC electronic load
a. Connect the positive DC input to connector J8 (VOUT) using a 16-AWG wire.
Note
Wire to the e-load should include at least some part in which the wire gauge can be strapped
by the oscilloscope current probe. This will eliminate the need for a setup change to when
making transient measurements.
b. Connect the negative DC input of e-load to connector J7 (GND) using a 16-AWG wire.
c. Connect voltage monitoring sensing ports of e-load across test points TP17 (VOUT) and TP26 (GND). A
voltage meter can be used to monitor this voltage also.
3. Oscilloscope
a. CH1 - Connect the voltage scope probe to scope probe test point J4 (PH) to monitor the phase node.
DC coupled, Full BW, 2 V/div, Rising Edge Trigger at 0.5 V.
b. CH2 - Connect voltage scope probe to scope probe test point J9 (VOUT) to monitor the output voltage.
AC coupled, BW = 20 MHz, 10 mV/div.
c. CH3 - Connect current scope probe to monitor current through wire connecting J8 (VOUT) and e-load. 5
A/div
Note
Only required for transient load testing
Table 3-1. Summary of Connections
Reference
Designator Silkscreen Function
J2,
J5 PVIN Input power: J2 = 5 V, J5 = GND (Vsupply)
J8,
J7 VOUT Output current: J8 = VOUT J7 = GND, pin 2 = VOUT ≈ 1 V (e-load)
J6 PH4 Phase switching node scope probe test point (Scope CH-1)
J9 VOUT VOUT scope probe test point (Scope CH-2)
TP17 VOUT VOUT test point (e-load monitor)
TP6 PVIN PVIN test point (Vsupply_sense)
TP18, TP23 GND GND test points ( e-load monitor, Vsupply_sense)
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4 TPS7H4002EVM-CVAL Testing
The following tests are described in subsequent sections:
1. Output voltage regulation
2. Output voltage ripple
3. Soft start-up
4. Transient response to positive/negative load step (0 A to 3 A to 0 A)
5. Input voltage ripple
6. Loop frequency response
7. Current limiting
4.1 Output Voltage Regulation
• Turn on the input DC source (5 V)
• Turn on the e-load and sweep the load current from 0 A to 3 A, or higher to observe the margin the device
has to the recommended operating condition of 3-A maximum. The monitored output voltage at TP17 (VOUT)
is at or near 2.5 V across the entire current load sweep as shown in Figure 4-1.
Figure 4-1. Output Voltage Regulation
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4.2 Output Voltage Ripple
Display CH1 (PH1) and CH2 (VOUT1) [AC coupled, BW = 20 MHz] on the oscilloscope to monitor the switching
phase node and the output voltage ripple as shown in Figure 4-2.
Figure 4-2. Output Voltage Ripple VIN = 5 V, VOUT = 2.5 V, IOUT = 3 A
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4.3 Soft Start-up
Display CH1 (PH1) and CH2 (VOUT1) [DC coupled, 500 mV/div] on the oscilloscope to monitor the switching
phase and the soft start profile of the output voltage as shown in Figure 4-3.
Figure 4-3. Output Soft Start Voltage, VIN = 5 V, VOUT = 2.5 V, IOUT = 3 A
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4.4 Transient Response to Positive/Negative Load Step (0 A to 3A to 0A)
• Configure e-load to switch between 0 A and 3 A at a rate of 1 A/µs.
• On the oscilloscope, display CH2 (VOUT) [AC coupled, 50 mV/div] and CH3 (Output Current Probe) [1 A/div,
trigger rising edge ≈ 120 mA] with 20 µs/div.
Figure 4-4 shows the response to this load step to be about 50mV, or 2%.
Figure 4-4. Transient Response to Load Step 0 A to 3 A at 1 A/µs
• Change the trigger on CH3 to falling edge to capture the transient response of VOUT to negative current step
from 3 A to 0 A as shown in Figure 4-5.
Again, transient deviation is approximately 50 mV, ignoring peak envelope, or 2%.
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Figure 4-5. Transient Response to Load Step 3 A to 0 A at 1 A/µs
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4.5 Input Voltage Ripple
• Trigger CH1 of the oscilloscope on Phase Node and put the CH2 scope probe between test point TP6 (PVIN)
and TP23 (GND).
As shown in Figure 4-6, the voltage ripple (ignoring the switching coupling to the input) is approximately 50 mV.
Figure 4-6. Input Voltage Ripple, VIN = 5 V, VOUT = 2.5 V, IOUT = 3 A
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