Texas Instruments TPS631012/3 User manual

EVM User's Guide: TPS631012/3
TPS631012/3 Evaluation Module
Description
The TPS631012/3 is a highly efficientcy, single-
inductor, internally compensated buck-boost converter
in a 8-pin, 0.9-mm × 1.8-mm DSBGA package.
The output voltage is programmable from 1.0V to
5.5V in 25mV steps via I2C. The EVM is based
on TPS631012, in which the power-up value of
the ENABLE bit is 0. The only difference between
TPS631012 and TPS631013 is the ENABLE bit.
Features
• Output current 1.5 A (Vin > 2.7 V to Vout = 3.3V)
• Over 92% efficiency Vin=3.6V to Vout=3.3V
Iout=1A
• 8 µA operating quiescent current
• I2C configurable
• Fixed frequency operation (2.0 MHz)
• Auto PFM / Forced PWM mode selectable
TPS631012/3 EVM
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1 Evaluation Module Overview
1.1 Introduction
This user’s guide describes the operation and use of the TPS631012/3EVM. The EVM is designed to help users
easily evaluate and test the operation and functionality of the TPS631012/3 buck-boost converter family. The
EVM has the output voltage set to 3.3 V . The output voltage can be programmed via I2C interface between 1.0
V and 5.5 V. The EVM operates with an input voltage between 1.6 V and 5.5 V and the output current can go up
to 1.5 A when Vin≥2.7V. This document includes setup instructions for the hardware, together with the schematic
and the PCB layout of the EVM. Throughout this document, the abbreviations EVM, TPS631012/3EVM, and the
term evaluation module are synonymous with the TPS631012/3, unless otherwise noted.
1.2 Kit Contents
Table 1-1. Kit List
Designator Quantity Description Material Type Packaging
PCB1 1 'TPS631012EVM; Circuit Board; EEE Bag, ESD
BOX1 1 Box, Cardboard Cardboard Box
FM1 2 Foam, Antistatic Plastic Foam
LBL1 1 Label, Small & Large standard labels Paper/card stock Paper
LIT1 1 Literature, EVM Disclaimer Read Me Paper/card stock Paper
LIT2 1 Literature, EVM Disclaimer Read Me Paper/card stock Paper
1.3 Specification
Table 1-2. Performance Specification Summary
SPECIFICATION SPECIFICATION MIN TYP MAX UNIT
Input voltage 1.6 5.5 V
Start-up input voltage 1.65 5.5 V
Output voltage 1.0 5.5 V
Output current VIN≥2.7V, VOUT=3.3V 0 1500 mA
1.4 Device Information
The TPS631012 and TPS631013 are constant frequency peak current mode control buck-boost converters in
tiny wafer chip scale package. The TPS631012 and TPS631013 have a 3-A peak current limit (typical) and 1.6-V
to 5.5-V input voltage range, and provide a power supply for system pre-regulators and voltage stabilizers.
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2 Hardware
2.1 Background
The TPS631012/3EVM uses the TPS631012/3 integrated circuit (IC) , and is set to 3.3 V output voltage. The
EVM operates with an input voltage between 1.6 V and 5.5 V.
2.2 Setup
This section describes how to properly use the TPS631012/3EVM.
2.3 Input and Output Connectors, Test Points, and Headers Description
2.3.1 J1, Pin 1 and 2 – VIN
Positive input voltage connection from the input power supply for the EVM.
2.3.2 J1, Pin 3 and 4 – S+/S-
Input voltage sense connections. Measure the input voltage at this point.
2.3.3 J1, Pin 5 and 6 – GND
Input voltage GND return connection from the input power supply for the EVM, common with J2 GND connection
2.3.4 J2, Pin 1 and 2 – VOUT
Positive output voltage connection
2.3.5 J2, Pin 3 and 4 – S+/S-
Output voltage sense connections. Measure the output voltage at this point.
2.3.6 J2, Pin 5 and 6 – GND
Output voltage GND return connection, common with J1 GND connection
2.3.7 Test Points
2.3.7.1 J4, J5
Test points connected to L1 and L2 switch node pins of the TPS631012/3
2.3.7.2 TP1, TP2
Test points connected to SDA and SCL pins of the TPS631012/3
2.3.8 Header Information
2.3.8.1 J6– I2C
10-pin header used to connect the USB2ANY adapter to the EVM
2.3.9 Jumper Information
2.3.9.1 JP1 – ENABLE
Placing a jumper across pins EN and ON enables the device. Placing a jumper across pins EN and OFF
disables the device.
2.4 Setup
To operate the EVM, connect a power supply with the positive lead to J1 VIN pins and the negative lead to J1
GND pins. Connect a load with the positive lead to J2 VOUT pins and the negative lead to J2 GND pins. Place a
jumper across EN and ON pins on J3 to enable the device.
2.5 Modifications
The printed-circuit board (PCB) for the EVM is designed to accommodate the TPS631012/3. Extra positions are
available for additional input and output capacitors and I2C pullup resistors.
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2.5.1 IC U1 Operation
This EVM requires an appropriate I2C interface, such as the TI USB2ANY, to reconfigure the TPS631012/3. The
output voltage can be chosen between two I2C-programmable values by using an on-board jumper. See Section
3.4 for the available output voltage values.
3 Software
3.1 Software Setup
A graphical user interface (GUI) is available from ti.com (TPS631012), which allows simple and convenient
programming of the device through the TI USB2ANY (http://www.ti.com/tool/USB2ANY) device. Alternatively, the
user can use any I2C-standardized programming tool or I2C host to configure the device. Be mindful of the I2C
pins specification, such as timing parameters and proper pullup resistors.
3.2 Interface Hardware Setup
Connect the USB2ANY adapter to your PC using the supplied USB cable. Connect the EVM connector J3 to
the USB2ANY adapter using the supplied 10-pin ribbon cable. The connectors on the ribbon cable are keyed to
prevent incorrect installation.
Figure 3-1 shows a quick adapter connection overview.
Figure 3-1. Quick Connection Overview
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3.3 User Interface Operation
Upon start-up, the GUI automatically connects to the EVM. If not, then click on the Connect button in the lower
left corner of the GUI window. The following sections give short overview of the three main GUI screens.
3.3.1 Home Screen
The Home screen gives a short overview of the TPS631012/3 devices. To start evaluating the device, click on
the Start button or on the Settings or Register Map icons on the left side of the GUI window.
Figure 3-2. GUI Home Screen
3.3.2 Settings Screen
The Settings screen provides control over the output voltage and operating modes of the TPS631012/3.
Figure 3-3. GUI Settings Screen
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3.3.3 Register Map Screen
The Register Map screen shows a register-wise view of all parameters. Here, single registers can be read or
written to the device (if applicable). Refer to Section 3.4 for a detailed description of the TPS631012/3 registers.
Figure 3-4. GUI Register Map Screen
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3.4 Register Map
Table 3-1 lists the memory-mapped registers for the Device registers. All register offset addresses not listed in
Table 3-1 must be considered as reserved locations and the register contents must not be modified.
Table 3-1. Device Registers
Address Acronym Register Name Section
0X02 CONTROL1 Control 1 Register Go
0X03 VOUT VOUT Register Go
0X05 CONTROL2 Control 2 Register Go
3.4.1 Register CONTROL1 (Target Address: 0x2A; Register Address: 0x02; Default: 0x08)
Table 3-2 shows the CONTROL1 register.
Return to Section 3.4.
This register configures the device. This register is volatile, so the register loses contents if the voltage on the
VIN pin becomes less than the UVLO threshold or a low logic level is applied to the EN pin.
Table 3-2. CONTROL1 Register Field Descriptions
Bit Field Type Reset Description
7:4 RESERVED R 0b0000 Not used.
During write operations data for these bits are ignored. During
read operations 0 is returned
3 EN_FAST_DVS R/W 0b0 Sets DVS to fast mode
0 : DISABLE, 1 : ENABLE
2 EN_SCP R/W 0b0 Enable short circuit hiccup protection
0 : DISABLE, 1 : ENABLE
1 NIL R 0b0 Not used
0 CONVERTER_EN R/W 0b0_TPS631012 Enable Converter ('AND'ed with EN-pin)
0 : DISABLE, 1 : ENABLE
0b1_TPS631013
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3.4.2 Register VOUT (Target Address: 0x2A; Register Address: 0x03; Default: 0x5C)
Table 3-3 shows the STATUS register.
Return to Section 3.4.
This register contains the device status. A read operation to this register clears the status bits. This register is
volatile, so the register loses contents if the voltage on the VIN pin becomes less than the UVLO threshold or a
low logic level is applied to the EN pin.
Table 3-3. Register VOUT Field Descriptions
Bit Field Type Reset Description
7:0 VOUT[7:0] R/W 0X5C These bits set the output voltage
Output voltage = 1.000 + (VOUT[7 :0] × 0.025) V when
0x00<=VOUT[7 :0]<=0xB4;
Output voltage = 5.5 V when 0xB5<=VOUT[7 :0]<=0xFF
3.4.3 Register CONTROL2 (Target Address: 0x2A; Register Address: 0x05; Default:0x45)
Table 3-4 shows the CONTROL2 register.
Return to Section 3.4.
This register identifies the die revision of the device.
Table 3-4. Register CONTROL2 Field Descriptions
Bit Field Type Reset Description
7 FPWM R/W 0b0 Force PWM operation
0 : DISABLE, 1 : ENABLE
6 FAST_RAMP_EN R/W 0b1 Device can start-up faster then VOUT ramp
0 : DISABLE, 1 : ENABLE
5:4 EN_DISCH_VOUT[1:0] R/W 0b00 Enable of BUBO Vout Discharge
00 : DISABLE
01 : SLOW (34mA)
10 : MEDIUM (67mA)
11 : FAST (100mA)
3 CL_RAMP_MIN R/W 0b0 Define the minimum current limit during the soft start ramp
0 : Low (500mA)
1 : High (2x Low)
2:0 TD_RAMP[2:0] R/W 0b101 Defines the ramp time for the Vo soft start ramp
000: 0.256ms
001: 0.512ms
010: 1.024ms
011: 1.920ms
100: 3.584ms
101: 7.552ms
110: 9.600ms
111: 24.320ms
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4 Hardware Design Files
4.1 Schematic
EXT_3V3
EXT_3V3
1 2
3 4
5 6
7 8
9 10
J6
TP1
SDA
GND
EXT_3V3
TP2
SCL
SDA
SCL
5
4
1
2
3
6
J1
5
4
1
2
3
6
J2
150uF
C1 22uF
10V
C2
22uF
10V
C3
22uF
10V
C5
22uF
10V
C4
22uF
10V
C6
1µH
L1
1
2
J4
1
2
J5
GND
GND
L1
L2
1
2
3
J3
EN
GND
EN
ON
OFF
VIN
S+
S-
GND
VOUT
S+
S-
GND
OUTPUT
GNDGND GND GND GND GND GND GND GND
100k
R1 INPUT
INPUT
EN
L1 L2
VI N
A1 LX1 B1
LX2 C1
EN
A2
SCL
D2
SDA
B2 VOUT D1
GND C2
TPS631012
U1
10.0k
R2
10.0k
R3
Figure 4-1. TPS631012/3EVM Schematic
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4.2 Board Layout
This section provides the TPS631012/3EVM board layout and illustrations.
Figure 4-2 and Figure 4-3 show the component placement and PCB layout of the TPS631012/3EVM.
Figure 4-2. TPS631012/3EVM PCB - Top Layer
Figure 4-3. TPS631012/3EVM PCB - Bottom Layer (Top View)
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