Texas Instruments TPS59650EVM-753 User manual

User's Guide
SLUU896–March 2012
Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase
CPU/2-Phase GPU SVID Power System
The TPS59650EVM-753 evaluation module (EVM) is a complete solution for Intel™ IMVP7 Serial
VID(SVID) Power System from a 9V-20V input bus. This EVM uses the TPS59650 for IMVP7 - 3-Phase
CPU and 2-Phase GPU Vcore controller, the TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4
Memory rail (1.2VDDQ, 0.6VTT and 0.6VTTREF) and also uses the (CSD87350Q5D) a 5mm x 6mm TI’s
power block MOSFETs that uses Powerstack™ technology with high-side and low-side MOSFETs for high
power density and superior thermal performance.
Contents
1 Description ................................................................................................................... 5
1.1 Typical Applications ................................................................................................ 5
1.2 Features ............................................................................................................. 5
2 TPS59650EVM-753 Power System Block Diagram .................................................................... 6
3 Electrical Performance Specifications .................................................................................... 7
4 Test Setup ................................................................................................................... 8
4.1 Test Equipment ..................................................................................................... 8
4.2 Recommended Wire Gauge ...................................................................................... 9
4.3 Recommended Test Setup ....................................................................................... 9
4.4 USB Cable Connections ......................................................................................... 10
4.5 Input Connections ................................................................................................ 10
4.6 Output Connections .............................................................................................. 11
5 Configuration ............................................................................................................... 11
5.1 CPU and GPU Configuration ................................................................................... 11
5.2 1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration ...................................................... 13
5.3 1.05V VCCIO Configuration ..................................................................................... 13
6 Test Procedure ............................................................................................................ 14
6.1 Line/Load Regulation and Efficiency Measurement Procedure ............................................ 14
6.2 Equipment Shutdown ............................................................................................ 17
7 Performance Data and Typical Characteristic Curves ................................................................ 18
7.1 CPU 3-Phase Operation ......................................................................................... 18
7.2 CPU 2-Phase Operation ......................................................................................... 21
7.3 CPU1-Phase Operation .......................................................................................... 25
7.4 GPU 2 Phase Operation ......................................................................................... 29
7.5 GPU 1 Phase Operation ......................................................................................... 32
7.6 1.05V VCCIO ...................................................................................................... 36
7.7 1.2V VDDQ ........................................................................................................ 39
8 EVM Assembly Drawings and PCB Layout ............................................................................ 42
9 Bill of Materials ............................................................................................................. 47
10 Schematics ................................................................................................................. 50
List of Figures
1 TPS59650EVM-753 Power System Block Diagram.................................................................... 6
2 TPS59650EVM-753 EVM Illustration..................................................................................... 7
Powerstack is a trademark of Texas Instruments.
Intel is a trademark of Intel.
All other trademarks are the property of their respective owners.
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3 USB Cable................................................................................................................... 8
4 TPS59650EVM-753 Recommended Test Set Up..................................................................... 10
5 TPS59650EVM-753 CPU GUI set up Window ........................................................................ 15
6 TPS59650EVM-753 GPU GUI set up Window ........................................................................ 16
7 CPU3 Efficiency ........................................................................................................... 18
8 CPU3 Load regulation .................................................................................................... 18
9 CPU3 Enable Turn on .................................................................................................... 18
10 CPU3 Enable Turn off .................................................................................................... 18
11 CPU3 Switching Node(Ripple) .......................................................................................... 18
12 CPU3 Dynamic VID: SetVID-Slow/Slow................................................................................ 18
13 CPU3 Dynamic VID:SetVID-Fast/Fast ................................................................................. 19
14 CPU3 Dynamic VID:SetVID-Decay/Fast ............................................................................... 19
15 CPU3 Output Load Insertion with OSR/USR middle level .......................................................... 19
16 CPU3 Output Load Release with OSR/USR middle level............................................................ 19
17 CPU3 Bode Plot at 12Vin, 1.05V/60A .................................................................................. 20
18 CPU3 MOSFET ........................................................................................................... 20
19 CPU3 IC .................................................................................................................... 20
20 CPU2 Efficiency ........................................................................................................... 21
21 CPU2 Load regulation .................................................................................................... 21
22 CPU2 Enable Turn on .................................................................................................... 21
23 CPU2 Enable Turn off .................................................................................................... 21
24 CPU2 Switching Node(Ripple) .......................................................................................... 22
25 CPU2 Dynamic VID: SetVID-Slow/Slow................................................................................ 22
26 CPU2 Dynamic VID:SetVID-Fast/Fast ................................................................................. 22
27 CPU2 Dynamic VID:SetVID-Decay/Fast ............................................................................... 22
28 CPU2 Output Load Insertion with OSR/USR middle level .......................................................... 23
29 CPU2 Output Load Release with OSR/USR middle level............................................................ 23
30 CPU2 Bode Plot at 12Vin, 1.05V/55A .................................................................................. 24
31 CPU2 MOSFET ........................................................................................................... 24
32 CPU2 IC .................................................................................................................... 24
33 CPU1 Efficiency ........................................................................................................... 25
34 CPU1 Load regulation .................................................................................................... 25
35 CPU1 Enable Turn on .................................................................................................... 25
36 CPU1 Enable Turn off .................................................................................................... 25
37 CPU1 Switching Node ................................................................................................... 25
38 CPU1 Switching node and Ripple ...................................................................................... 25
39 CPU1 Dynamic VID:SetVID-Slow/Slow ................................................................................ 26
40 CPU1 Dynamic VID:SetVID-Fast/Fast ................................................................................. 26
41 CPU1 Dynamic VID:SetVID-Decay/Fast ............................................................................... 26
42 CPU1 Output Load Insertion with OSR/USR middle level .......................................................... 26
43 CPU1 Output Load Release with OSR/USR middle level............................................................ 27
44 CPU1 Bode Plot at 12Vin, 1.05V/33A .................................................................................. 28
45 CPU1 MOSFET ........................................................................................................... 28
46 CPU1 IC .................................................................................................................... 28
47 GPU2 Efficiency .......................................................................................................... 29
48 GPU2 Load regulation .................................................................................................... 29
49 GPU2 Enable Turn on ................................................................................................... 29
50 GPU2 Enable Turn off ................................................................................................... 29
51 GPU2 Switching Node and Ripple ..................................................................................... 29
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52 GPU2 Dynamic VID:SetVID-Slow/Slow ................................................................................ 29
53 GPU2 Dynamic VID:SetVID-Fast/Fast ................................................................................. 30
54 GPU2 Dynamic VID:SetVID-Decay/Fast ............................................................................... 30
55 GPU2 Output Load Insertion with OSR/USR OFF ................................................................... 30
56 GPU2 Output Load Release with OSR/USR OFF .................................................................... 30
57 GPU2 Bode Plot at 12Vin, 1.23V/50A .................................................................................. 31
58 GPU2 MOSFET ........................................................................................................... 31
59 GPU2 IC .................................................................................................................... 31
60 GPU1 Efficiency .......................................................................................................... 32
61 GPU1 Load regulation .................................................................................................... 32
62 GPU1 Enable Turn on ................................................................................................... 32
63 GPU1 Enable Turn off ................................................................................................... 32
64 GPU1 Switching Node ................................................................................................... 33
65 GPU1 Switching Node and Ripple ..................................................................................... 33
66 GPU1 Dynamic VID:SetVID-Slow/Slow ................................................................................ 33
67 GPU1 Dynamic VID:SetVID-Fast/Fast ................................................................................. 33
68 GPU1 Dynamic VID:SetVID-Decay/Fast .............................................................................. 34
69 GPU1 Output Load Insertion with OSR/USR OFF.................................................................... 34
70 GPU1 Output Load Release with OSR/USR OFF .................................................................... 34
71 GPU1 Bode Plot at 12Vin, 1.23V/33A .................................................................................. 35
72 GPU1 MOSFET ........................................................................................................... 35
73 GPU1 IC .................................................................................................................... 35
74 1.05V Efficiency ........................................................................................................... 36
75 1.05V Load regulation .................................................................................................... 36
76 1.05V Enable Turn on .................................................................................................... 36
77 1.05V Enable Turn off .................................................................................................... 36
78 1.05V Switching Node ................................................................................................... 37
79 1.05V Ripple ............................................................................................................... 37
80 1.05V Transient DCM TO CCM ......................................................................................... 37
81 1.05V Transient CCM to DCM........................................................................................... 37
82 TPS51219 Thermal........................................................................................................ 38
83 1.2V Efficiency ............................................................................................................ 39
84 1.2V Load regulation...................................................................................................... 39
85 1.2V Enable Turn on ..................................................................................................... 39
86 1.2V Enable Turn off ..................................................................................................... 39
87 1.2V Switching Node ..................................................................................................... 39
88 1.2V Ripple................................................................................................................. 39
89 1.2V Transient DCM TO CCM .......................................................................................... 40
90 1.2V Transient CCM to DCM ............................................................................................ 40
91 TPS51916 Thermal........................................................................................................ 41
92 TPS59650EVM-753 Top Layer Assembly Drawing (Top view) ..................................................... 42
93 TPS59650EVM-753 Bottom Assembly Drawing (Bottom view)..................................................... 42
94 TPS59650EVM-753 Top Copper ....................................................................................... 43
95 TPS59650EVM-753 Bottom Copper ................................................................................... 43
96 TPS59650EVM-753 Internal Layer 2 .................................................................................. 44
97 TPS59650EVM-753 Internal Layer 3 .................................................................................. 44
98 TPS59650EVM-753 Internal Layer 4 .................................................................................. 45
99 TPS59650EVM-753 Internal Layer 5 ................................................................................... 45
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100 TPS59650EVM-753 Internal Layer 6 ................................................................................... 46
101 TPS59650EVM-753 Internal Layer 7 ................................................................................... 46
List of Tables
1 TPS59650EVM-753 Electrical Performance Specifications........................................................... 7
2 Current Limit Trip Selection.............................................................................................. 11
3 CPU Frequency Selection................................................................................................ 11
4 GPU Frequency Selection ............................................................................................... 12
5 F2808 DSP Program Mode Selection .................................................................................. 12
6 5Vin Bias Voltage Option (J33).......................................................................................... 12
7 On Board Dynamic Load Selection ..................................................................................... 12
8 VR_ON Enable Selection................................................................................................. 13
9 VDDQ S3, S5 Enable Selection ........................................................................................ 13
10 1.05V Enable Selection .................................................................................................. 13
11 VCCIO Output Voltage Selection ....................................................................................... 13
12 On Board Dynamic Load Enable/Disable selection .................................................................. 14
13 EVM Major Components List ............................................................................................ 47
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www.ti.com Description
1 Description
The TPS59650EVM-753 is designed to use a 9V-20V Input bus to produce 6 regulated outputs for IMVP7
SVID CPU/GPU Power System. The TPS59650EVM-753 is specially designed to demonstrate the
TPS59650 full IMVP7 mobile feature while providing GUI communication programing and a number of test
points to evaluate the static and dynamic performance of TPS59650.
1.1 Typical Applications
• IMVP7 Vcore Applications for Adapter, Battery, NVDC or 3V/5V/12V rails
1.2 Features
The TPS59650EVM-753 features:
• Complete solution for 9V-20V Input Intel IMVP7 SVID Power System
• GUI communication to demonstrate full IMVP7 Mobile feature
• 3-Phase CPU Vcore can support up to 94A output current
• 2-Phase GPU Vcore can support up to 46A output current
• 8 Selectable Switching frequency for CPU and GPU power
• 8 Levels selectable current limit for CPU and GPU power
• Switches or Jumpers for each output enable
• On Board Dynamic Load for CPU, GPU Vcore and VCCIO output
• High efficiency and high density by using TI power block MOSFET
• Convenient test points for probing critical waveforms
• Eight Layer PCB with 1oz copper
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9-20VBAT CPU Core
(94A)
GPU Core
(46A)
Power Block
IMVP7
TPS59650
48 Pin
6x6 QFN
TPS51219
16 Pin
3x3 QFN VCCIO: 1.05V/10A
TPS70102PWP
20 Pin
PWP
TPS51916
20 Pin
3x3 QFN
TMS320F2808PZS
TUSB3410RHB
VCCIO: 0A-10A
VDDQ: 1.2V/8A
VTT: 0.6V/2A,
VTTREF: 0.6V/10mA
1.8V/500mA
GPU: 0A-19A
On Board Dynamic
Load for CPU, GPU
and VCCIO
CPU: 0A-32A
SVID
5Vin 3.3V/250mA
Host Computer
B
USB Cable
A
GUI communication
DDR3L/DDR4 Memory Rail
TPS59650EVM-753 Power System Block Diagram www.ti.com
2 TPS59650EVM-753 Power System Block Diagram
Figure 1. TPS59650EVM-753 Power System Block Diagram
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CPU Core
GPU CORE
TPS51219
VCCIO
TPS59650
Chief River CPU
socket
OCL, FSW
selection
TPS51916
DDR3L/DDR4
Memory Rail
Intel SVID GUI
from USB
CPU/GPU
VR_ON
CPU Load
Connector
CSD87350Q5D
GPU Load Connector
www.ti.com Electrical Performance Specifications
Figure 2. TPS59650EVM-753 EVM Illustration
3 Electrical Performance Specifications
Table 1. TPS59650EVM-753 Electrical Performance Specifications(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
INPUT CHARACTERISTICS
12VBAT input voltage range VBAT 9 12 20 V
Maximum input current VBAT = 12V, all full load (3-Phase CPU/2-Phase GPU) 15.5 A
No load input current VBAT=12V, all no load(3-Phase CPU/2 Phase GPU) 0.14 A
5VIN input voltage range 5Vin 4.5 5 5.5 V
Maximum input current VBAT =12 V, all full load 0.3 A
No load input current VBAT=12V, all no load 0.1 A
OUTPUT CHARACTERISTICS
CPU(TPS59650)
Output voltage Vcore SVID: Address:00 CPU, Payload: 1.05V 1.05 V
Line regulation 0.1%
Output voltage regulation Load regulation(Droop) Load Line –1.9 mΩ
Output voltage ripple VBAT=12V, 1.05V/90A(3-Phase) at 300kHz 25 mVpp
Output load current CPU 3-Phase operation 0 94 A
Output over current Selectable per phase 37 A
Switching frequency Selectable 250 300 600 kHz
Full load efficiency VBAT=12V, 1.05V/95A at 300kHz 80.05%
GPU(TPS59650)
Output voltage Vcore SVID: Address:01 GPU, Payload: 1.23V 1.23 V
(1) Jumpers set to default locations, see section 6 of this user’s guide
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Test Setup www.ti.com
Table 1. TPS59650EVM-753 Electrical Performance Specifications(1) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Line regulation 0.1%
Output voltage regulation Load regulation(Droop) Load Line –3.9 mΩ
Output voltage ripple VBAT=12V, 1.23V/50A 2 Phase at 385kHz 30 mVpp
Output load current 0 50 A
Output over current Selectable per phase 37 A
Switching frequency Selectable 275 385 660 kHz
Full load efficiency VBAT=12V, 1.23V/50A 2 Phase at 385KHz 86.58%
1.05V VCCIO (TPS51219)
Output voltage 1.05 V
Line regulation 0.1%
Output voltage regulation Load regulation 0.1%
Output voltage ripple VBAT=12V, 1.05V/10A 30 mVpp
Output load current 0 10 A
Output over current 16 A
Switching frequency Selectable 500 kHz
Full load efficiency VBAT=12V, 1.05V/10A 89.87%
DDR3L/DDR4 Memory Rail (TPS51916)
Output voltage 1.2 V
Line regulation 0.1%
Output voltage regulation Load regulation 0.1%
Output voltage ripple VBAT=12V, 1.2V/8A 30 mVpp
Output load current 0 8 A
Output over current 10 A
Switching frequency Selectable 500 kHz
Full load efficiency VBAT=12V, 1.2V/8A 89.07%
Operating temperature 25 °C
4 Test Setup
4.1 Test Equipment
4.1.1 PC Computer (Host Computer)
Microsoft Windows XP or newer with available USB port
4.1.2 USB Cable
The USB Cable: Standard USB_A to USB_B 5 Pin Mini-B cable. See Figure 3 .
Figure 3. USB Cable
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4.1.3 TPS59650 USB driver and SVID GUI Installation
1. Copy the both files: setup.exe and setup.msi to the host computer.
2. Run this setup.exe.
3. Following installation Instructions, this will install the driver and the Texas Instruments SVID GUI.
4. It will add the below icon
4.1.4 DC Source
12VBAT DC Source: The 12VBAT DC source should be a 0-20V variable DC source capable of
supplying 20Adc current. Connect 12VBAT to J21 as shown in Figure 4.
5Vin DC Source: The 5Vin DC source should be a 0-5V variable DC source capable of supplying 1Adc
current. Connect 5Vin to J22 as shown in Figure 4.
4.1.5 Meters
•V1: 5Vin at TP81(5Vin) and TP83(GND)
•V2: 12VBAT at TP82(VBAT) and TP24(GND)
•V3: CPU Vcore sense voltage at J7; GPU Vcore sense voltage at J9; VDDQ sense voltage at J20,
VCCIO sense voltage at J16
•A1: 12VBAT input current
4.1.6 Load
The output load should be an electronic constant current load capable of 0-90Adc.
4.1.7 Oscilloscope
A digital or analog oscilloscope can be used to measure the output ripple. The oscilloscope should be set
for 1MΩimpedance, 20MHz Bandwidth, AC coupling, 2us/division horizontal resolution, 50mV/division
vertical resolution. Test point TP30 and TP46 can be used to measure the output ripple voltage for CPU
and GPU. Do not use a leaded ground connection as this may induce additional noise due to the large
ground loop.
4.2 Recommended Wire Gauge
1. V5in to J22(5V input):
The recommended wire size is 1x AWG #18 per input connection, with the total length of wire less than
4 feet (2 feet input, 2 feet return).
2. 12VBAT to J21(12V input):
The recommended wire size is 1x AWG #16 per input connection, with the total length of wire less than
4 feet (2 feet input, 2 feet return).
3. J1, J2, J3(CPU) to LOAD or J4, J5 (GPU) to LOAD or J19 (VDDQ) to LOAD or J15(VCCIO) to
LOAD:
The minimum recommended wire size is 2x AWG #16, with the total length of wire less than 4 feet (2
feet output, 2 feet return)
4.3 Recommended Test Setup
Figure 4 is the recommended test set up to evaluate the TPS59650EVM-753.Working at an ESD
workstation, make sure that any wrist straps, bootstraps or mats are connected referencing the user to
earth ground before handling the EVM.
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Host Computer
B
USB Cable
A
CPU
V1
- +
5Vin DC
Source
+
-
V2
- +
A1
12VBAT DC
Source
+
-
-+++ --
Load
+
-
V3
+
-
VCCIO +
-
GPU
-
+
VDDQ
_
+
Test Setup www.ti.com
Figure 4. TPS59650EVM-753 Recommended Test Set Up
4.4 USB Cable Connections
A standard USB_A and 5 pin Mini_B USB cable needed to connect between host computer and J34 USB
port (left bottom side). A GREEN LED(D13) will light up near the USB port on the EVM. This just means
USB cable is connected.
4.5 Input Connections
1. Prior to connecting the 5Vin DC source, it is advisable to limit the source current from 5Vin to 1A
maximum. Make sure 5Vin is initially set to 0V and connected as shown in Figure 4.
2. Prior to connecting the 12VBAT DC source, it is advisable to limit the source current from 12VBAT to
10A maximum. Make sure 12VBAT is initially set to 0V and connected as shown in Figure 4.
3. Connect voltmeters V1 at TP81 (5Vin) and TP83 (GND) to measure 5Vin voltage, V2 at TP82 (VBAT)
and TP24 (GND) to measure 12VBAT voltage as shown in Figure 4.
4. Connect a current meter A1 between 12VBAT DC source and J21 to measure the 12VBAT input
current.
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4.6 Output Connections
1. Connect Load to J1, J2, J3 and set Load to constant resistance mode to sink 0Adc before 5Vin and
12VBAT are applied. This is for CPU operation.
2. Connect a voltmeter V3 at J7 to measure CPU Vcore sense voltage.
5 Configuration
All Jumper selections should be made prior to applying power to the EVM. User can configure this EVM
per following configurations.
5.1 CPU and GPU Configuration
5.1.1 CPU/GPU Current Limit Trip Selection (J10 for CPU and J12 for GPU)
The current limit trip can be set by J10(COCP) and J12(GOCP).
Default setting: Level 5 for both CPU and GPU.
Table 2. Current Limit Trip Selection
Jumper set to Connected Resistor COCP/GOCP Limit (Typ.)
Left (1-2 pin shorted) 150k Max
2nd(3-4 pin shorted) 100k Level 7
3rd(5-6 pin shorted) 75k Level 6
4th(7-8 pin shorted) 56.2k Level 5
5th(9-10 pin shorted) 39.2k Level 4
6th(11-12 pin shorted) 30.1k Level 3
7th(13-14 pin shorted) 24.3k Level 2
Right(15-16 pin shorted) 20.0k Min
5.1.2 CPU Frequency Selection (J11)
The operating frequency can be set by J11
Default setting: 300 kHz for CPU
Table 3. CPU Frequency Selection
Jumper set to Connected Resistor CPU
Left (1-2 pin shorted) 150k 600 kHz
2nd(3-4 pin shorted) 100k 550 kHz
3rd(5-6 pin shorted) 75k 500 kHz
4th(7-8 pin shorted) 56.2k 450 kHz
5th(9-10 pin shorted) 39.2k 400 kHz
6th(11-12 pin shorted) 30.1k 350 kHz
7th(13-14 pin shorted) 24.3k 300 kHz
Right(15-16 pin shorted) 20.0k 250 kHz
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5.1.3 GPU Frequency Selection (J13)
The operating frequency can be set by J13
Default setting: 385 kHz for GPU.
Table 4. GPU Frequency Selection
Jumper set to Connected Resistor GPU
Left (1-2 pin shorted) 150k 660 kHz
2nd(3-4 pin shorted) 100k 605 kHz
3rd(5-6 pin shorted) 75k 550 kHz
4th(7-8 pin shorted) 56.2k 495 kHz
5th(9-10 pin shorted) 39.2k 440 kHz
6th(11-12 pin shorted) 30.1k 385 kHz
7th(13-14 pin shorted) 24.3k 330 kHz
Right(15-16 pin shorted) 20.0k 275 kHz
5.1.4 F2808 DSP Program Mode Selection (J39)
The F2808 DSP Program Mode(GUI) Selection can be set by J39.
Default setting: No Jumper shorts on J39 for normal operation
Table 5. F2808 DSP Program Mode Selection
Jumper set to Program Mode Selection
No Jumper on J39 Normal Operation
Jumper on J39 Flash the DSP program to the EVM
5.1.5 5Vin Bias Voltage Option (J33)
The 5Vin Bias Voltage can be used from USB or Externally
Default setting: No Jumper shorts on J33
Table 6. 5Vin Bias Voltage Option (J33)
Jumper set to Selection
No Jumper 5Vin Bias from J22 external
Jumper on J39 5Vin Bias from USB, 5Vin from J22 should not be connected
5.1.6 On Board Dynamic Load Selection (S3 for CPU, S2(upper) for GPU, S2(lower) for VCCIO)
The on board dynamic load can be set by S2 and S3.
Default setting: Push S2 and S3 to “OFF” position to disable the on board dynamic load
Table 7. On Board Dynamic Load Selection
Switch set to Dynamic Load Selection
Push S3 to “ON” position Enable 32A on board dynamic load at CPU
Push S3 to “OFF” position Disable 32A on board dynamic load at CPU
Push S2(upper) to “ON” position Enable 19A on board dynamic load at GPU
Push S2(upper) to “OFF” position Disable 19A on board dynamic load at GPU
Push S2(lower) to “ON” position Enable 10A on board dynamic load at VCCIO
Push S2(lower) to “OFF” position Disable 10A on board dynamic load at VCCIO
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5.1.7 IMVP-7 VR_ON Enable Selection (S4)
The IMVP-7 CPU/GPU can be enabled and disabled by S4
Default setting: Push S4 to “OFF” position to disable both CPU and GPU
Table 8. VR_ON Enable Selection
Switch set to VR_ON Selection
Push S4 to “ON” position Enable IMVP-7 CPU/GPU Vcore
Push S4 to “OFF” position Disable IMVP-7 CPU/GPU Vcore
5.2 1.2VDDQ, 0.6V VTT and 0.6V VTTREF Configuration
5.2.1 VDDQ S3, S5 Enable Selection
The controller can be enabled and disabled by J18 and J17.
Default setting: Jumper shorts on Pin2 and Pin3 of J18,
Def ault setti ng : Jumper shorts on Pin2 and Pin3 of J17
Table 9. VDDQ S3, S5 Enable Selection
State J17 (S3) set to J18(S5) set to VDDQ VTTREF VTT
S0 ON position ON position ON ON ON
S3 OFF position ON position ON ON OFF(High-Z)
S4/S5 OFF position OFF position OFF(Discharge) OFF(Discharge) OFF(Discharge)
5.3 1.05V VCCIO Configuration
5.3.1 1.05V Enable Selection (S1)
1.05V Enable can be set by S1
Default setting: Push S1 to ”OFF” position
Table 10. 1.05V Enable Selection
Jumper set to Selection
Push S1 to “ON” position 1.05V Enabled
Push S1 to “OFF” position 1.05V Disabled
5.3.2 VCCIO Output Voltage Selection (J14)
The VCCIO Output Voltage can be selected by J14
Default setting: Jumper shorts Pin1 and Pin2 of J14
Table 11. VCCIO Output Voltage Selection
Jumper set to Selection
Jumper shorts on Pin1 and Pin2 VCCIO: 1.05V
Jumper shorts on Pin2 and Pin3 VCCIO: 1.00V
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5.3.3 On Board Dyanamic Load Enable Pin (J23)
The on board dynamic load can be enabled or disabled by J23
Default setting: Jumper shorts on J23
Table 12. On Board Dynamic Load Enable/Disable selection
Jumper set to Selection
Jumper shorts Enable on board dynamic load
No Jumper short Disable on board dynamic load
6 Test Procedure
6.1 Line/Load Regulation and Efficiency Measurement Procedure
6.1.1 CPU
1. Set up EVM as described in Section 4.3 through Section 4.6 and Figure 4.
2. Ensure J39 no Jumper shorts on
3. Ensure all other Jumpers configuration setting by Section 5 before 5Vin and 12VBAT are applied.
4. Ensure Load is set to constant resistance mode and to sink 0Adc
5. Ensure S1 and S4 are in “OFF” position
6. Add scope probe on the TP30 for CPU Vcore ripple measurement
7. Ensure USB Cable is connected between host computer and USB port(J34) on the EVM
8. Increase 5Vin from 0V to 5V. Using V1 to measure 5Vin input voltage.
9. Increase 12VBAT from 0V to 12V. Using V2 to measure 12VBAT input voltage.
10. Double-Click the icon to launch the GUI program. The GUI window shown in Figure 5.
11. Push S4 to “ON” position to enable the VR_ON of TPS59650. VR_ON LED will light up.
12. Now the user is ready to send SVID commends. The GUI at start-up defaults:
Address: 00 CPU, Commend: SetVIDslow, Payload: 1.05V (The user can select the SVID commend by
using the pull-down menu”)
13. Click “send Commend” and CPU CPGOOD LED will light up, See the GUI window as Figure 5.
14. Measure V3: CPU Vcore at J7 and A1: 12VBAT input current
15. Vary CPU LOAD from 0Adc to 94Adc, CPU Vcore must remain in load line
16. Vary 12VBAT from 9V to 20V CPU Vcore must remain in line regulation
17. Push S4 to “OFF” position to disable CPU Vcore controller.
18. Decrease LOAD to 0A and disconnect the LOAD from terminal J1, J2, J3
19. Disconnect V3 from J7.
20. Disconnect scope probe from TP30
14 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896–March 2012
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www.ti.com Test Procedure
Figure 5. TPS59650EVM-753 CPU GUI set up Window
6.1.2 GPU
1. Connect the LOAD to GPU terminal J4, J5 and V3 at J9. Ensure correct polarity.
2. Add scope probe on the TP46 for GPU Vcore_G ripple measurement
3. Push S4 to “ON” position to enable the VR_ON of TPS59650. The VR_ON LED will light up.
4. Now you are ready to send SVID commends for GPU. Using pull-down menu:
Address: 01 GPU, Commend: SetVIDslow, Payload: 1.23V
5. Click “send Commend” and GPU GPOOD LED will light up, See the GUI window as Figure 6.
15
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Test Procedure www.ti.com
Figure 6. TPS59650EVM-753 GPU GUI set up Window
6. Measure V3: GPU Vcore_G at J9 and A1: 12VBAT input current
7. Vary GPU LOAD from 0Adc to 50Adc, GPU Vcore must remain in load line
8. Vary 12VBAT from 9V to 20V GPU Vcore must remain in line regulation
9. Push S4 to “OFF” position to disable GPU Vcore controller.
10. Decrease LOAD to 0A and disconnect the LOAD from terminal J11
11. Disconnect V3 from J9.
12. Disconnect scope probe from TP46
13. Exit SVID GUI window: click File →click Exit
14. Disconnect the USB cable between host Computer and EVM
16 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896–March 2012
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www.ti.com Test Procedure
6.1.3 VDDQ
1. Connect the LOAD to VDDQ terminal J19 and V3 at J20. Ensure correct polarity.
2. Remove Jumper from J17, J18 from pin2 and pin3 and put this Jumper on pin1 and pin 2 of J18, J17
to enable S5 of VDDQ controller. VDDQ PGOOD LED will light up.
3. Measure V3: VDDQ at J20 and A1: 12Vin input current
4. Vary VDDQ LOAD from 0Adc to 8Adc, VDDQ must remain in the load regulation
5. Vary 12VBAT from 9V to 20V, VDDQ must remain in the line regulation
6. Remove Jumper of J17, J18 and shorts back on pin2 and pin3 of J17, J18 to disable VDDQ controller.
7. Decrease LOAD to 0A and disconnect the LOAD from terminal J19
8. Disconnect V3 from J20.
6.1.4 VCCIO
1. Connect the LOAD to VCCIO terminal J15 and V3 at J16. Ensure correct polarity.
2. Push S1 to “ON” position to enable the VCCIO controller. VCCIO EN and PGOOD LED will light up.
3. Measure V3: VCCIO at J16 and A1: 12Vin input current
4. Vary VDDQ LOAD from 0Adc to 10Adc, VCCIO must remain in the load regulation
5. Vary 12VBAT from 9V to 20V, VCCIO must remain in the line regulation
6. Push S1 to “OFF” position to disable VCCIO controller.
7. Decrease LOAD to 0A and disconnect the LOAD from terminal J15
8. Disconnect V3 from J16.
6.2 Equipment Shutdown
1. Shut down Load
2. Shut down 12VBAT and 5Vin
3. Shut down oscilloscope
4. Shut down host computer
17
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0.8
0.85
0.9
0.95
1
1.05
1.1
V - Output Voltage - V
O
0 10 20 30 40 50 60 70 80 90 100
I - Output Current - A
O
V = 12 V
IN
V = 20 V
IN
V = 9 V
IN
SPEC(min)
SPEC(nom)
SPEC(max)
65
70
75
80
85
90
95
Efficiency - %
0 10 20 30 40 50 60 70 80 90 100
I - Output Current - A
O
V = 12 V
IN
V = 20 V
IN
V = 9 V
IN
TPS59650EVM
CPU VR_ON Turn off
Test condition: 12 Vin, 1.05V/60A
CPU 3 Phase operation
CH4: CPGOOD
CH1: CSW1
CH2: CSW2
CH3: 1.05V core
TPS59650EVM
CPU VDIO Turn on
Test condition: 12 Vin, 1.05V/60A
CPU 3 Phase operation
CH1: CSW1
CH2: CSW2
CH3: 1.05V core
CH4: CPGOOD
Performance Data and Typical Characteristic Curves www.ti.com
7 Performance Data and Typical Characteristic Curves
Figure 7 through Figure 91 present typical performance curves for TPS59650EVM-753. Jumpers set to
default locations, see section 6 of this user’s guide.
7.1 CPU 3-Phase Operation
Figure 7. CPU3 Efficiency Figure 8. CPU3 Load regulation
Figure 9. CPU3 Enable Turn on Figure 10. CPU3 Enable Turn off
18 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896–March 2012
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Test condition: 12 Vin, 1.05V/60A
CPU 3 Phase operation
CH1: CSW1
CH2: CSW2
TPS59650EVM
CPU Switching node and Output Ripple
CH3: CSW3
CH4: 1.05V core Ripple
TPS59650EVM
CPU Dynamic VID: Set VID-Slow/Slow
Test condition: 12 Vin, 1.05V/1A
CPU 3 Operation
CH4: VDIO
CH1: CSW1
CH2: CSW2
CH3: 1.05V core
Test condition: 12 Vin, 1.05V/1A
CPU 3 Operation
CH4: VDIO
CH1: CSW1
CH2: CSW2
CH3: 1.05V core
TPS59650EVM
CPU Dynamic VID: Set VID-Fast/fast
TPS59650EVM
CPU Dynamic VID: Set VID-Decay/Fast
Test condition: 12 Vin, 1.05V/1A
CPU 3 Operation
CH4: VDIO
CH1: CSW1
CH2: CSW2
CH3: 1.05V core
www.ti.com Performance Data and Typical Characteristic Curves
Figure 11. CPU3 Switching Node(Ripple) Figure 12. CPU3 Dynamic VID: SetVID-Slow/Slow
Figure 13. CPU3 Dynamic VID:SetVID-Fast/Fast Figure 14. CPU3 Dynamic VID:SetVID-Decay/Fast
19
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CH1: CSW1
CH2: CSW2
TPS59650EVM
CPU Output Load Releas with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
CH3: CSW3
CH4: 1.05V core
TPS59650EVM
CPU Output Load Insertion with
OSR/USR middle level
Test condition: 12 Vin, 1.05V/0A-51A
CPU 3 Phase on board dynamic load
CH1: CSW1
CH2: CSW2
CH4: 1.05V core
CH3: CSW3
Performance Data and Typical Characteristic Curves www.ti.com
Figure 15. CPU3 Output Load Insertion with OSR/USR Figure 16. CPU3 Output Load Release with OSR/USR
middle level middle level
Figure 17. CPU3 Bode Plot at 12Vin, 1.05V/60A
Test condition: CPU3 12Vin, 1.05V/60A no airflow
20 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896–March 2012
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