Texas Instruments AM62-SIP SK Series User manual

EVM User's Guide: SK-AM62-SIP
AM62x-SIP SK Evaluation Module
Description
The SK-AM62-SIP starter kit (SK) evaluation module
(EVM) is a stand-alone test and development platform
built around the AM6254 system-on-a-chip (SoC)
with integrated 512MB LPDDR4 SDRAM in a single
package. AM625SIP processors are comprised of a
quad-core 64-bit Arm®-Cortex®-A53 microprocessor
and single-core Arm Cortex-M4F MCU.
SK-AM62-SIP allows the user to experience a dual-
display feature with 3D GPU through high-definition
multimedia interface (HDMI) over dots per inch (DPI)
and low-voltage differential signaling (LVDS), as well
as industrial communication applications using serial,
Ethernet, USB and other interfaces.
Get Started
1. Order the EVM at SK-AM62-SIP.
2. Download the EVM design files.
3. Download the reference software for many
applications from AM62x Development Portal.
4. The EVM Users Guide is here.
Features
• USB-C powered standalone mode of operation
• Power optimized discrete DC-DC power
management
• Onboard XDS110 JTAG interface with USB
connectivity for code development and debugging
• Onboard 32 GB eMMC memory and 512 Mb OSPI
NOR Flash
• 2x RGMII RJ45 connectors
• 2x USB 2.0 on type A and type C connectors
• Test automation interface through XDS110
• Expansion econnectors to access the interfaces
• M.2 connector for Wi-Fi/BT module
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1 Evaluation Module Overview
1.1 Introduction
This technical User’s Guide describes the hardware architecture of the SK-AM62-SIP EVM, a low cost Starter
Kit built around the AM62x SIP SoC. The AM62x SIP processor comprises of a Quad-Core 64-bit Arm®-Cortex®
A53 microprocessor, Single-core Arm Cortex-R5F MCU and an Arm Cortex-M4F MCU.
SK-AM62-SIP includes high-security field-securable (HS-FS) silicon to optionally customize keys and encryption
for security applications.
SK-AM62-SIP can be used for display applications (for example, human machine interface (HMI) and control
panel) with either an HDMI display and an external LVDS panel, up to 2K 60fps resolution. The powerful Arm
performance of quad-A53 at 1.4 GHz with rich industrial interfaces, offers good control and communication
capabilities for a wide range of applications, such as programmable logic controllers (PLC), automation control,
gateway, EV charging, medical, or building automation systems.
1.2 Kit Contents
• SK-AM62-SIP EVM
• EVM user guide pamphlet
• EVM disclaimer and standard terms
1.3 Specification
The figure below shows the functional block diagram of the AM62x SIP SK EVM.
Figure 1-1. Functional Block Diagram of AM62x SIP SK EVM
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1.4 Device Information
In addition, SK-AM62-SIP can communicate with other processors or systems and act as a communication
gateway. SK-AM62-SIP can directly operate as a standard remote I/O system or simple sensor connected to an
industrial communication network.
The embedded emulation logic allows for emulation and debugging using standard development tools such as
the Code Composer Studio™ integrated development environment (IDE) (CCSTUDIO). Reference software for
many applications can be downloaded from AM62x Development Portal.
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2 Hardware
2.1 Additional Images
This section shows the EVM pictures and the location of various blocks on the board.
Figure 2-1. EVM Top Side
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Figure 2-2. EVM Bottom Side
2.2 Key Features
The AM62x SIP SK EVM is a high performance, standalone development platform that enable users to evaluate
and develop industrial applications for the Texas Instrument's AM62x SIP System-on-Chip (SoC).
The following sections discuss the SK EVM's key features.
2.2.1 Processor
• AM62x SIPSoC, 13 mm x 13 mm, 0.5 mm pitch, 425‐pin VCA FBGA
2.2.2 Power Supply
• Two USB Type-C ports (5 V‐15 V input range)
• Optimized power solution with discrete regulators and LDOs for the processor and peripherals
2.2.3 Memory
• MicroSD Card slot with UHS-1 support
• 512MbitOctal SPI Flash memory
• 512Kbit Inter-Integrated Circuit (I2C) board ID EEPROM
• 32GBeMMC Flash with HS-400 support
2.2.4 JTAG/Emulator
• XDS110 On-Board Emulator
• Supports20-pin JTAG connection from external emulator
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2.2.5 Support Interfaces and Peripherals
• 1xUSB2.0 Type C interface, support DFP and UFP roles
• 1xUSB2.0 Host interface, Type A
• 1xHDMI interface
• Audio line in and mic + headphone out
• M.2 Key E interface support for both Wi-Fi and Bluetooth modules
• 2x Gigabit Ethernet ports supporting 10/100/1000 Mbps data rate on two RJ45 connectors
• Quadport UART to USB circuit over microB USB connector
• Industrial ethernet LEDs
• INA devices for current monitoring
• 1x Temperature sensor near SoC for thermal monitoring
2.2.6 Expansion Connectors/Headers
• CSI Camera Header
• LVDS Display connector
• User Expansion connector
• PRU Header
• MCU Header
2.3 Interface Mapping
Table 2-1. Interface Mapping
Interface Name Port on SoC Device Part Number
Memory – OSPI OSPI0 S28HS512TGABHM010
Memory – Micro SD Socket MMC1 MEM2051-00-195-00-A
Memory – eMMC MMC0 MTFC32GAZAQHD-IT
Memory – Board ID EEPROM SoC_I2C0 AT24C512C-MAHM-T
Ethernet 1 – RGMII SoC_RGMII1 DP83867IRRGZ
Ethernet 2 – RGMII SoC_RGMII2 DP83867IRRGZ
LED Driver – 8 Communication LEDs WKUP_I2C0 TPIC2810D
PRU Header – 2x10 HDR PR0_PRU0_GPO and SoC_I2C0 PREC010DAAN-RC
User Expansion Connector – 2x20 HDR SPI0, SPI2, UART5, SoC_I2C0, SoC_I2C2
and GPIOs
PEC20DAAN
MCU Header – 2x14 HDR MCU_UART0,MCU_MCAN0, MCU_SPI0,
MCU_I2C0 and MCU GPIOs
PREC014DAAN-RC
USB– 2.0 Type C USB0 2012670005
USB– 2.0 Type A USB1 629104151021
LVDS Display Connector OLDI0 FFC2A32-40-T
CSI Interface CSI0 1-1734248-5
HDMI VOUT0 SiI9022ACNU + TPD12S016PWR
[phone]RLF
AudioCodec McASP2and SoC_I2C1 TLV320AIC3106IRGZT+ SJ-43514-SMT
GPIO Port Expander SoC_I2C1 TCA6424ARGJR
UART Terminal (UART-to-USB) SoC_UART[1:0], WKUP_UART0 and
MCU_UART0
FT4232HL+ 629105150521
Test Automation Header SoC_I2C1 FH12A-40S-0.5SH
Temperature Sensor SoC_I2C1 TMP100NA/3K
Current Monitors SoC_I2C1 INA231AIYFDR
Connectivity– M.2 Key E MMC2, McASP1 and SoC_UART1 2199119-4
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2.4 Power ON/OFF Procedure
Power to the EVM is provided through an external power supply providing PD voltage and current to the either of
the two USB Type-C Ports.
Note
The maximum length of the IO cables shall not exceed 3 meters.
2.4.1 Power ON Procedure
1. Place the SK EVM boot switch selectors (SW1, SW2) into selected boot mode. Example boot-modes for
SDcard and no-boot are shown below.
2. Connect your boot media (if applicable).
3. Attach the PD capable USB Type-C cable to the SKEVM Type-C (J11 or J13) Connector.
4. Connect the other end of the Type-C cable to the source, either AC Power Adapter, or Type C source device
(such as a Laptop computer).
5. Visually inspect that either LD10 or LD12 LED are illuminated.
6. XDS110JTAG and UART debug console output are routed to micro-USB ports J16 and J15, respectively.
Figure 2-3. SD Boot Mode Switch Setting Example
2.4.2 Power OFF Procedure
1. Disconnect AC power from AC/DC converter.
2. Remove the USB Type-C cable from the SK EVM.
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2.4.3 Power Test Points
Test points for each power output on the board is mentioned in the table below.
Table 2-2. Power Test Points
S.No Power Supply Test Point Voltage
1 VBUS_TYPEC1 C398.1 5V-15V
2 VBUS_TYPEC2 C415.1 5V-15V
3 VMAIN TP95 5V-15V
4 VCC_5V0 TP70 5 V
5 VCC_3V3_SYS TP51 3.3V
6 VDD_2V5 TP42 2.5V
7 VPP_1V8 TP31 1.8V
8 VDD_1V0 TP33 1.0V
9 VDD_1V2 TP10 1.2V
10 VDDA1V8 TP36 1.8V
11 VCC_1V8 TP41 1.8V
12 VDDSHV_SDIO TP29 1.8V/3.3V
13 VCC1V1_DDR TP40 1.1V
14 VCC_CORE TP45 0.85V
15 VDD_CORE TP46 0.85V
16 VCC3V3_TA TP87 3.3V
17 VCC3V3_XDS TP77 3.3V
18 VCC_3V3_FT4232 C482.1 3.3V
2.5 Clocking
The figure below shows the clocking architecture of the AM62x SIP SK EVM.
Figure 2-4. Clock Architecture
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A clock generator of part number LMK1C1103PWR is used to drive the 25 MHz clock to the SoC and two
Ethernet PHYs. LMK1C1103PWR is a 1:3 LVCMOS clock buffer, which takes the 25 MHz crystal/LVCMOS
reference input and provides three 25 MHz LVCMOS clock outputs. The source for the clock buffer shall be
either the CLKOUT0 pin from the SoC or a 25 MHz oscillator; the selection is made using a set of resistors. By
default, an oscillator is used as input to the clock buffer on the AM62x SIP SKEVM. Output Y2 and Y3 of the
clock buffer are used as reference clock inputs] for two Gigabit Ethernet PHYs.
There is one external crystal attached to the AM62x SIP SoC to provide clock to the WKUP domain of the SoC
(32.768 KHz).
Figure 2-5. SoC WKUP Domain
2.5.1 Peripheral Ref Clock
Clock inputs required for peripherals such as XDS110, FT4232, HDMI Transmitter and Audio Codecare
generated locally using separate crystals or oscillators. Crystals or Oscillators used to provide the reference
clocks to the EVM peripherals are shown in the table below.
Table 2-3. Clock Table
Peripheral Mfr. Part Number Description Frequency
XDS110 Emulator XRCGB16M000FXN01R0 CRY 16.000MHz 8 pF SMD 16.000MHz
FT4232 Bridge ECS-120-18-30B-AGN-TR CRY12.000 MHz 18 pF SMD 12.000MHz
Audio Codec KC2520Z12.2880C1KX00 OSC12.288 MHz CMOS SMD 12.288MHz
HDMI Transmitter KC2520Z12.2880C1KX00 OSC12.288 MHz CMOS SMD 12.288MHz
The clock required by the HDMI Transmitter can be provided by either the on board oscillator or the SoC’s
AUDIO_EXT_REFCLK1, which can be selected through a resistor mux. SoC’s EXT_REFCLK1 is used to
provide clock to the User Expansion Connector on the SKEVM. The 32.768 KHz clock to the M.2 module is
provided by WKUP_CLKOUT0 of AM62x SIP SoC through a voltage translational buffer.
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2.6 Reset
The Reset Architecture of AM62x SIP SK EVM is shown below.
The SoC has following resets:
• RESETSTATz is the Main domain warm reset status output
• PORz_OUT is the Main domain power ON reset status output
• RESET_REQz is the Main domain warm reset input
• MCU_PORz is the MCU domain power ON/ Cold Reset input
• MCU_RESETz is the MCU domain warm reset input
• MCU_RESETSTATz is the MCU domain warm reset status output
Upon Power on Reset, all peripheral devices connected to the main domain get reset by RESETSTATz.
Figure 2-6. Reset Architecture
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2.7 CSI Interface
The CSI-2 interface from the AM62x SIP SoC is terminated to a 15 pin Camera FPC connector 1-1734248-5
compatible with the RPi Camera Modules. These modules support 2 Lane CSI RX signals. While the SoC
supports 4 CSI RX Lanes, only two are pinned out on the SK EVM.
The CSI connector pin-out is compatible with the RPi camera connector. The below table shows 15 pin CSI
Connector pin-out. SoC I2C2 signals are also connected to the CSI Header. IO Expander GPIO signals are
connected to the camera GPIO’s.
Figure 2-7. CSI Interface
Table 2-4. CSI Camera Connector J19 Pinout
Pin No. Pin Description
1 GND
2 CSI0_RXN0
3 CSI0_RXP0
4 GND
5 CSI0_RXN1
6 CSI0_RXP1
7 GND
8 CSI0_RXCLKN
9 CSI0_RXCLKP
10 GND
11 CSI_GPIO1
12 CSI_GPIO2
13 CSI_I2C2_SCL
14 CSI_I2C2_SDA
15 VCC_3V3_SYS
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2.8 Audio Codec Interface
AM62x SIP SK EVM has TI‘s Low-Power TLV320AIC3106 Stereo Audio Codec to interface with AM62x SIP via
McASP.
TLV320AIC3106 is a low-power stereo audio codec with stereo headphone amplifier, as well as multiple
inputs and outputs programmable in single ended or fully differential configurations. The record path of the
TLV320AIC3106 contains integrated microphone bias, digitally controlled stereo microphone preamplifier and
automatic gain control (AGC) with mix/Mux capability among the multiple analog inputs. The stereo audio DAC
supports sampling rates from 8 kHz to 96 kHz.
1xStandard 3.5 mm TRRS Audio Jack connector Mfr. Part# SJ-43514 shall be provided for MIC and Headphone
output. Audio Codec’s Line inputs are terminated to Test points.
SELECT pin shall be held LOW to select I2C as control interface. Codec can be configured over I2C interface,
where I2C address can be set by driving pins MFP0 and MFP1 pin either high or low. Both these pins are set
to high, so the Device address is set to 0x1B. Unused inputs and outputs of the Audio Codec are connected to
ground.
The Controller Clock input, MCLK to the Audio Codec is provided through a 12.288MHz Oscillator. Audio serial
data bus bit clock BCLK of the codec is driven by the AM62x SIP SoC through a buffer. Audio serial data bus
input and output DIN, DOUT are connected to SoC’s MCASP1_AXR0 and MCASP1_AXR2 through buffers. An
AND output of RESETSTATz and a GPIO sourced via IO expander are used to reset the Audio codec.
TheTLV320AIC3106 is powered by an analog supply of 3.3 V, a digital core supply of 1.8 V, and a digital I/O
supply 3.3 V.
Figure 2-8. Audio Codec Interface
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2.9 HDMI Display Interface
The DSS (Display Sub system) interface from AM62x SIP SoC is used on the SKEVM to provide a HDMI
Interface through a standard Type-A Connector. The SKEVM features a SiI9022A HDMI Transmitter from Lattice
semiconductors to convert the 24-bit Parallel RGB DSS output stream as well as a McASP to a HDMI-compliant
digital audio and video signal.
The Data mapping format used is RGB888. The data bus width is 24-bits.
SoC_I2C1 is connected to the HDMI Transmitter to access the compatible mode registers, the TPI registers,and
the CPI registers. To use the SiI9022A, the SoC needs to set up the device by the I2C interface between
the SoC and the SiI9022A. Audio Data is sent from SoC to HDMI transmitter through the McASP1 instance.
HDMI_I2C Bus accesses the EDID and HDCP data on an attached sink device.
TMDS Differential data pairs along with the differential clock signals from the transmitter are connected to the
HDMI connector through HDMI ESD device Mfr Part# TPD12S016PWR which also acts as a load switch to limit
current supplied to the HDMI connector from board 5 V supply.
The HDMI Framer is powered using 3.3 V Board IO Supply and 1.2 V by a dedicated LDO Mfr Part#-
TLV75512PDQNR.
Figure 2-9. HDMI Interface
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2.10 JTAG Interface
AM62x SIP SK EVM board include XDS110 class on board emulation. The connection for the emulator uses
an USB 2.0 micro-B connector and the circuit act as a bus-powered USB device. The VBUS power from the
connector is used to power the emulation circuit so that connection to the emulator is not lost when the power to
the SK EVM is removed. Voltage translation buffers are used to isolate the XDS110 circuit from the rest of the
SK EVM.
Optionally, JTAG Interface on SK EVM is also provided through 20 Pin Standard JTAG cTI Header J17. This
allows the user to connect an external JTAG Emulator Cable. Voltage translation buffers are used to isolate
the JTAG signals from cTI header from the rest of the SK EVM. The output from the voltage translators
from XDS110 Section and cTI Header Section are muxed and connected to AM62x SIP JTAG Interface. If a
connection to the cTI 20 Pin JTAG connector is sensed using a presence detect circuit, then the mux is set to
route the 20 pin signals from the cTI connector to the AM62x SIP SoC in place of the on-board emulation circuit.
Figure 2-10. JTAG Interface
The pin-outs of the cTI 20 pin JTAG connector are given in the table below. An ESD-protection part number
TPD4E004 is provided on USB signals to steer ESD current pulses to VCC or GND. TPD4E004 protects against
ESD pulses up to ±15-kV Human-Body Model (HBM) as specified in IEC 61000-4-2 and provides ±8-kV contact
discharge and ±12- kV air-gap discharge.
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Table 2-5. JTAG Connector (J17) Pin-Out
Pin No. Signal
1 JTAG_TMS
2 JTAG_TRST#
3 JTAG_TDI
4 JTAG_TDIS
5 VCC3V3_SYS
6 NC
7 JTAG_TDO
8 SEL_XDS110_INV
9 JTAG_cTI_RTCK
10 DGND
11 JTAG_cTI_TCK
12 DGND
13 JTAG_EMU0
14 JTAG_EMU1
15 JTAG_EMU_RSTn
16 DGND
17 NC
18 NC
19 NC
20 DGND
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2.11 Test Automation Header
AM62x SIP SK EVM has a 40-pin test automation header (FH12A-40S-0.5SH) to allow an external controller to
manipulate some basic operations like Power Down, POR, Warm Reset, Boot Mode control, and so forth.
The Test Automation Circuit is powered by the 3.3 V supply generated by a dedicated regulator Mfr.
Part# TPS62177DQCR. The SoC’s I2C1 is connected to the test automation header. Another I2C instance
(BOOTMODE_I2C) from the Test Automation Header is connected to the 24-bit I2C boot mode IO Expander of
Mfr. Part# TCA6424ARGJR to allow control of the boot modes for the AM62x SIP SoC.
The test automation circuit has voltage translation circuits so that the controller is isolated from the IO voltages
used by the AM62x SIP. Boot mode for the AM62x SIP must be controlled by either the user using DIP Switches
or the test automation header through the I2C IO Expander. Boot Mode Buffers are used to isolate the Boot
Mode controls driven through DIP Switches or I2C IO Expander. The boot mode is controlled by the user using
two 8-bit DIP switches on the board, which connects a pull-up resistor to the output of a buffer when the switch
is set to the ON position and to weaker pull-down resistor when set to the OFF position. The output of the buffer
is connected to the boot mode pins on the AM62x SIP SoC and the output is enabled when the boot mode is
needed during a reset cycle.
When boot mode is to be set through Test Automation header, the required switch values are set at the I2C IO
expander output, which overwrites the DIP switch values to give the desired boot values to the SoC. The pins
used for boot mode also have other functions which is isolated by disabling the boot mode buffer during normal
operation.
The power down signal from the Test automation header instructs the SK EVM to power down all the rails except
for dedicated power supplies on the board. Similarly PORZn signal is also provided to give a hard reset to the
SoC and WARM_RESETn for warm reset of the SoC. One Interrupt signal from the Test Automation header is
routed to the SoC GPIO (GPIO1_23) to provide an external Interrupt.
Figure 2-11. Test Automation
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Table 2-6. Test Automation Connector (J23) Pin-Out
Pin No. Signal IO Direction Pin No. Signal IO Direction
1 VCC3V3_TA Power 21 NC NA
2 VCC3V3_TA Power 22 NC NA
3 VCC3V3_TA Power 23 NC NA
4 NC NA 24 NC NA
5 NC NA 25 DGND Power
6 NC NA 26 TEST_POWERDOW
N
Input
7 DGND Power 27 TEST_PORz Input
8 NC NA 28 TEST_WARMRESET
n
Input
9 NC NA 29 NC NA
10 NC NA 30 TEST_GPIO1 Bidirectional
11 NC NA 31 TEST_GPIO2 Bidirectional
12 NC NA 32 TEST_GPIO3 Input
13 NC NA 33 TEST_GPIO4 Input
14 NC NA 34 DGND Power
15 NC NA 35 NC NA
16 DGND Power 36 SoC_I2C1_TA_SCL Bidirectional
17 NC NA 37 BOOTMODE_I2C_S
CL
Bidirectional
18 NC NA 38 SoC_I2C1_TA_SDA Bidirectional
19 NC NA 39 BOOTMODE_I2C_S
DA
Bidirectional
20 NC NA 40 DGND Power
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2.12 UART Interface
The four UART ports of the SoC (MCU UART0, WKUP UART0, SoC UART0 and SoC UART1) provided by
the AM62x SIP are interfaced with an FTDI FT4232HL for UART-to-USB functionality and terminated on a USB
micro-B connector (J15) on board. When the AM62x SIP SKEVM is connected to a Host using USB cable, the
computer can establish a Virtual COM Port which can be used with any terminal emulation application. The
FT4232HL is bus powered.
Since the circuit is powered through BUS power, the connection to the COM port is not lost when the SKEVM
power is removed.
Table 2-7. UART Port Interface
UART Port USB to UART Bridge USB Connector COM Port
SoC_UART0
FT4232HL J15
COM1
SoC_UART1 COM2
WKUP_UART0 COM3
MCU_UART0 COM4
The FT4232 chip is configured to operate in Single chip USB to four channel UART mode and takes the
configuration file from the external SPI EEPROM connected to the FT4232 chip. The EEPROM (93LC46B)
supports 1Mbit/s clock rate. The EEPROM is programmable in-circuit over USB using a utility program called
FT_PROG available from the FTDI web site. The FT_PROG is also used for programming the board serial
number for users to identify the connected COM port with board serial number when one or more boards are
connected to the computer.
Figure 2-12. UART Interface
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2.13 USB Interface
2.13.1 USB 2.0 Type A Interface
On SK EVM, USB 2.0 HOST Interface is offered through a Type-A Ports using Type-A Connector Mfr Part#
629104151021. USB1 Port of AM62x SIP SoC is used for USB 2.0 Type-A Host Interface.
USB Data lines from Type-A connectors are connected to the Current Limit Load Switch and ESD Protection IC
Mfr Part# TPD3S014DBVR. This switch limits the current to 500 mA and dissipates the ESD strikes above the
maximum level specified in the IEC 61000-4-2.
Figure 2-13. USB 2.0 Type A Interface
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2.13.2 USB 2.0 Type C Interface
On SK EVM, USB 2.0 Interface is offered through USB Type-C Connector J13 Mfr part# 2012670005, which
supports data rate up to 480Mbps. J13 is used for Data communication and also as power connector. J13 is
configured as DRP port using PD controller TPS65988DHRSHR IC, so J13 can act as either host or device. The
power role of the port depends on the type of the device getting connected on the connector and the ability to
either sink or source. When the port is acting as DFP, the port can source up to 5V@500mA.
A GPIO from the PD controller is connected to USB0_DRVVBUS pin of the SoC to indicate the data role of
the device connected to J13 Type-C connector. The GPIO is configured to output HIGH/LOW depending on the
HOST/ DEVICE behavior of the J13 connector.
USB2.0 Data lines DP and DM from J13 are connected to the USB0 interface of AM62x SIP SoC via choke and
ESD protection device. USB0_VBUS to the SoC is provided through a resistor divider network.
A common mode choke of Mfr Part# DLW21SZ900HQ2B is provided on USB Data lines to take care of EMI/
EMC. An ESD protection device of part number ESD122DMXR is included to dissipate ESD strikes on USB2.0
DP/DM Signals. An ESD protection device of part number TPD1E01B04DPLT is included on CC signals and
TVS2200DRVR IC is included on VBUS rail of Type-C Connector J13 to dissipate ESD strikes.
Figure 2-14. USB 2.0 Type C Interface
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