Texas Instruments TPS65291 EVM User manual

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TPS65291 EVM User's Guide
User's Guide
SLVUB61–July 2017
TPS65291 EVM User's Guide
The TPS65291EVM is an evaluation module (EVM) for the TPS65291 power management unit (PMU)
device, which is primarily used in gas and water meters. In addition to gas and water meters, the
TPS65291 device can be used in any low-power, portable industrial application powered from a single-cell
(1S) or dual-stacked (2S) Lithium-Ion (Li-Ion) battery.
This document provides a description of how to setup and configure the EVM for operation. This
document also includes hardware documentation, including the schematic, layout and bill of materials,as
well as software instructions for installing the IPG-UI graphical user interface (GUI).
Contents
1 Introduction (Board Overview) ............................................................................................. 2
2 Getting Started............................................................................................................... 3
Appendix A EVM Documentation.............................................................................................. 12
Appendix B Software Installation and Setup Instructions................................................................... 17
List of Figures
1 TPS65291EVM Printed Circuit Board (Top View) ...................................................................... 3
2 TPS65291EVM Block Diagram ........................................................................................... 4
3 TPS65291 Test Setup: Power Supply and Multi-meter Connections ................................................ 5
4 TPS65291EVM Split With Ribbon Cable Between USB2ANY and TPS65291 Sections .......................... 7
5 Successful Completion Read ALL Registers in IPG-UI ................................................................ 9
6 B2_Enreg is Enabled by Default in IPG-UI ............................................................................. 10
7 Enabling BUCK1 (B1_Enreg) in IPG-UI................................................................................. 10
8 Enabling LDO_SW (LDOnSW_Enreg) in IPG-UI ...................................................................... 11
9 Component Placement—Top Assembly ................................................................................ 12
10 Component Placement—Bottom Assembly ............................................................................ 12
11 Layout—Top Composite .................................................................................................. 12
12 Layout—Bottom Composite .............................................................................................. 12
13 Top Layer ................................................................................................................... 13
14 Bottom Layer (Top View).................................................................................................. 13
15 TPS65291EVM Schematic................................................................................................ 14
16 Run the IPG-UI Software ................................................................................................. 17
17 Successful Connection Between Computer and USB2ANY.......................................................... 17
18 Creating New IPG-UI Project for the TPS65291....................................................................... 18
19 Successful Write Access to TPS65291 Notification ................................................................... 18
20 Failed GUI Communication to TPS65291 Notification ................................................................ 18
21 TPS65291 SPI Project Introduction Tab in IPG-UI .................................................................... 19
List of Tables
1 TPS65291EVM Test Point List............................................................................................. 6
2 TPS65291EVM Jumper List ............................................................................................... 6
3 Bill of Materials ............................................................................................................. 15

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TPS65291 EVM User's Guide
Trademarks
MSP430 is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
1 Introduction (Board Overview)
The TPS65291EVM allows designers to evaluate the operation and performance of the TPS65291 PMU.
The TPS65291EVM is simple to test, requiring only a single power supply at the input, a USB cable
connected to a computer running the GUI, and a load at the output to measure performance. With no load
or a light load on the EVM, only the USB cable is required to power the TPS65291 device from the 5 V
provided by the VBUS wire of USB. The computer and GUI is used to communicate to the TPS65291
device through the SPI protocol.
The 50-mA BUCK2 output of the TPS65291 device is always-on, meaning it is enabled when an
adequately high voltage of at least 3.0 V is applied to the B2_VIN pin by a power supply. The performance
of BUCK2 can be measured without additional connections.
The 1-A BUCK1 output and the LDO_SW (configurable LDO or switch) output of the TPS65291 device
must be enabled by communicating to the TPS65291 device through SPI from a host controller. On the
EVM, an MSP430™ MCU is programmed as a USB2ANY device, and the SPI signals (CLK, MOSI, MISO,
and CS) are hard-wired to the TPS65291 device so that only a USB cable must be plugged into the EVM
to enable BUCK1 and LDO_SW. The B1_VIN pin can be shorted to the B2_VIN pin to provide power to
both DC-DC bucks.
The TPS65291EVM is perforated such that the printed circuit board (PCB) is split into two distinct
sections. The upper section, shown in Figure 1, contains the TPS65291 device, required passive
components, test points, and banana jacks for applying input power and loads. The lower section of the
PCB contains components not relevant to the evaluation of the TPS65291 device. Instead, the MSP430
MCU and other simple circuitry on this section of the PCB are used for communicating to the TPS65291
device through SPI and controlling the device from a computer with a USB cable.
If the two sections of the PCB are split apart, they can be connected by using a standard keyed 10-pin
ribbon cable with 2 rows by 5 pins and 100-mil pitch. The lower half is now a standard USB2ANY device
with SPI, I2C, 2 GPIOs, and a controllable 3.3-V output rail provided by a 150-mA LDO.

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Figure 1. TPS65291EVM Printed Circuit Board (Top View)
1.1 Related Documentation
Texas Instruments, TPS65291 High-Efficiency Solution for Multi-Stacked Battery Systems data sheet
1.2 TPS65291 Applications
The TPS65291 can be used in, but not limited to,the following applications:
• Low-power energy harvesting systems
• Battery powered applications
• Gas and water maters
• POL supply from single (1S) or dual (2S) Li-Ion batteries
• Higher-efficiency LDO replacement
2 Getting Started
Figure 2 shows the high-level block diagram of the TPS65291EVM, highlighting important integrated
circuits (ICs) and connections, the upper and lower sections of the PCB, and the interface between the
EVM and a computer.

Upper Section of PCB
Lower Section of PCB
MSP430F5529IPN
USB2ANY
(on-board)
P4.1
P4.2
MSP_3P3V
I2C_SDA
I2C_SCL
2.2 k 2.2 k
P4.0
P4.4
P4.5
P2.0
VBUS
PU.0
PU.1
VSS
P2.4
P1.2
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
10-Pin Header
CLK
MOSI
MISO
CS
GND
SDA
SCL
GPIO3
GPIO7
VBUS
D+
D-
GND
MSP_3P3V
USB_5V
AVCC
DVCC
3.3V MSP_3P3V
P7.6
3V3_EN
TPS76333
LDO
USB_5V USB_3P3V B2_VOUT
B1_VIN
TPS65291
PMU
B2_VIN B1_VIN
B1_LX
NC
VIN_MON
NC
B2_LX
LDO_SW_IN_B2_FB
PAD
LDO_SW_OUT
B1_PGND
B2_PGND_AGND
B1_FB
CLK
MOSI
MISO
CS
10-Pin Header
CLK
MOSI
MISO
CS
GND
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
B2_VIN
LDO_SW_OUT
VIN_MON
B2_VOUT B1_VOUT
USB_5V
VIN_MON
B2_VIN
B1_VIN
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Figure 2. TPS65291EVM Block Diagram
2.1 Power Connections
This section describes the banana jacks and screw terminals for applying input power to and delivering
output power from the TPS65291EVM.

DC POWER SUPPLY
CURRENT (A) VOLTAGE (V)
1.5 6.0
CURRENT
FINE COARSE FINE COARSE
VOLTAGE
MULTIMETER
2.8 V
DC
V
V
mV Ÿ
µA
mA
A
VŸ
COM
AmAµA
~
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NOTE: Banana jacks and screw terminals allow two different connection options for providing power
to or delivering power from the input and output pins of the TPS65291. For each power
connection, use either banana plugs or screwed-in wires; do not use both.
Figure 3 shows the test setup for applying power to both B1_VIN (J1) and B2_VIN (J2) on the
TPS65291EVM from a single power supply and measuring the output voltage B2_VOUT (J6) when power
is first applied.
Figure 3. TPS65291 Test Setup: Power Supply and Multi-meter Connections
J1 (B1_VIN) and J9 (GND), or J4 (pin 2 = B1_VIN, pin 1 = GND) — TheJ1 and J9 banana jacks and the
J4 screw terminal are for providing power to BUCK1 through the positive lead (+) of a power supply
and a return path to ground through the negative lead (–).
J2 (B2_VIN) and J9 (GND), or J5 (pin 1 = B2_VIN, pin 2 = GND) — TheJ2 and J9 banana jacks and the
J5 screw terminal are for providing power to BUCK2.
J6 (B2_VOUT) and J12 (GND), or J10 (pin 2 = B2_VOUT, pin 1 = GND) — TheJ6 and J12 banana
jacks and the J10 screw terminal are for attaching a load to draw power from BUCK2.
J11 (LDO_SW_VOUT) and J12 (GND), or J13 (pin 1 = LDO_SW_VOUT, pin 1 = GND) — TheJ11 and
J12 banana jacks and the J13 screw terminal are for attaching a load to draw power from
LDO_SW.

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J7 (B1_VOUT) and J14 (GND), or J8 (pin 1 = LDO_SW_VOUT, pin 1 = GND) — TheJ7 and J14 banana
jacks and the J8 screw terminal are for attaching a load to draw power from BUCK1.
2.2 Test Points
This section describes the test points located on the TPS65291EVM to measure the voltage of all pins of
the TPS65291 device. Table 1 lists the test points.
(1) Ground test points are labeled GND (except for TP15) and do not show TPxx on the silk-screen of the PCB.
(2) Headers used as test points are tin or gold-plated tin but do not have colored plastic and are designated Jxx instead of TPxx.
Table 1. TPS65291EVM Test Point List
PCB Reference Designator Color Type Net Name
TP1 Red Input power B2_VIN
TP2 Red Input power B1_VIN
TP3 Yellow Output power B2_VOUT
TP4 Yellow Output power B1_VOUT
TP5 Orange Data output VIN_MON
TP7 Red Input power LDO_SW_IN
TP8 Orange Data input CLK
TP10 Yellow Output power LDO_SW_OUT
TP11 Orange Data input MOSI
TP12 Orange Data output MISO
TP14 Orange Data input CS
TP6, TP9, TP13, TP15-TP18(1) Black Ground PGND, AGND, thermal pad
TP19 Metal (Surface Mount) MSP430 power rail USB_3P3V
J17(2) 3-Pin Header Input power B1_VIN (pin 1) Data output VIN_MON (pin 2)
Input power B2_VIN (pin 3)
J18 (2) Header MSP430 power output EXT_3V3
CAUTION
J17 does not allow for the installation of a shunt to short two pins together. The
center pin, VIN_MON, is an output that indicates a valid input supply on the
B1_VIN or B2_VIN pin. The B1_VIN and B2_VIN pins have Kelvin connections
routed to the J17 header and should be used for accurately measuring voltage
with an oscilloscope.
2.3 Jumpers
This section describes the jumper headers located on the TPS65291EVM for connecting nets of the PCB
together to perform various functions. Table 2 lists the jumpers.
Table 2. TPS65291EVM Jumper List
PCB Reference
Designator Pin Net Name Default Shunt Connection Description
J20
1 USB_3P3V Pins 1 and 2 Shorted Required to deliver 3.3-V rail to MSP430
and turn on LED D1
2 MSP_3P3V
3 B2_VOUT — Optional way to provide 3.3-V rail to
MSP430 from TPS65291 BUCK2
J3 1 USB_5V Not Installed Optional way to provide 5-V VBUS rail to
TPS65291 from USB
2 B2_VIN

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Table 2. TPS65291EVM Jumper List (continued)
PCB Reference
Designator Pin Net Name Default Shunt Connection Description
J15 1 LDO_SW_OUT Not Installed Optional light load on LDO_SW
2 GND
J22 1 PUR Not Installed Short to re-flash firmware to MSP430
2 VUSB
Figure 3 shows the required jumper installation on J20. Figure 4 shows J20 installed correctly.
2.4 Cable Connections
When the PCB is first taken out of the box, the only cable connection required is a Standard-A to micro-B
USB cable. Connect the micro-USB plug to J21 and the other end (standard-A plug) of the USB cable into
a USB2or USB3 port of a computer.
If the PCB is split into two sections so that the lower half can be used as a stand-alone USB2ANY, a
keyed 10-pin ribbon cable must be connected between J19 and J16 to control the TPS65291 device
through SPI. Figure 4 shows these connections.
Figure 4. TPS65291EVM Split With Ribbon Cable Between USB2ANY and TPS65291 Sections
WARNING
Do not split the PCB into two sections without protection.
Protective glasses and gloves should be worn. First, use wire
cutters to partially sever the connections between the two sections
on both top and bottom. Then, connect one end to a rigid surface
with a vice grip. Finally, grab the other end of the PCB firmly with
pliers and bend back and forth slowly until the two sections
separate.

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2.5 EVM Operation
This section describes the power-on procedure and the software instructions to enable BUCK1 and
LDO_SW. When these procedures are complete, a load can be applied in parallel to the multi-meter
shown in Figure 3.Probes can be placed on any test point in Table 1 to evaluate the full performance of
the TPS65291 device.
2.5.1 Power-On Procedure
After setting up the hardware to match the test setup shown in Figure 3, follow these instructions to verify
the voltage on the always-on BUCK2 rail:
• Set the input supply voltage to 6V and ensure it is off before connecting to the EVM.
• Connect the power supply return lead (the black cable) to the J9 header.
• Apply the input power lead (the red cable) to J1 and a jumper cable from J1 to J2.
• Ensure that the current limit on the supply is 1.5 A.
• Connect the voltage lead of digital multi-meter (DMM) to B2_VOUT (J6) and connect the GND lead to
J12.
• Turn the power supply on and observe the voltage on the DMM measuring J6 (B2_VOUT):
– Measure (with the DMM) and verify the BUCK2 output voltage at J6 is approximately 2.8 V.
• Move the voltage lead of the DMM to J11 (LDO_SW_VOUT):
– Measure (with the DMM) and confirm that LDO_SW is disabled.
• Move the voltage lead of the DMM to J7 (B1_VOUT):
– Measure (with the DMM) and confirm that BUCK1 is disabled.
2.5.2 Software Instructions to Enable BUCK1 and LDO_SW
After verifying the operation of BUCK2, follow these instructions to enable BUCK1 and LDO_SW:
• Click the Read All button and verify that some values other than 0x00 (hexadecimal) appear in the
Register0 row of the register map table, as shown in Figure 5.
• Click the Read All button again and most blue highlighted '1's will turn white or gray, indicating that
these bits have not changed since the last time they were read.

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Figure 5. Successful Completion Read ALL Registers in IPG-UI
• Click the Register0 row so that it is highlighted in gray and shows the Register0 contents.
• Hover the mouse over Bit 1 to verify that B2_Enreg is Enabled, as shown in Figure 6.

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Figure 6. B2_Enreg is Enabled by Default in IPG-UI
• Change the B1_Enreg position from Disabled to Enabled while the red voltage lead of the DMM is still
on J7 (B1_VOUT), and then click the Wbutton in the Register0 row to write new values to only this
register. Figure 7 shows that bit 0 now has a value of 1b, B1_Enreg is Enabled, and that until the W
button is clicked the changes made have not yet been written to the TPS65291 device.
– Measure (with the DMM) and verify the voltage at J7 is approximately 3 V.
Figure 7. Enabling BUCK1 (B1_Enreg) in IPG-UI
• Move the red voltage lead of the DMM to J11 (LDO_SW_VOUT), change the LDOnSW_Enreg
position from Disabled to Enabled, and then click the Wbutton in the Register0 row. Figure 8 shows
that bit 2 now has a value of 1b, LDOnSW_Enreg is Enabled, and that after the Wbutton is pressed
all changes made by the user in the GUI have been written to the TPS65291 device. If more than one
register is changed at a time, then the Write All function will be faster than writing to each register one
at a time.
– Measure (with the DMM) and verify the voltage at J11 is approximately 2.8 V, or 5 to 10 mV below
B2_VOUT because LDO_SW is configured as a load switch by default.

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Figure 8. Enabling LDO_SW (LDOnSW_Enreg) in IPG-UI

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EVM Documentation
Appendix A
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EVM Documentation
A.1 Layout
Figure 9 through Figure 14 show the board layout for the TPS65291EVM.
Figure 9. Component Placement—Top Assembly Figure 10. Component Placement—Bottom Assembly

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EVM Documentation
Figure 11. Layout—Top Composite Figure 12. Layout—Bottom Composite
Figure 13. Top Layer Figure 14. Bottom Layer (Top View)

GND
GND
1µF
C3
100 µF
C7
GNDGND
GND
1µF
C17
1µF
C16
GND
GND
GND
GND
B2_VOUT
1µF
C10
1µF
C9
4.99K
R6
GND
GNDGND
GND
0
R3
GND
GND
GND
1µF
C1
100 µF
C5
GND
GND
GND
1µF
C13
1µF
C12
GNDGND GND
1
2
J4
B1_VIN
4.7µF
C21
100k
R29
GND GNDGND
USB_3P3V
IN
1
2
EN
3NC 4
OUT 5
GND
U3 TPS76333DBVT
3.3V Supply
0
R30
TP19
USB_3P3V
TP1
B2_VIN
TP2
B1_VIN
10µH
L2
NLC453232T-100K-PF
LDO_SW_IN
VIN_MON
TP7
LDO_SW_IN
GND
1µF
C15
J15
1
2
J13
LDO_SW_OUT
P6.4/CB4/A4 1
P6.5/CB5/A5 2
P6.6/CB6/A6 3
P6.7/CB7/A7 4
P7.0/CB8/A12
5
P7.1/CB9/A13
6
P7.2/CB10/A14
7
P7.3/CB11/A15
8
P5.0/A8/VREF+/VEREF+
9
P5.1/A9/VREF-/VEREF-
10
AVCC1
11
P5.4/XIN
12
P5.5/XOUT
13
AVSS1 14
P8.0 15
P8.1 16
P8.2 17
DVCC1
18 DVSS1 19
VCORE
20
P1.0/TA0CLK/ACLK
21
P1.1/TA0.0
22
P1.2/TA0.1
23
P1.3/TA0.2
24
P1.4/TA0.3
25
P1.5/TA0.4
26
P1.6/TA1CLK/CBOUT
27
P1.7/TA1.0
28
P2.0/TA1.1 29
P2.1/TA1.2 30
P2.2/TA2CLK/SMCLK 31
P2.3/TA2.0 32
P2.4/TA2.1 33
P2.5/TA2.2 34
P2.6/RTCCLK/DMAE0 35
P2.7/UCB0STE/UCA0CLK 36
P3.0/UCB0SIMO/UCB0SDA
37
P3.1/UCB0SOMI/UCB0SCL
38
P3.2/UCB0CLK/UCA0STE
39
P3.3/UCA0TXD/UCA0SIMO
40
P3.4/UCA0RXD/UCA0SOMI
41
P3.5/TB0.5
42
P3.6/TB0.6
43
P3.7/TB0OUTH/SVMOUT
44
P4.0/PM_UCB1STE/PM_UCA1CLK 45
P4.1/PM_UCB1SIMO/PM_UCB1SDA 46
P4.2/PM_UCB1SOMI/PM_UCB1SCL 47
P4.3/PM_UCB1CLK/PM_UCA1STE 48
DVSS2 49 DVCC2
50
P4.4/PM_UCA1TXD/PM_UCA1SIMO 51
P4.5/PM_UCA1RXD/PM_UCA1SOMI 52
P4.6/PM_NONE 53
P4.7/PM_NONE 54
P5.6/TB0.0
55
P5.7/TB0.1
56
P7.4/TB0.2
57
P7.5/TB0.3
58
P7.6/TB0.4
59
P7.7/TB0CLK/MCLK
60
VSSU 61
PU.0/DP 62
PUR 63
PU.1/DM 64
VBUS
65
VUSB
66
V18
67
AVSS2 68
P5.2/XT2IN
69
P5.3/XT2OUT
70
TEST/SBWTCK 71
PJ.0/TDO 72
PJ.1/TDI/TCLK 73
PJ.2/TMS 74
PJ.3/TCK 75
RST/NMI/SBWTDIO 76
P6.0/CB0/A0 77
P6.1/CB1/A1 78
P6.2/CB2/A2 79
P6.3/CB3/A3 80
U2
MSP430F5529IPN
24MHz
1 2
Y1
22pF
C18
22pF
C19
100pF
C23
0.1µFC30
0.47 µF
C24
0.1µF
C29
0.1µF
C28
1.50k
R26
MSP430
GND GND
100pFC27 USB_5V
USB_5V
GND
GND
Green
21
D1
S
D
G
1
2 3
Q1
VBUS
1
D-
2
D+
3
ID
4
GND
5
6 7 8
11 10 9
J21
GND
D1_P
D1_N 100Diff
100Diff
100Diff
100Diff
2.2k
R13
2.2k
R14
33
R16
33
R17
33
R32
33
R34
120k
R27
D2_N
D2_P
GND
1.5k
R35
1 2
3 4
5 6
7 8
9 10
J19
0
R24
0
R25
-----------USB2ANY Interface-----------
Pin 1: GPIO1 Pin 2: SPI CS
Pin 3: SPI MISO Pin 4: SPI MOSI
Pin 5: 3.3V Pin 6: GND
Pin 7: GPIO7 Pin 8: SPI CLK
Pin 9: I2C SCL Pin 10: I2C SDA
----------------LEGEND----------------
______________________________
USB2ANY (MSP430F5529) Interface
Pin 51 = P4.4 = SPI MOSI
Pin 52 = P4.5 = SPI MISO
Pin 45 = P4.0 = SPI CLK
Pin 29 = P2.0 = SPI CS
1000pF
C20
GND
GND
TPS65291
I/O Header
J22
PUR
33
R12
33
R22
LPad_SPI_MISO
33
R21
33
R15
LPad_SPI_MOSI
LPad_SPI_CLK
LPad_SPI_CS-O
LPad_SPI_CS-W
LPad_SPI_CS-D
1
2
J10
B2_VOUT
1
2
J8
B1_VOUT
1 2
3 4
5 6
7 8
9 10
J16
USB2ANY Interface
Pin 2: SPI CS
Pin 3: SPI MISO
Pin 4: SPI MOSI
Pin 6: GND
Pin 8: SPI CLK
GND
MSP_3P3V
MSP_3P3V
MSP_3P3V
MSP_3P3V
GND
GND
GND
GND
GND
GND
GND
GND
USB2ANY
0
R8 SPI_CS1SPI_CS2
0
R11
SPI_CLK2 SPI_CLK1
0
R10SPI_MOSI2 SPI_MOSI1
B1_VIN
0
R9 SPI_MISO2SPI_MISO1
SPI_CLK1
SPI_CS1
SPI_MOSI1
SPI_MISO1
GND
GPIO7_PWM0
GPIO3_PWM2
GPIO7_PWM0
GPIO3_PWM2
0
R20
0
R18
0
R23
EXT_3V3
0
R19SPI_MISO1
SPI_CS1
SPI_MOSI1
SPI_CLK1
J6
B2_VOUT
J14
J12
J9
J11 LDO_SW_OUT
J7 B1_VOUT
4.7µH
L1
SRR4018-4R7Y
SCL_3P3V
SDA_3P3V
SDA_3P3V
B2_VIN
1
NC
2
B2_LX
3
VIN_MON
4
B2_PGND_AGND 5
LDO_SW_IN_B2_FB
6
LDO_SW_OUT
7MOSI 8
CS 9
CLK 10
MISO 11
B1_FB 12
B1_PGND 13
B1_LX 14
NC
15
B1_VIN 16
PAD 17
U1
TPS65291PWPR
SPI_CLK1
SPI_MOSI1
SPI_MISO1
SPI_CS1
B2_VIN
J3
USB_5V USB_5V
1
2
3
J17
VIN_MON
VIN_MON
B1_VOUTB1_LXB2_LX
1.0M
R5
1.0M
R7
B2_VIN
B1_VIN
0
R4
GND
SCL_3P3V
IN
1
GND 2 EN
3
FAULT
4ILIM 5
OUT 6
U4
TPS2553DBVR-1
0.1µF
C22
GND
USB_5V
EXT3V3_FLT
EXT3V3_EN
100k
R33
160k
R31
EXT3V3_FLT
GND
EXT3V3_EN
1µF
C26
GND
MSP_3P3V
2.2µF
C25
GND
EXT_3V3
0
R28
USB_3P3V
B2_VOUT
1 2 3
J20 MSP_3P3V
MSP_3P3V
1
J18
EXT_3V3
1µF
C6
GND
Conducted EMI filter (optional)
1
2
J5
B2_VIN
Conducted EMI filter (optional)
J2
B2_VIN
J1
B1_VIN
1µH
L4
1µF
C8
GND
0R2
0R1
1µH
L3
22µF
C14
22µF
C4
22µF
C11
22µF
C2
TP3
B2_VOUT TP4
B1_VOUT
TP10
LDO_SW_OUT
TP8
SPI_CLK
TP11
SPI_MOSI
TP12
SPI_MISO
TP14
SPI_CS
TP5
VIN_MON
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Schematic www.ti.com
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EVM Documentation
A.2 Schematic
Figure 15 shows the schematic of the TPS65291EVM.
Figure 15. TPS65291EVM Schematic

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EVM Documentation
A.3 Bill of Materials
Table 3 provides the bill of materials (BOM) for the TPS65291EVM.
Table 3. Bill of Materials
Designator Quantity Value Description Package Reference Part Number Manufacturer
!PCB 1 Printed Circuit Board BMC004 Any
C1, C3, C10, C12,
C15, C16 6 1uF CAP, CERM, 1uF, 25V, +/-10%, X7R, 1206 1206 12063C105KAT2A AVX
C2, C4, C11, C14 4 22uF CAP, TA, 22 µF, 10 V, +/- 10%, 3 ohm, AEC-
Q200 Grade 1, SMD 3216-18 TAJA226K010RNJ AVX
C18, C19 2 22pF CAP, CERM, 22 pF, 50 V, +/- 5%, C0G/NP0,
0603 0603 06035A220JAT2A AVX
C20 1 1000pF CAP, CERM, 1000 pF, 50 V, +/- 10%, X7R,
0603 0603 C0603C102K5RACTU Kemet
C21 1 4.7uF CAP, CERM, 4.7 µF, 6.3 V, +/- 20%, X5R,
0402 0402 GRM155R60J475ME47 DMuRata
C22, C28, C29,
C30 4 0.1uF CAP, CERM, 0.1 µF, 10 V, +/- 10%, X5R, 0402 0402 GRM155R61A104KA01 DMuRata
C23, C27 2 100pF CAP, CERM, 100 pF, 50 V, +/- 10%,
C0G/NP0, 0805 0805 C0805C101K5GACTU Kemet
C24 1 0.47uF CAP, CERM, 0.47 µF, 16 V, +/- 5%, X7R,
0805 0805 0805YC474JAT2A AVX
C25 1 2.2uF CAP, CERM, 2.2 µF, 10 V, +/- 10%, X7R,
0603 0603 GRM188R71A225KE15 DMuRata
C26 1 1uF CAP, CERM, 1 µF, 10 V, +/- 10%, X7R,
0603 0603 GRM188R71A105KA61 DMuRata
D1 1 Green LED, Green, SMD LED_0603 150060VS75000 Wurth Elektronik
H1, H2, H3, H4 4 Machine Screw, Round, #4-40 x 1/4, Nylon,
Philips panhead Screw NY PMS 440 0025 PH B&F Fastener Supply
H5, H6, H7, H8 4 Standoff, Hex, 0.5"L #4-40 Nylon Standoff 1902C Keystone
J1, J2, J6, J7, J9,
J11, J12, J14 8 Standard Banana Jack, Uninsulated, 8.9mm Keystone575-8 575-8 Keystone
J3, J15, J22 3 Header, 2.54 mm, 2x1, Tin, TH Header, 2.54 mm, 2x1, TH TSW-102-07-T-S Samtec
J4, J5, J8, J10,
J13 5 Terminal Block, 3.5mm Pitch, 2x1, TH 7.0x8.2x6.5mm ED555/2DS On-Shore Technology
J16, J19 2 Header (shrouded), 100mil, 5x2, High-
Temperature, Gold, TH 5x2 Shrouded header N2510-6002-RB 3M
J17, J20 2 Header, 2.54 mm, 3x1, Tin, TH Header, 2.54 mm, 3x1, TH TSW-103-07-T-S Samtec
J18 1 Header, 100mil, 1pos, Gold, TH Testpoint TSW-101-07-G-S Samtec
J21 1 Connector, Receptacle, Micro-USB Type B,
R/A, Bottom Mount SMT 7.5x2.45x5mm 0473460001 Molex
L1 1 4.7uH Inductor, Drum Core, Ferrite, 4.7 µH, 1.65 A,
0.082 ohm, SMD Inductor, 4.8x1.8x4.8mm SRR4018-4R7Y Bourns
L2 1 10uH Inductor, Wirewound, Ferrite, 10 µH, 0.55 A,
0.5 ohm, SMD 4.5x3.2x3.2mm NLC453232T-100K-PF TDK
LBL1 1 Thermal Transfer Printable Labels, 0.650" W
x 0.200" H - 10,000 per roll PCB Label 0.650"H x 0.200"W THT-14-423-10 Brady
Q1 1 50V MOSFET, N-CH, 50 V, 0.22 A, SOT-23 SOT-23 BSS138 Fairchild Semiconductor
R1, R2 2 0 RES, 0, 5%, 0.333 W, 0805 0805 CRCW08050000Z0EAH
PVishay-Dale
R3 1 0 RES, 0 ohm, 5%, 0.1W, 0603 0603 CRCW06030000Z0EA Vishay-Dale
R4 1 0 RES, 0, 5%, 0.1 W, 0603 0603 CRCW06030000Z0EA Vishay-Dale
R7 1 1.0Meg RES, 1.0 M, 5%, 0.063 W, 0402 0402 CRCW04021M00JNED Vishay-Dale
R8, R9, R10, R11,
R18, R19, R20,
R23, R24, R25 10 0 RES, 0, 5%, 0.05 W, 0201 0201 CRCW02010000Z0ED Vishay-Dale
R12, R15, R16,
R17, R21, R22,
R32, R34 8 33 RES, 33, 5%, 0.063 W, 0402 0402 CRCW040233R0JNED Vishay-Dale
R13, R14 2 2.2k RES, 2.2 k, 5%, 0.063 W, 0402 0402 CRCW04022K20JNED Vishay-Dale
R26 1 1.50k RES, 1.50 k, 1%, 0.1 W, 0603 0603 CRCW06031K50FKEA Vishay-Dale
R27 1 120k RES, 120 k, 1%, 0.063 W, 0402 0402 CRCW0402120KFKED Vishay-Dale
R29, R33 2 100k RES, 100 k, 5%, 0.063 W, 0402 0402 CRCW0402100KJNED Vishay-Dale
R31 1 160k RES, 160 k, 5%, 0.063 W, 0402 0402 CRCW0402160KJNED Vishay-Dale
R35 1 1.5k RES, 1.5 k, 5%, 0.063 W, 0402 0402 CRCW04021K50JNED Vishay-Dale
TP1, TP2, TP7 3 Test Point, Multipurpose, Red, TH Red Multipurpose Testpoint 5010 Keystone

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EVM Documentation
Table 3. Bill of Materials (continued)
Designator Quantity Value Description Package Reference Part Number Manufacturer
TP3, TP4, TP10 3 Test Point, Multipurpose, Yellow, TH Yellow Multipurpose
Testpoint 5014 Keystone
TP5, TP8, TP11,
TP12, TP14 5 Test Point, Multipurpose, Orange, TH Orange Multipurpose Testpoint 5013 Keystone
TP6, TP9, TP13,
TP15, TP16,
TP17, TP18 7 Test Point, Multipurpose, Black, TH Black Multipurpose
Testpoint 5011 Keystone
TP19 1 SMT Test Point, Miniature, SMT Testpoint_Keystone_Miniat
ure 5015 Keystone
U1 1 High efficiency solution for multi-stacked
batteries systems, PWP0016C (TSSOP-16) PWP0016C TPS65291PWPR Texas Instruments
U2 1 Mixed Signal MicroController, PN0080A PN0080A MSP430F5529IPN Texas Instruments
U3 1
Single Output LDO, 150 mA, Fixed 3.3 V
Output, 2.7 to 10 V Input, with Low IQ, 5-pin
SOT-23 (DBV), -40 to 125 degC, Green
(RoHS & no Sb/Br)
DBV0005A TPS76333DBVT Texas Instruments
U4 1 Adjustable, Active High, Latch-off, Current- Limited Power-Distribution Switch,
DBV0006A (SOT-23-6) DBV0006A TPS2553DBVR-1 Texas Instruments
Y1 1 Crystal, 24.000MHz, 20pF, SMD Crystal, 11.4x4.3x3.8mm ECS-240-20-5PX-TR ECS Inc.
C5, C7 0 100uF CAP, TA, 100uF, 16V, +/-20%, 0.125 ohm,
SMD 7343-31 TPSD107M016R0125 AVX
C6, C8 0 1uF CAP, CERM, 1 µF, 10 V, +/- 10%, X7R,
0603 0603 GRM188R71A105KA61 DMuRata
C9, C13, C17 0 1µF CAP, CERM, 1uF, 25V, +/-10%, X7R, 1206 1206 12063C105KAT2A AVX
FID1, FID2, FID3 0 Fiducial mark. There is nothing to buy or
mount. Fiducial N/A N/A
L3 0 1uH Inductor, Multilayer, Ferrite, 1 µH, 2 A, 0.08
ohm, SMD 2.0x1.0x1.2mm LQM21PN1R0MGH MuRata
L4 0 1uH Inductor, Multilayer, Ferrite, 1 µH, 0.8 A, 0.19
ohm, SMD 0805 LQM21PN1R0MC0D MuRata
R5 0 1.0Meg RES, 1.0 M, 5%, 0.063 W, 0402 0402 CRCW04021M00JNED Vishay-Dale
R6 0 4.99K RES, 4.99k ohm, 1%, 0.1W, 0603 0603 CRCW06034K99FKEA Vishay-Dale
R28 0 0 RES, 0, 5%, 0.25 W, 1206 1206 CRCW12060000Z0EA Vishay-Dale
R30 0 0 RES, 0, 5%, 0.063 W, 0402 0402 CRCW04020000Z0ED Vishay-Dale

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Software Installation and Setup Instructions
Appendix B
SLVUB61–July 2017
Software Installation and Setup Instructions
B.1 IPG-UI Software Installation
The following instructions explain how to install the IPG-UI software on a computer. If this software is
already installed, this section may be skipped.
To install the IPG-UI software, first download the IPG-UI software installation package from www.ti.com.
Then unzip and install the IPG-UI software tool onto the computer.
B.2 IPG-UI Setup for TPS65291
The following instructions explain how to run, setup, and operate the IPG-UI software on a computer and
connect it to the TPS65291EVM.
• Install a shunt on header J20, shorting pin 1 (USB_3P3V) and pin 2 (MSP_3P3V).
• Run the IPG-UI software by using the Windows Start Menu and navigating to the Texas Instruments
folder, or by double-clicking the desktop icon, as shown in Figure 16.
Figure 16. Run the IPG-UI Software
• Wait for the program to load.
• Plug in the micro-USB cable to J21 and connect the other end of the USB cable to an open USB2/3
port on the computer.
• Verify that the software is connected to the USB2ANY as shown in Figure 17.
Figure 17. Successful Connection Between Computer and USB2ANY
• Click the drop-down menu in the Create New Project section and select TPS65291-spi-1.x as shown in
Figure 18.

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Software Installation and Setup Instructions
Figure 18. Creating New IPG-UI Project for the TPS65291
• Click the Create Project button.
NOTE: After a project is initially created, it is available in the Create Projects from Recent Devices
menu. When a project is saved, it is available in the Open Recent Projects menu.
• Verify that a blue notification appears stating that register write access is enabled as shown in
Figure 19.
Figure 19. Successful Write Access to TPS65291 Notification
• The TPS65291 Introduction tab is now displayed. If a red notification appears (as in Figure 20), it
indicates the computer can talk to the USB2ANY but cannot communicate with the TPS65291 device.
The primary cause of this issue may be that the power supply is not turned on or a cable is unplugged.
In case of either issue, the test setup of the EVM must be debugged before continuing.
Figure 20. Failed GUI Communication to TPS65291 Notification
• Click the Get Started button or the Register Map tab shown in Figure 21 to begin reading from and
writing to registers to evaluate the TPS65291 device.

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Software Installation and Setup Instructions
Figure 21. TPS65291 SPI Project Introduction Tab in IPG-UI
NOTE: At present, the IPG-UI software version is 2.5.0.3 and the TPS65291-SPI file version is 1.1.

STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.