Texas Instruments UCC14131EVM-070 User manual

User’s Guide
Using the UCC14131EVM-070 for Biasing GaN and Gate
Driver ICs in Automotive and Industrial Applications
ABSTRACT
This user’s guide provides a description and instructions for use of the UCC14131EVM-070 to evaluate the
UCC14131-Q1; a high frequency, integrated transformer, DC-DC converter module from Texas Instruments. This
EVM allows designers to quickly and efficiently evaluate the UCC14131-Q1 for use in automotive or industrial
applications requiring gate driver IC bias power as high as 1.5 W, meeting up to 5 kVRMS isolation.
Table of Contents
1 Introduction.............................................................................................................................................................................3
1.1 Pin Configuration and Functions........................................................................................................................................ 3
2 Description.............................................................................................................................................................................. 5
2.1 EVM Electrical Performance Specifications....................................................................................................................... 6
3 Schematic................................................................................................................................................................................7
4 EVM Setup and Operation......................................................................................................................................................8
4.1 Recommended Test Equipment......................................................................................................................................... 8
4.2 External Connections for Easy Evaluation......................................................................................................................... 8
4.3 Powering the EVM............................................................................................................................................................. 9
4.4 EVM Test Points.................................................................................................................................................................9
4.5 Probing the EVM.............................................................................................................................................................. 11
5 Performance Data................................................................................................................................................................. 12
5.1 Efficiency Data................................................................................................................................................................. 12
5.2 Regulation Data............................................................................................................................................................... 14
5.3 Steady State Input Current...............................................................................................................................................15
5.4 Start-Up Waveforms.........................................................................................................................................................15
5.5 Inrush Current.................................................................................................................................................................. 18
5.6 AC Ripple Voltage............................................................................................................................................................ 20
5.7 EN and Timing..................................................................................................................................................................22
5.8 RLIM.................................................................................................................................................................................22
5.9 Shutdown......................................................................................................................................................................... 24
5.10 Thermal Performance.................................................................................................................................................... 25
6 Assembly and Printed Circuit Board (PCB) Layers...........................................................................................................26
7 Bill of Materials (BOM)..........................................................................................................................................................30
List of Figures
Figure 1-1. DWN Package, 36-Pin SSOP (Top View)..................................................................................................................3
Figure 2-1. UCC14131EVM-070 (Top View)................................................................................................................................5
Figure 2-2. UCC14141EVM-070 (Bottom View).......................................................................................................................... 5
Figure 3-1. UCC14131EVM-070 Schematic Diagram................................................................................................................. 7
Figure 4-1. Typical Efficiency Measurement Setup......................................................................................................................8
Figure 4-2. UCC14131EVM-070, PCB Scope Probe Test Points.............................................................................................. 11
Figure 5-1. Measured Efficiency, VDD-VEE = 12-V Loading Only.............................................................................................12
Figure 5-2. Regulation vs Power, VDD-VEE Loading Only....................................................................................................... 14
Figure 5-3. Regulation vs Current, VDD-VEE Loading Only..................................................................................................... 14
Figure 5-4. Input Current vs Power, VDD-VEE Loading Only....................................................................................................15
Figure 5-5. Start-up 1: VIN = 12 V, IVDD = 0 mA, I[+5V] = 0 mA.................................................................................................. 15
Figure 5-6. Start-up 2: VIN = 12 V, IVDD = 130 mA, I[+5V] = 0 mA.............................................................................................. 16
Figure 5-7. Start-up 3: VIN = 12 V, IVDD = 0 mA, I[+5V] = 10 mA................................................................................................ 16
Figure 5-8. Start-up 4: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA............................................................................................ 17
www.ti.com Table of Contents
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
1
Copyright © 2023 Texas Instruments Incorporated

Figure 5-9. Inrush Current: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA..................................................................................... 18
Figure 5-10. Inrush Current: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA................................................................................... 18
Figure 5-11. Inrush Current: VIN = 12 V, IVDD = 0 mA, I[+5V] = 0 mA..........................................................................................19
Figure 5-12. Inrush Current: VIN = 12 V, IVDD = 0 mA, I[+5V] = 0 mA......................................................................................... 19
Figure 5-13. AC Ripple: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA.......................................................................................... 20
Figure 5-14. AC Ripple: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA.......................................................................................... 20
Figure 5-15. AC Ripple: VIN = 12 V, IVDD =0 mA, I[+5V] = 0 mA................................................................................................. 21
Figure 5-16. AC Ripple: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA.......................................................................................... 21
Figure 5-17. EN to /PG Delay, 4.62 ms, IVDD = 0 mA, I[+5V] = 0 mA.......................................................................................... 22
Figure 5-18. RLIM: VIN = 12 V, IVDD = 0 mA, I[+5V] = 0 mA........................................................................................................22
Figure 5-19. RLIM: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA..................................................................................................23
Figure 5-20. RLIM: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA..................................................................................................23
Figure 5-21. Shutdown by VIN Removal: VINOFF = 7.2 V, IVDD = 0 mA, I[+5V] = 0 mA...............................................................24
Figure 5-22. Shutdown by EN Low: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA........................................................................24
Figure 5-23. VIN=12 V, IVDD = 128.5 mA, 1.54 W......................................................................................................................25
Figure 5-24. Power Dissipation and Case Temperature vs Input Voltage, TA=24.6°C, 1.54 W.................................................25
Figure 5-25. VIN=12 V, IVDD =0 mA, POUT=0 W.......................................................................................................................25
Figure 5-26. Power Dissipation and Case Temperature vs Input Voltage, TA=23.9°C, 0 W......................................................25
Figure 6-1. UCC14131EVM-070, Fully Assembled 3D Top View.............................................................................................. 26
Figure 6-2. UCC14131EVM-070, Fully Assembled 3D Bottom View.........................................................................................26
Figure 6-3. UCC14131EVM-070, 3D Angle View...................................................................................................................... 27
Figure 6-4. UCC14131EVM-070, PCB Top Layer, Assembly.................................................................................................... 27
Figure 6-5. UCC14131EVM-070, GND Layer 2 (same as layer 3)............................................................................................28
Figure 6-6. UCC14131EVM-070, GND Layer 3 (same as layer 2)............................................................................................28
Figure 6-7. UCC14131EVM-070, PCB Bottom Layer, Assembly (mirrored view)..................................................................... 29
List of Tables
Table 1-1. Pin Functions (refer and follow the data sheet).......................................................................................................... 4
Table 2-1. EVM Electrical Specifications..................................................................................................................................... 6
Table 4-1. Input, Output, Test Point (I/O/TP) Description...........................................................................................................10
Table 5-1. Efficiency Test Data (VIN = 11.2 V)...........................................................................................................................12
Table 5-2. Efficiency Test Data (VIN = 12 V) .............................................................................................................................13
Table 5-3. Efficiency Test Data (VIN = 14 V) .............................................................................................................................13
Table 7-1. UCC14131EVM-070 BOM........................................................................................................................................ 30
Trademarks
All trademarks are the property of their respective owners.
Trademarks www.ti.com
2Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

1 Introduction
The UCC14131-Q1 is a high efficiency, low-emissions, 5 kVRMS Isolated DC-DC Converter capable of delivering
1.5-W of power. Since the UCC14131-Q1 provides isolated power in an integrated package, this allows systems
to reduce cost and size by removing the need for separate isolated power supplies. The UCC14131-Q1 delivers
class-leading efficiency in power conversion from the primary to the secondary side while removing the need
for bulky external transformers or power modules commonly used in existing designs. This integration allows for
minimal printed circuit board (PCB) area as well as decreased height profile.
Note
Please follow the latest UCC14131-Q1 data sheet for each pin function.
1.1 Pin Configuration and Functions
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
VEE
VEEA
FBVDD
FBVEE
RLIM
VEE
VEE
VDD
VDD
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
PG
GNDP
GNDP
ENA
GNDP
VIN
VIN
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
GNDP
Figure 1-1. DWN Package, 36-Pin SSOP (Top View)
www.ti.com Introduction
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
3
Copyright © 2023 Texas Instruments Incorporated

Table 1-1. Pin Functions (refer and follow the data sheet)
PIN TYPE(1) DESCRIPTION
NAME NO.
GNDP
1, 2, 5, 8, 9, 10,
11, 12, 13, 14,
15, 16, 17, 18
GPrimary-side ground connection for VIN. PIN 1,2, and 5 are analog ground. PIN 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, and 18 are power ground. Place several vias to copper pours for thermal relief.
PG 3 O
Active low power-good open-drain output pin. PG remains low when (UVLO ≤ VVIN ≤
OVLO); (UVP1 ≤ (VDD – VEE) ≤ OVP1); TJ_Primary ≤ TSHUTPPRIMARY_RISE; and TJ_secondary ≤
TSHUTSECONDARY_RISE
ENA 4 I Enable pin. Forcing ENA LOW disables the device. Pull HIGH to enable normal device
functionality. 5.5-V recommended maximum.
VIN 6, 7 P
Primary input voltage. PIN 6 is for analog input, and PIN 7 is for power input. For PIN 7, connect
two 10-μF ceramic capacitor from VIN7 to power GNDP. Connect a 0.1-μF high-frequency bypass
ceramic capacitor close the pins. For PIN 6, connect a 4.75-ohm resistor to power input. Connect
a 10-μF ceramic capacitor from VIN6 to power analog GNDP. Connect a 330-pF high-frequency
bypass ceramic capacitor close the pins
VEE
19, 20, 21, 22,
23, 24, 25,26,
27, 30,31, 36
GSecondary-side reference connection for VDD. The VEE pins are used for the high current return
paths.
VDD 28, 29 P
Secondary-side isolated output voltage from transformer. Connect a 2.2-μF and a parallel 0.1-μF
ceramic capacitor from VDD to VEE. The 0.1-μF ceramic capacitor is the high frequency bypass
and must be next to the IC pins.
RLIM 32 P Secondary-side second isolated output voltage resistor to limit the source current from VDD.
FBVEE 33 I Feedback output voltage sense pin used to adjust the output voltage.
FBVDD 34 I
Feedback (VDD – VEE) output voltage sense pin and to adjust the output (VDD – VEE) voltage.
Connect a resistor divider from VDD to VEE so that the midpoint is connected to FBVDD, and
the equivalent FBVDD voltage when regulating is 2.5 V. Add a 330-pF ceramic capacitor for high
frequency decoupling in parallel with the low-side feedback resistor. The 330-pF ceramic capacitor
for high frequency bypass must be next to the FBVDD and VEEA IC pins on top layer or back
layer connected with vias.
VEEA 35 G
Secondary-side analog sense reference connection for the noise sensitive analog feedback inputs,
FBVDD and FBVEE. Connect the low-side feedback resistors and high frequency decoupling filter
capacitor close to the VEEA pin and respective feedback pin FBVDD or FBVEE. Connect to
secondary-side gate drive lowest voltage reference, VEE. Use a single point connection and place
the high frequency decoupling ceramic capacitor close to the VEEA pin.
(1) P = power, G = ground, I = input, O = output
Introduction www.ti.com
4Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

2 Description
The UCC14131EVM-070 is intended to allow designers to evaluate the performance characteristics and
capabilities of the UCC14131-Q1 quickly and easily for use in automotive, isolated, gate driver bias applications,
as well as a variety of isolated industrial bias power applications. The EVM allows users to test functions of the
UCC14131-Q1 such as: Enable/Disable (EN) of the device and easily apply variable loads to the outputs. This
EVM allows the user to measure efficiency across the input voltage range and varying output loads according to
system requirements. Another feature of the EVM is the ease of probing during test. Test points are strategically
placed and described according to Table 4-1.
Figure 2-1. UCC14131EVM-070 (Top View)
Figure 2-2. UCC14141EVM-070 (Bottom View)
www.ti.com Description
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
5
Copyright © 2023 Texas Instruments Incorporated

2.1 EVM Electrical Performance Specifications
Table 2-1. EVM Electrical Specifications
VIN = 12 V, VDD-VEE = 12 V, [+5V]-VEE = 5 V, TA = 25°C, (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS
VIN Input voltage range PVDD-VEE = 1.5 W 11.2 12 14 V
VIN_ON Input voltage on 9 10 V
VIN_OFF Input voltage off 7.2 V
IIN_FL Input current at full load VIN = 11.2 V, IVDD = 132.6 mA 290
mAVIN = 12 V, IVDD = 128.5 mA 282
VIN = 14 V, IVDD = 128.5 mA 274
IIN_NL Input current at no load VIN = 11.2V, IVDD = 0 mA 22
mAVIN = 12 V, IVDD = 0 mA 21
VIN = 14 V, IVDD = 0 mA 19
IIN_OFF Input current at EN LOW EN LOW, VDD = VEE = 0 V 540 µA
EN to /PG
delay
IVDD =IVEE = 0 mA 4.6 ms
OUTPUT CHARACTERISTICS
VDD-VEE DC full load set-point 11.2 V < VIN <14 V, IVDD = 130 mA 12 V
IVDD VDD load current range 11.2 V < VIN < 14 V 0 130 mA
VDD%LD Load regulation VDDREG =
VImin −VImax
VImax
× 100%
VIN = 12 V, 0 mA ≤ IVDD ≤ 130 mA
0.7 %
VDD%LN Line regulation VDDREG =
VImin −VImax
VImax
× 100%
IVDD = 124 mA, 11.2 V ≤ VIN ≤ 14 V
0.2 %
VDDAC pk-to-pk AC ripple IVDD = 130 mA 115 mV
VDDSS Soft-start IVDD = I[+5V] = 0 mA 16 ms
PMAX Maximum output power IVDD = 130 mA, I[+5V] = 0 mA, 11.2 V < VIN <
14 V 1.5 W
[+5V] DC full load set-point 11.2 V ≤ VIN ≤ 14 V, I[+5V] = 10 mA 5 V
I[+5V] [+5V] load current range 11.2 V ≤ VIN ≤ 14 V 0 10 mA
[+5V]AC pk-to-pk AC ripple I[+5V] = 10 mA 155 mV
SYSTEM CHARACTERISTICS
η100% Full load efficiency IVDD = 130 mA, VDD = 12 V, 45 %
η50% Half load efficiency IVDD = 65 mA, VDD = 12 V, 41 %
FSW Switching frequency (1) VIN = 11.2 V, 0 mA < IVDD < 130 mA 20.5
MHzVIN = 12 V, 0 mA < IVDD < 130 mA 19.1
VIN = 14 V, 0 mA < IVDD < 130 mA 16.6
VDD(OCL)
VDD overcurrent limit
(I[+5V] = 0 mA)
VIN = 11.2 V, VDD = 12 V 140
mAVIN = 12.0 V, VDD = 12 V 155
VIN = 14.0 V, VDD = 12 V 170
[+5V](OCL) [+5V] overcurrent limit
(IVDD = 0 mA) VIN = 12.0 V, VDD = 12 V 16 mA
TMAX Maximum temperature rise
above ambient
IVDD = 130 mA, I[+5V] = 0 mA, VDD = 12 V 75 °C
(1) Switching frequency is specified as primary-side switching frequency. Secondary-side is 2x primary.
Description www.ti.com
6Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

3 Schematic
Figure 3-1 shows the EVM electrical schematic. C2, C4 and R8 are intentionally unpopulated as indicated by a
red X on the secondary side, placed directly over the component.
Figure 3-1. UCC14131EVM-070 Schematic Diagram
www.ti.com Schematic
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
7
Copyright © 2023 Texas Instruments Incorporated

4 EVM Setup and Operation
4.1 Recommended Test Equipment
• VBIAS: 5-V DC power supply1: 5 V, 0 to 10 mA
• VIN: DC power supply2: 8 to 18 V, 500 mA
• IVDD: Electronic load or fixed resistor: 12 V, 0 to 150 mA
• I[+5V]: Electronic load or fixed resistor: 5 V, 10 mA
• (3) DVMs measuring DC voltage < 30 V
• (3) DVMs measuring DC current < 200 mA on IVDD or I[+5V], and < 500 mA on IVIN
• Oscilloscope: 4 channel, 500 MHz or better, voltage probes, current probes
• Minimum wire gauge 20 AWG to 22 AWG or better
• Thermal camera (optional) or thermocouple to measure U1 case temperature
4.2 External Connections for Easy Evaluation
The UCC14131EVM-070 EVM utilizes screw terminals for quickly connecting to VIN, VDD, [+5V] and VEE (refer
to Table 4-1). Connecting the appropriate ammeters and voltmeters, as shown in Figure 4-1, allows accurate
EVM efficiency measurements to be made.
Connecting Test Equipment
1. Move jumper SH-J1 into the J2:1-2, EN OFF position. This makes sure the EVM cannot start while test
equipment is being connected.
2. Connect a 5-V DC bias power supply to J1:1-2 (+3.3 V to +5 V). Set the power supply to 0 V. The 5-V supply
at J1 serves as the pullup bias for /PG and ENA. Turn off/disable the 5-V DC Bias power supply.
3. Connect the VIN DC power supply capable of 8 V<VIN<18 V, 300 mA at J4:1-2 (VIN). Adjust the power supply
to 12 V, and set the current limit to 350 mA. Set the power supply voltage to 12 V. Turn off/disable the VIN
power supply.
4. Connect a variable load between J3:1 (VDD) and J3:3 (VEE). If using an electronic load, set to constant
current (CC), 68 mA. Leave the load disabled until the EVM is powered.
5. Connect a second load between J3:2 ([+5V]) and J3:3 (VEE). If using an electronic load, set to constant
current (CC), 10 mA. Leave the load disabled until the EVM is powered. Since the required load is small, a
through-hole, 250-mW, 400-Ω load resistor can be connected between J3:2-3.
6. Some electronic loads are not be able to regulate/stabilize CC when setting in the low mA range. Monitor the
input current and load currents by inserting ammeters, A1-A3, as shown in Figure 4-1. Use a current probe
with the oscilloscope to verify the stability of the DC current being regulated by an electronic load.
V1
A1
VIN
10-14 V
+5 V
DC Bias
VISO
LOAD
A2
V2
V3
RL
499 Ω
TP1
TP2 TP3
TP4
TP5
TP6
TP7
TP8
TP9
TP10
TP11
Figure 4-1. Typical Efficiency Measurement Setup
EVM Setup and Operation www.ti.com
8Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

4.3 Powering the EVM
WARNING
• Hot Surface. Contact can cause burns. U1 package surface can reach temperatures of 45°C
above ambient. Do not touch!
• Do not test this EVM unless you are trained in the proper safety, handling and testing of power
electronics.
4.3.1 Power on for Start-up
1. Verify VIN and 5-V DC bias power supplies are OFF/disabled and no voltage is applied to the UUT
2. Move EN shorting jumper, SH-J1, to the J2:2-3 EN ON position
3. Turn on the VIN DC power supply. Verify 12-V is present at VIN(TP7)-to-GNDP(TP10)
4. Verify the loads on VDD and VEE are disabled
5. Turn on the 5-V DC bias power supply. EVM is now enabled with VDD and +5V in regulation under no load
conditions.
6. Verify 12-V is present on VDD-VEE and 5-V is present on [+5V](TP3)-GNDS(TP1)
7. Enable the 100-mA load on VDD-(+5V), enable the 10-mA load on [+5V]-GNDS
8. The UCC14131-Q1 is now regulating VDD and VEE and processing 1.5-W of isolated output power
9. Vary VIN between 11.2 V<VIN<14 V, vary IVDD between 0 mA<IVDD<130 mA, vary IVEE between 0
mA<I[+5V]<30 mA.
10. Insert oscilloscope probes into VIN(TP9), [+12V](TP6) and [+5V](TP3) for measuring VIN, [+12V] and [+5V]
start-up, steady state and AC ripple voltage
4.3.2 Power off for Shutdown
1. Move EN shorting jumper SH-1 to the J2:1-2, EN OFF position
2. Turn off the 5-V DC bias power supply
3. Disable the IVDD load
4. Disable the I[+5v] load
5. Turn off VIN power supply
4.4 EVM Test Points
Table 4-1 describes the various EVM test points, allowing easy access for connecting oscilloscope probes,
DVM test leads and wire connections to lab test equipment as shown in Figure 4-1. Pay attention to maintain
separation between the primary side, GNDP and secondary side, VEE (= GNDS). Primary-side test points are
not to be referenced to VEE through improper test equipment insertion. Likewise, secondary-side test points are
not to be referenced to GNDP through improper test equipment insertion.
Note
Refer to Figure 4-1 to locate test point location on the board for TP1, TP2, etc.
www.ti.com EVM Setup and Operation
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
9
Copyright © 2023 Texas Instruments Incorporated

Table 4-1. Input, Output, Test Point (I/O/TP) Description
PIN Name I/O/TP COLOR DESCRIPTION MIN TYP MAX UNIT
J1 5-V I Green VBIAS, EN and /PG bias 3 VBIAS 5 V
J2:1-2 EN I Green EN, off 0 V
J2:2-3 EN I Black EN, on VBIAS V
J3:1-3 VDD,
[+12V]
O Green Secondary, +12V Output, [+12V]-to-VEE, or VDD-VEE 12 V
J3:2-3 [+5V] O Green Secondary, +5V Output, [+5V]-to-VEE, or [+5V]-VEE 5 V
J4 VIN I Green VIN, primary input voltage 8 12 18 V
TP1 GNDS TP Black VEE and GNDS, secondary side reference 0 V
TP2 /PG TP Yellow /PG, power good test point VBIAS V
TP3 +5V TP PCB [+5V]-VEE, secondary COM scope probe point 0 5 V
TP4 +5V TP White [+5V]-VEE, secondary +5V output 0 5 V
TP5 EN,
ENA
TP Yellow EN, enable test point VBIAS V
TP6 VDD,
[+12V]
TP PCB [+12V]-to-VEE, or VDD-VEE, secondary VDD scope probe
point 12 V
TP7 VIN TP Red VIN, positive probe point 8 12 18 V
TP8 VDD,
[+12V]
TP Red [+12V], secondary VDD test point 12 V
TP9 VIN TP PCB VIN-to-GNDP scope probe point 8 12 18 V
TP10 GNDP TP Black GNDP, shared primary GND test point 0 V
TP11 GNDP TP Black GNDP, shared primary GND test point 0 V
EVM Setup and Operation www.ti.com
10 Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

4.5 Probing the EVM
Using TP3 ([+5V]), TP6 ([+12V]) and TP9 (VIN) oscilloscope probe PCB test points (see Figure 4-1 and Figure
4-2), the UCC14131-Q1 is a high frequency DC-DC module that requires careful measurement for accurately
capturing transient events and measuring high frequency, AC ripple voltage. Remove the witch hat probe tip
cover and ground lead from the scope probe. If scope probe ground springs are not available, wrap a piece of
22 AWG bare wire around the scope probe ground ring or use a fitted ground spring and insert the probe tip and
ground into the EVM as shown in Figure 4-2.
Figure 4-2. UCC14131EVM-070, PCB Scope Probe Test Points
The EVM output nomenclature (VDD, VEE) corresponds to what is commonly used when referring to isolated
gate driver ICs for [+12V] and GNDS of this evaluation board. As shown in Figure 4-2, [+5V](TP4) is the [+5V]
output (ref Table 4-1). When the UCC14131-Q1 is used to bias a gate driver IC, [+12V] (VDD to VEE) and
[+5V] (capacitor-middle to VEE) are referred to with respect to VEE (= GNDS). When testing the EVM as a
stand-alone bias power supply, oscilloscope probing of the secondary-side outputs are limited to [+5V](TP3) and
[+12V](TP6), which are referenced to VEE or GNDS.
www.ti.com EVM Setup and Operation
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
11
Copyright © 2023 Texas Instruments Incorporated

5 Performance Data
Unless otherwise specified, all performance data and waveforms collected using electronic load set to constant
current.
5.1 Efficiency Data
PVDD-VEE (W)
Efficiency (%)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0
5
10
15
20
25
30
35
40
45
50
VIN = 11.2 V
VIN = 12 V
VIN = 14 V
Figure 5-1. Measured Efficiency, VDD-VEE = 12-V Loading Only
Table 5-1. Efficiency Test Data (VIN = 11.2 V)
VIN (V) IIN (mA) VDD-VEE (V) IVDD-VEE (mA) [+5V]-VEE (V) PIN (W) PVDD-VEE (W) Eff (%)
11.21 22.20 12.023 0.00 5.02 0.25 0.00 0.00
11.21 47.00 12.013 11.91 5.02 0.53 0.14 27.17
11.21 63.90 12.015 20.00 5.02 0.72 0.24 33.56
11.21 88.87 12.008 32.00 5.01 1.00 0.38 38.58
11.21 106.59 12.002 40.17 5.01 1.19 0.48 40.36
11.21 131.62 11.991 52.17 5.01 1.47 0.63 42.41
11.21 148.95 11.989 60.33 5.01 1.67 0.72 43.33
11.21 175.11 11.983 72.66 5.01 1.96 0.87 44.37
11.21 198.67 11.976 83.58 5.01 2.23 1.00 44.96
11.21 234.50 11.966 99.96 5.01 2.63 1.20 45.52
11.21 268.62 11.953 116.31 5.01 3.01 1.39 46.19
11.21 282.53 11.931 124.40 5.00 3.17 1.48 46.88
11.21 290.25 11.766 132.58 5.00 3.25 1.56 47.96
11.21 294.42 11.269 136.78 5.00 3.30 1.54 46.72
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
Performance Data www.ti.com
12 Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

Table 5-2. Efficiency Test Data (VIN = 12 V)
VIN (V) IIN (mA) VDD-VEE (V) IVDD-VEE (mA) [+5V]-VEE (V) PIN (W) PVDD-VEE (W) Eff (%)
12.02 21.39 12.036 0.00 5.02 0.26 0.00 0.00
12.02 45.30 12.030 11.93 5.02 0.54 0.14 26.38
12.02 61.20 12.020 20.14 5.02 0.73 0.24 32.95
12.02 85.20 12.013 31.98 5.02 1.02 0.38 37.56
12.02 102.33 12.007 40.19 5.02 1.23 0.48 39.28
12.02 126.36 12.001 52.24 5.02 1.52 0.63 41.32
12.02 142.91 11.992 60.41 5.02 1.72 0.72 42.22
12.02 168.05 11.987 72.62 5.02 2.02 0.87 43.14
12.02 190.87 11.981 83.63 5.01 2.29 1.00 43.72
12.01 216.78 11.975 95.84 5.01 2.60 1.15 44.10
12.01 259.45 11.962 116.13 5.01 3.11 1.39 44.60
12.01 282.30 11.954 128.24 5.01 3.39 1.53 45.23
12.01 301.86 11.947 136.48 5.01 3.62 1.63 44.99
12.01 313.04 11.913 145.76 5.01 3.76 1.74 46.20
12.01 316.52 11.744 149.99 5.01 3.80 1.76 46.35
12.01 320.33 11.380 154.06 5.01 3.85 1.75 45.59
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
Table 5-3. Efficiency Test Data (VIN = 14 V)
VIN (V) IIN (mA) VDD-VEE (V) IVDD-VEE (mA) [+5V]-VEE (V) PIN (W) PVDD-VEE (W) Eff (%)
14.01 19.35 12.043 0.00 5.02 0.27 0.00 0.00
14.01 42.17 12.036 12.29 5.02 0.59 0.15 25.05
14.01 56.40 12.027 20.38 5.02 0.79 0.25 31.03
14.01 79.31 12.019 32.14 5.02 1.11 0.39 34.78
14.01 101.91 12.011 44.18 5.03 1.43 0.53 37.18
14.01 125.44 12.004 56.30 5.02 1.76 0.68 38.47
14.01 156.40 11.990 72.59 5.02 2.19 0.87 39.74
14.01 209.63 11.978 99.92 5.02 2.94 1.20 40.77
14.01 233.87 11.971 111.96 5.02 3.28 1.34 40.92
14.01 274.64 11.956 132.45 5.01 3.85 1.58 41.17
14.01 299.44 11.950 145.98 5.01 4.19 1.74 41.60
14.01 310.70 11.945 150.04 5.00 4.35 1.79 41.19
14.01 316.27 11.933 154.19 5.00 4.43 1.84 41.53
14.01 323.90 11.889 162.29 5.00 4.54 1.93 42.53
14.01 328.53 11.527 166.50 5.00 4.60 1.92 41.71
14.01 332.90 11.213 170.46 5.00 4.66 1.91 41.00
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
www.ti.com Performance Data
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
13
Copyright © 2023 Texas Instruments Incorporated

5.2 Regulation Data
PVDD-VEE (W)
VDD-VEE (V)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12
12.1
VIN = 11.2 V
VIN = 12 V
VIN = 14 V
Figure 5-2. Regulation vs Power, VDD-VEE Loading Only
IVDD-VEE (mA)
VDD-VEE (V)
0 20 40 60 80 100 120 140 160 180
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12
12.1
VIN = 11.2 V
VIN = 12 V
VIN = 14 V
Figure 5-3. Regulation vs Current, VDD-VEE Loading Only
Performance Data www.ti.com
14 Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

5.3 Steady State Input Current
PVDD-VEE (W)
IIN (mA)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
10
40
70
100
130
160
190
220
250
280
310
340
VIN = 11.2 V
VIN = 12 V
VIN = 14 V
Figure 5-4. Input Current vs Power, VDD-VEE Loading Only
5.4 Start-Up Waveforms
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
top: VDD-VEE, 5 V/div, bot: /PG, 5 V/div,
mid-1: [+5 V]-VEE, 2 V/div, time = 1 ms/div
mid-2: EN, 5 V/div,
Figure 5-5. Start-up 1: VIN = 12 V, IVDD = 0 mA, I[+5V] = 0 mA
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
www.ti.com Performance Data
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
15
Copyright © 2023 Texas Instruments Incorporated

top: VDD-VEE, 5 V/div, bot: /PG, 5 V/div,
mid-1: [+5 V]-VEE, 2 V/div, time = 1 ms/div
mid-2: EN, 5 V/div,
Figure 5-6. Start-up 2: VIN = 12 V, IVDD = 130 mA, I[+5V] = 0 mA
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
top: VDD-VEE, 5 V/div, bot: /PG, 5 V/div,
mid-1: [+5 V]-VEE, 2 V/div, time = 1 ms/div
mid-2: EN, 5 V/div,
Figure 5-7. Start-up 3: VIN = 12 V, IVDD = 0 mA, I[+5V] = 10 mA
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
Performance Data www.ti.com
16 Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

top: VDD-VEE, 5 V/div, bot: /PG, 5 V/div,
mid-1: [+5 V]-VEE, 2 V/div, time = 1 ms/div
mid-2: EN, 5 V/div,
Figure 5-8. Start-up 4: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA
www.ti.com Performance Data
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
17
Copyright © 2023 Texas Instruments Incorporated

5.5 Inrush Current
Inrush current measurement made with VIN applied and toggle EN pin. This makes sure the input capacitors are
pre-biased to VIN and make negligible contribution to the measure inrush current. Inrush current is measured by
connecting a current probe to the positive connecting cable between the input supply voltage and the EVM, J4
terminal block.
top: VDD-VEE, 5 V/div, bot: IIN, 1 A/div,
mid-1: [+5 V]-VEE, 2 V/div, time = 1 ms/div,
mid-2: EN, 5 V/div,
Figure 5-9. Inrush Current: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
top: VDD-VEE, 5 V/div, bot: IIN, 1 A/div,
mid-1: [+5 V]-VEE, 2 V/div, time = 1 ms/div,
mid-2: EN, 5 V/div, time_zoom = 100 µs/div
Figure 5-10. Inrush Current: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA
Performance Data www.ti.com
18 Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated

top: VDD-VEE, 5 V/div bot: IIN, 1 A/div
mid-1: [+5V]-VEE, 2 V/div time = 1 ms/div
mid-2: EN, 5 V/div,
Figure 5-11. Inrush Current: VIN = 12 V, IVDD = 0 mA, I[+5V] = 0 mA
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
top: VDD-VEE, 5 V/div, bot: IIN, 1 A/div,
mid-1: [+5 V]-VEE, 2 V/div, time = 1 ms/div,
mid-2: EN, 5 V/div, time_zoom = 100 µs/div
Figure 5-12. Inrush Current: VIN = 12 V, IVDD = 0 mA, I[+5V] = 0 mA
www.ti.com Performance Data
SLUUCU2 – MARCH 2023
Submit Document Feedback
Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
19
Copyright © 2023 Texas Instruments Incorporated

5.6 AC Ripple Voltage
top: VDD-VEE, 100 mV/div, pk-to-pk = 157 mV),
pk-to-pk = 113 mV, time = 100 ms/div
bot: [+5 V]-VEE, 100 mV/div,
Figure 5-13. AC Ripple: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA
Note
VDD, VEE, and [+5V], etc., refer to Table 4-1 and Figure 4-1.
top: VDD-VEE, 100 mV/div, time = 100 µs/div bot: [+5V]-VEE, 100 mV/div)
Figure 5-14. AC Ripple: VIN = 12 V, IVDD = 130 mA, I[+5V] = 10 mA
Performance Data www.ti.com
20 Using the UCC14131EVM-070 for Biasing GaN and Gate Driver ICs in
Automotive and Industrial Applications
SLUUCU2 – MARCH 2023
Submit Document Feedback
Copyright © 2023 Texas Instruments Incorporated