Texas Instruments LMR10530 User manual

7
Rinc
D1
L1
Rfbt
VIN U1 SW
FB
LMR10530YSD
SW
8VOUT
Rfbb
Cff
Cinc Co2
Ren
Co1
Cin
9
5
4
6
10
2
1
11
3
SW SW
NC
PGND
SGND
DAP
VINC
EN
EN VIND
VIND
GND
User's Guide
SNVU192A–October 2012–Revised April 2013
AN-2280 LMR10530 Evaluation Module
1 Introduction
The LMR10530 evaluation module is designed to provide the power supply design engineer with a fully
functional regulator design using the LMR10530 3MHz switching regulator in an WSON-10 package. The
evaluation module is configured to provide an output of 1.2V at up to 3A from an input voltage range of 3V
to 5.5V.
The printed circuit board consists of 4 layers of copper on FR4 material. The middle layers are solid
ground layers with the first middle layer having a small polygon cut out for the VIN node. The intermediate
ground layer helps in minimizing the AC current loop. The LMR10530 is thermally tied to the other layers
by thermal vias directly underneath the device. This user's guide contains the evaluation module
schematic, a quick setup procedure, and a Bill-of-Materials (BOM). For complete circuit design
information, see LMR10530 SIMPLE SWITCHER 5.5Vin, 3.0A Step-Down Voltage Regulator in WSON-10
(SNVS814).
The module has a Cff capacitor footprint reserved for applications requiring higher VOUT. The Cff cap also
helps to minimize the output voltage overshoot during sluggish startup. For suggested cap values, see the
LMR10530 datasheet (SNVS814). The module also has a reserved footprint for an additional output cap,
Co2, for certain applications requiring more capacitance.
The performance of the evaluation board is:
• Input Range: 3 to 5.5V
• Output Voltage: 1.2V
• Output Current: 0 to 3A
• Frequency of Operation: 3000 kHz
• Board Size: 2.016 × 1.08 inches (51.2 × 27.43 mm)
2 Evaluation Board Schematic
Figure 1. LMR10530 Evaluation Module Schematic
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Powering and Loading Considerations www.ti.com
3 Powering and Loading Considerations
Read this entire section prior to attempting to power the evaluation board.
3.1 Quick Start Procedure
Step 1: Set the bench power supply current limit to 3A. Set the power supply voltage to 4V. Turn off the
power supply output. Connect the power supply to the LMR10530 demo board. Positive connection to VIN
and negative connection to GND.
Step 2: Connect a load, as high as 3A, to the VOUT terminal. Positive connection to VOUT and negative
connection to GND.
Step 3: The EN pin should be left open for normal operation.
Step 4: Turn on the bench power supply with no load applied to the LMR10530. The VOUT would be in
regulation at a nominal 1.2V output.
Step 5: Slowly increase the load while monitoring the output voltage, VOUT should remain in regulation as
the load is increased up to 3 Amps. The LMR10530 is designed to skip some pulses at very light loads to
maintain output voltage regulation. Depending on load levels, the circuit may operate in either
discontinuous or continuous conduction mode.
Step 6: Slowly sweep the input voltage from 3 to 5.5V, VOUT should remain in regulation with a nominal
1.2V output.
3.2 Starting Up
By default, VINC is connected to VIN through a low pass filter to remove any high frequency noise present
at the input. EN is connected to VINC through a 100kΩresistor. A separate logic signal at the EN terminal
can be used, if startup and shutdown need to be controlled. The EN pin is tied to VIN to simplify start-up.
The pull-up resistor allows the power supply design engineer to toggle EN independently, if desired, and
observe the start-up behavior of the LMR10530.
3.3 Adjusting the Output Voltage
The output voltage is set using the following equation where Rfbb is connected between the FB pin and
GND, and Rfbt is connected between VOUT and FB.
VOUT = VFB(1 + (Rfbt/Rfbb)) (1)
The feedback voltage VFB is regulated at 0.60V typically.
Adjusting the output voltage will affect the performance of the LMR10530. In addition, output capacitors
might not be rated for the new output voltage. For more information, see LMR10530 SIMPLE SWITCHER
5.5Vin, 3.0A Step-Down Voltage Regulator in WSON-10 (SNVS814).
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Co
VOUT GND
Oscilloscope
www.ti.com Powering and Loading Considerations
3.4 Typical Test Setup
Figure 2. Efficiency Measurements
Figure 3. Voltage Ripple Measurements
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GND
EN
VIN SENSE+
SPARE
VOUT SENSE -
VOUT SENSE+
I I I I I I
I I I I I I
1 2 3 4 5 6
A B C D E F
VIN VOUT
GND
Powering and Loading Considerations www.ti.com
Figure 4. Edge Connector Schematic
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www.ti.com Board Images
4 Board Images
Figure 5. Top Side
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Board Images www.ti.com
Figure 6. Bottom Side
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VOUT = 1.2V
100 mV/Div
100 Ps/DIV
500 mA/Div
IOUT
VOUT = 1.2V
20 mV/Div
2V/Div
200 ns/DIV
VSW
VOUT = 1.2V
20 mV/Div
2V/Div
200 ns/DIV
VSW
0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
57
60
63
66
69
72
75
78
81
EFFICIENCY (%)
IOUT(A)
Vin = 3.0V
Vin = 3.5V
Vin = 4.0V
Vin = 4.2V
Vin = 4.6V
Vin = 4.8V
Vin = 5.2V
Vin = 5.5V
VOUT = 1.2V
500 mV/Div
1V/Div
100 Ps/DIV
VIN = 5.5V
2A/Div
IOUT = 3A
www.ti.com Typical Performance Characteristics
5 Typical Performance Characteristics
Efficiency vs Load Current
VOUT = 1.2V Startup
Steady-state (CCM Mode) Steady-state (DCM Mode)
VIN = 3V, IOUT = 3A VIN = 5.5V, IOUT = 0.025A
Load Transient
VIN = 5.5V, IOUT = 0.3A to 3A
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SNVU192A–October 2012–Revised April 2013 AN-2280 LMR10530 Evaluation Module
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Bill of Materials www.ti.com
6 Bill of Materials
Part ID Part Value Part Number Manufacturer
U1 3MHz 3.0A buck regulator, WSON-10 LMR10530 Texas Instruments
L1 1.2µH, 4.6A 7447745012 Wurth Elektronik eiSos
Cin 47µF, 10V, X5R, 1206 C3216X5R0J226M TDK
Cinc 0.22µF, 25V, X7R, 0603 06033D224KAT2A AVX
Co1 47µF, 10V, X5R, 1210 GRM32ER61A476KE20L Murata
D1 Schottky, 30V, 3A, 3-4E1A CMS01 Toshiba
Rfbt 2.00kΩ, 1%, 1/8W, 0603 CRCW06032K00FKEA Vishay
Rfbb 2.00kΩ, 1%, 1/8W, 0603 CRCW06032K00FKEA Vishay
Rinc 10.0Ω, 1%, 1/8W, 0603 CRCW060310R0FKEA Vishay
Ren 100kΩ, 1%, 1/8W, 0603 CRCW0603100KFKEA Vishay
VIN Test Point Loop 5010 Keystone
SW Test Point Loop 5012 Keystone
GND Test Point Loop 5011 Keystone
GND Test Point Loop 5011 Keystone
VOUT Test Point Loop 5013 Keystone
EN Test Point Loop 5014 Keystone
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www.ti.com Layout
7 Layout
Figure 7. Top Copper
Figure 8. Top Overlay
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Layout www.ti.com
Figure 9. Internal Plane 1
Figure 10. Internal Plane 2
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