Texas Instruments TPS7H1111EVM-CVAL User manual

User’s Guide
TPS7H1111EVM-CVAL Evaluation Module (EVM)
ABSTRACT
This user’s guide describes operational use of the TPS7H1111EVM-CVAL evaluation module (EVM) as a
reference design for engineering demonstration and evaluation of the TPS7H1111-SP, a 1.5-A, Ultra-Low Noise,
High PSRR, Radiation-Hardness-Assured RF Low Drop Out (LDO) regulator. This user's guide provides details
about the EVM, its configuration, schematics, and bill of material (BOM).
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Related Information............................................................................................................................................................3
1.2 Features............................................................................................................................................................................. 3
1.3 Applications........................................................................................................................................................................3
2 Setup........................................................................................................................................................................................4
2.1 Input/Output Connectors and Jumper Descriptions........................................................................................................... 4
2.2 Equipment Setup................................................................................................................................................................6
3 Operation.................................................................................................................................................................................6
4 Adjustable Operation..............................................................................................................................................................7
5 Test Results.............................................................................................................................................................................8
5.1 Enable and Soft Start Timing............................................................................................................................................. 8
5.2 PSRR................................................................................................................................................................................. 9
5.3 Stability.............................................................................................................................................................................10
5.4 Noise Spectral Density..................................................................................................................................................... 11
6 Board Layout.........................................................................................................................................................................12
7 Schematic..............................................................................................................................................................................16
8 Bill of Materials..................................................................................................................................................................... 17
List of Figures
Figure 1-1. TPS7H1111EVM-CVAL (LP052B)............................................................................................................................. 2
Figure 4-1. Simplified Schematic to Configure Output Voltage....................................................................................................7
Figure 5-1. TPS7H1111 enable and soft start timing................................................................................................................... 8
Figure 5-2. TPS7H1111EVM-CVAL PSRR vs IOUT ..................................................................................................................... 9
Figure 5-3. TPS7H1111EVM-CVAL Gain and Phase vs. Frequency (Bode Plot)...................................................................... 10
Figure 5-4. Output Noise vs. Frequency across Output Current (Noise Spectral Density)........................................................11
Figure 6-1. Top Overlay Silkscreen............................................................................................................................................12
Figure 6-2. Top Solder Mask......................................................................................................................................................12
Figure 6-3. Top Signal Layer......................................................................................................................................................13
Figure 6-4. Signal 1 Layer......................................................................................................................................................... 13
Figure 6-5. Signal 2 Layer......................................................................................................................................................... 14
Figure 6-6. Bottom Signal Layer................................................................................................................................................ 14
Figure 6-7. Bottom Solder Layer................................................................................................................................................15
Figure 7-1. TPS7H1111EVM-CVAL (LP052B) Schematic..........................................................................................................16
List of Tables
Table 2-1. Jumpers...................................................................................................................................................................... 4
Table 2-2. Test Points.................................................................................................................................................................. 5
Table 8-1. Bill of Materials..........................................................................................................................................................17
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
The TPS7H1111-SP is an ultra-low noise, high PSRR, low dropout linear regulator (LDO) optimized for powering
RF (radio frequency) devices in a space environment. It is capable of sourcing up to 1.5 A over a 0.85-V to 7-V
input range with a 2.2-V to 14-V bias supply.
The EVM is configured with a default output resistor to regulate to a 1.8 V VOUT, with a usable VIN range of
(1.8 V + VDO) to 7 V with VBIAS range of (VOUT + 1.6 V to 14 V). Worst case VDO ranges from 430mV for VBIAS
≥ (VOUT + 1.6 V) to 1.4 V with VBIAS = VIN across recommended operating conditions. The EVM is intended to
aid engineers in the evaluation of the operation and performance of the TPS7H1111-SP linear regulator. The
TPS7H1111-SP low-dropout regulator allows input voltages from 0.85 V to 7 V and is capable of regulating any
output voltage between 0.4 V and up to 5.5 V by changing the VOUT current setting resistor R8. The EVM is
capable of delivering up to 1.5 A to a load. Achieving the maximum load depends on multiple variables, including
the input-output power dissipation, board thermal dissipation, and heat removal.
Figure 1-1. TPS7H1111EVM-CVAL (LP052B)
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1.1 Related Information
• TPS7H1111-SP data sheet (SLVSFT8)
1.2 Features
• Radiation Performance
– Radiation hardness assurance (RHA) up to a total ionizing dose (TID) of 100 krad(Si)
– Single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) immune to
linear energy transfer (LET) = 75 MeV-cm2/mg
– Single-event functional interrupt (SEFI) and single-event transient (SET) characterized to LET = 75 MeV-
cm2/mg
Ultra-Low Noise: 1.71 µVRMS (typ), 10 Hz - 100 kHz
• High power-supply rejection ratio, PSRR (typ):
– 109 dB at 100 Hz
– 71 dB at 100 kHz
– 66 dB at 1 MHz
• Input voltage range from 0.85 V to 7 V
• Bias supply of 2.2 V to 14 V to minimize power dissipation
• Output voltage as low as 0.4 V
• Up to 1.5-A output current
• Excellent output accuracy over line and load:
– +1.1% / –1.3% across temperature
– +0.9% / -0.7% at 25°C
• Low-dropout: 215 mV (typ) at 1.5 A
• Programmable soft start control (SS_SET)
• Open-drain power good (PG) indicator
• Configurable power good threshold (FB_PG)
• Exposed control loop with the external compensation STAB pin
• Internal current limit with configurable behavior
• Capable of current sharing to enable higher currents
1.3 Applications
•Satellite electrical power system (EPS)
• Power for high-speed and high-accuracy analog circuits
– Data Converters: ADCs and DACs (analog-to-digital and digital-to-analog converters)
– VCOs (voltage controlled oscillators)
– PLLs (phase-lock-loops)
– SerDes (serializer and deserializers)
– Imaging sensors
• Accurate supply for FPGAs (field programmable gate arrays) and DSPs (digital signal processors)
• Radiation-hardened ultra-clean analog supply for space constrained areas
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2 Setup
This section describes the jumpers and connectors on the EVM as well as how to properly connect, set up, and
use the TPS7H1111EVM-CVAL.
2.1 Input/Output Connectors and Jumper Descriptions
2.1.1 Jumpers
Table 2-1 contains the list of jumpers and descriptions of their function(s).
Table 2-1. Jumpers
Schematic
Reference
Description
J1 VIN Input power banana jack. 0.85 to 7 V.
J2 VOUT Output regulated power banana jack. As configured VOUT = 1.8 V.
J3 GND for VIN banana jack.
J4 VCOUT Output regulated power SMA.
J5 VOUT Output regulated power SMA.
J6 VOUT Output regulated power cold nose probe connector.
J7 VBIAS Bias input power banana jack. 2.2 to 14 V.
J8 VBIAS Bias input power SMA.
J9 GND for VOUT banana jack.
J10 GND for VIN banana jack.
J11 GND for VBIAS banana jack.
J12 Three pin current limit mode jumper selector. Selects "Constant current" or "Turn-off" current limit mode.
J13 Three pin enable/disable jumper selector. Pulls EN signal to VIN "enable" or GND "disable". No jumper will enable LDO
based on VIN R2/R7 divider reaching 600mV enable threshold.
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2.1.2 Test Points
Table 2-2 contains the list of test point and descriptions of their function(s).
Table 2-2. Test Points
Schematic
Reference
Description
TP1 VOUT Test point. This test point is prior to 0 Ω R1, and directly connected to OUT pins of LDO.
TP2, TP3 VCOUT Test points. These test points are after the 0 Ω R1. They are on the COUT plane. TP2 is used for Bode signal
injection along with TP8.
TP4 VOUT Test point. This test point is after L1 (populated with 0 Ω) in the output path. This testpoint is outside the feedback
loop.
TP5 VIN Test point.
TP6 PG power good test point.
TP7 EN enable test point.
TP8 Feedback OUTS test point. Used for Bode signal injection along with TP2.
TP9 SS_SET test point. This node defines VOUT regulation, and soft start.
TP10 Bias test point, located on device side of the bias filter defined by R6 and C14.
TP11 GND test point.
TP12 Bias test point, located on source side of the bias filter defined by R6 and C14.
TP13 FB_PG test point.
TP14, TP15 GND test points.
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2.2 Equipment Setup
The following procedure guides the setup and testing of the TPS7H1111EVM-CVAL.
The following equipment is required for this testing:
1. Power supply PS1 capable of up to 7 V and 1.5 A for suppling VIN.
• If testing current limit functionality, PS1 should be capable of 3 A.
2. Power supply PS2 capable of up to 14 V and 100 mA.
3. Eload or resistive load capable of > 1.5 A (or desired test load).
4. Voltage meter and/or oscilloscope for monitoring VOUT.
The following procedure describes the connectivity, supplies, and load setup:
1. With PS1 disabled, setup with 2.5 V, and 1.5 A current limit.
2. Connect PS1 positive supply with banana cable to VIN + jumper J1.
3. Connect PS1 negative supply with banana cable to VIN GND jumper J10.
• Alternately, VIN can be supplied with SMA J3. Observe current ratings of SMA cable.
4. With PS2 disabled, setup with 5 V, and 100 mA current limit.
5. Connect PS2 positive supply with banana cable to VBIAS + jumper J7.
6. Connect PS2 negative supply with banana cable to VBIAS GND jumper J11.
• Alternately, VBIAS can be supplied with SMA J8.
7. Connect oscilloscope to SMA jack J5 if desired to monitor VOUT.
• Alternatively, the cold nose connector J6 or TP4 may be used for VOUT monitoring.
8. Connect voltage meter to VOUT using TP4, J6, J5, or J2 if needed.
9. Connect desired (≤1.5 A) load between the VOUT connector J2, and the GND at connector J9.
Note
Large VIN – VOUT differentials can lead to excessive internal power dissipation when operating at
higher ILOAD currents. Internal power dissipation power can be estimated with VIN – VOUT × ILOAD. See
SLVSFT8 for more information on power calculations
3 Operation
1. Set jumper J13 to the enable position.
• J13 can also be left open, as a resistor divider is used with VIN to pull the enable pin up. Enable threshold
is ~600mV. Resistor divider R2/R7 can be changed to achieve different turn on voltages for VIN. By
default, device will be enabled when VIN > ~1.8 V for default EVM. It can also be digitally controlled from
a host through J13.
2. Enable PS1, and PS2. Sequence is not important.
3. VOUT should now read ~1.8 V.
• VOUT at load will likely be lower than 1.8 V when load applied. The OUTS connection for feedback
regulation is located on the COUT plane closer to U1.
4. PG output (TP6) should also now be pulled up to VOUT and read 1.8 V.
5. Vary the load as necessary for test purposes.
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4 Adjustable Operation
The nominal output voltage for the TPS7H1111-SP is configured using equation VSS_SET = VOUT = ISET x RSET.
Therefore, RSET = VSS_SET / ISET = 1.8 V / 100 μA = 18 kΩ. ISET is determined by RREF, and is designed to be
100 uA using a precision 12 kΩ resistor. See Figure 4-1 for block diagram. See Figure 7-1 for RSET (R8), and
RREF (R9) connectivity. See SLVSFT8 for more detailed information.
IN
+
-
+
-
+
-
OUTS
OUT
1.2V VREF
REF
SS_SET
ISET = IREF
12kŸ12kŸ
RSET RSET
Input supply
Output load
AVDD
Figure 4-1. Simplified Schematic to Configure Output Voltage
It is also important to note that the TPS7H1111-SP utilizes an adjustable power good PG output threshold
FB_PG. When changing the output voltage, a suitable voltage divider needs to be set on the FB_PG pin in order
for the LDO to assert PG when appropriate threshold achieved. Additionally when PG is asserted, this turns off
internal fast charge circuit that is part of the soft start. Thus, setting appropriate divider is important for proper
startup. See SLVSFT8 for more detailed information.
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5 Test Results
This section provides typical performance waveforms for the TPS7H1111EVM-CVAL with respect to stability,
Noise Spectral Density (NSD), and PSRR. All performance data show is utilizing the the standard configuration
of the EVM. The standard configuration is based on the following conditions: Vin = 2.5 V, Vbias = 5 V, and Vout =
1.8 V
Note
The datasheet for the TPS7H1111-SP LDO contains a wide assortment of additional performance data
under various input and output conditions. See SLVSFT8
5.1 Enable and Soft Start Timing
Figure 5-1 shows the enable and soft start characteristic where VIN is 2.5 V, VBIAS is 5 V, EN is toggled from
ground to ~800 mV while the output drives a ~1.5 A resistive load. The waveforms for EN, VOUT, SS_SET, and
IOUT are shown for reference. CSS of 4.7uF results in a soft start time of approximately 3.7 ms.
Figure 5-1. TPS7H1111 enable and soft start timing
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5.2 PSRR
Figure 5-2 shows the typical PSRR performance of the TPS7H1111EVM-CVAL at various IOUT loads under the
following conditions: VIN = 2.5 V, VBIAS = 5 V, VOUT = 1.8 V, CIN removed.
Frequency (Hz)
PSRR (dB)
0
20
40
60
80
100
120
140
10 100 1k 10k 100k 1M 10M
IOUT = 1.5 A
IOUT = 1 A
IOUT = 500 mA
IOUT = 100 mA
IOUT = 10 mA
IOUT = 1 mA
Figure 5-2. TPS7H1111EVM-CVAL PSRR vs IOUT
Measuring ultra high PSRR on a device can be challenging. To obtain adequate results, the output of the LDO is
fed to a wideband amplifier with approximately 50 dB of gain. Amplifying the output effectively lowers the noise
floor of the measuring instrument. Once results are obtained, the gain curve of the amplifier in dBs is added to
the results across the frequency span.
The injected signal on VIN was -10 dBm into a 50 Ω load. This results in a 200 mV pk-pk signal. Additionally a
small variable amount of injected signal attenuation was used starting at 100 kHz to minimize signal distortion at
higher frequencies. Final injected signal power used was -17 dBm at approximatly 2 MHz.
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5.3 Stability
Figure 5-3 shows the typical Bode gain and phase plot versus frequency for minimum no load, and maximum
load of 1.5 A. Stability tests performed with the TPS7H1111EVM-CVAL operating with the following conditions:
VIN = 2.5 V, VBIAS = 5 V, VOUT = 1.8 V.
Frequency (Hz)
Gain (dB)
Phase (degrees)
-100 -200
-80 -160
-60 -120
-40 -80
-20 -40
0 0
20 40
40 80
60 120
80 160
100 200
1k 10k 100k 1M 10M
Gain 0 A
Phase 0 A
Gain 1.5 A
Phase 1.5 A
Figure 5-3. TPS7H1111EVM-CVAL Gain and Phase vs. Frequency (Bode Plot)
Measuring accurate Bode response with a high bandwidth high gain LDO required using a very small injected
signal. The signal injected used a shape for injected level with an injected signal reference level of -7 dBm. This
reference level was reduced to -27 dBm from 10 kHz to 200 kHz. Additionally, the entire injected signal was
externally attenuated with an inline attenuator by 26 dB. This was required to prevent overdriving the signal into
feedback loop and keeping response within small signal behavior.
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5.4 Noise Spectral Density
Figure 5-4 shows the typical Noise Spectral Density (NSD) performance of the TPS7H1111EVM-CVAL operating
with the following conditions: VIN = 2.5 V, VBIAS = 5 V, VOUT = 1.8 V. The plot also shows the integrated 10 Hz to
100 kHz RMS noise for the various output loads.
Frequency (Hz)
Noise (nV/vHz)
10 100 1k 10k 100k 1M 10M1
10000
1000
100
10
1
0.1
IOUT = 1.5 A, 1.68 µVRMS
IOUT = 1 A, 1.67 µVRMS
IOUT = 500 mA, 1.65 µVRMS
IOUT = 100 mA, 1.69 µVRMS
IOUT = 10 mA, 1.76 µVRMS
IOUT = 1 mA, 1.76 µVRMS
Figure 5-4. Output Noise vs. Frequency across Output Current (Noise Spectral Density)
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6 Board Layout
The following images represent the board design layers.
Figure 6-1. Top Overlay Silkscreen
Figure 6-2. Top Solder Mask
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Figure 6-3. Top Signal Layer
Figure 6-4. Signal 1 Layer
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Figure 6-5. Signal 2 Layer
Figure 6-6. Bottom Signal Layer
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Figure 6-7. Bottom Solder Layer
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7 Schematic
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
1 2
8/16/2022
LP052B.SchDoc
Sheet Title:
Size:
Mod. Date:
File:
Sheet: of
B http://www.ti.com
Contact: http://www.ti.com/support
TPS7H1111-SPProject Title:
Designed for: Public Release
Assembly Variant: 001
© Texas Instruments 2022
Drawn By:
Engineer:
Wade Vonbergen
Wade Vonbergen
Texas Instruments and/or its licensors do not warrant the accuracy or completeness of this specification or any information contained therein. Texas Instruments and/or its licensors do not
warrant that this design will meet the specifications, will be suitable for your application or fit for any particular purpose, or will operate in an implementation. Texas Instruments and/or its
licensors do not warrant that the design is production worthy. You should completely validate and test your design implementation to confirm the system functionality for your application.
Not in version controlSVN Rev:
LP052Number: Rev: B
TID #: N/A
Orderable: TPS7H1111EVM-CVAL
TPS7H1111-SP EVM - Schematic
OUTPUT (0.4 V - 5.5 V @ 1.5 A)
INPUT (0.85 V - 7 V)
TP1 TP2 TP3 TP4
TP5
OUT
VIN
COUT
VOUT
VIN
J1
J2
1210
0.75W
L1
750mW
1%
1210
0
R1
10%
0805
1µF
25V
C3
10%
0603
100nF
25V
C4
0603
1%
0.1W
75V
56.2k
R2
20%
25V
1206
10µF
C2
10%
0603
100nF
25V
C5
10%
0805
1µF
25V
C6
10%
1812_280
50V
6.8uF
C7
10%
0603
100nF
25V
C10
1
2 3 4 5
J3
VIN
1
2 3 4 5
J4
1
2 3 4 5
J5
STAB
CLM
CLM TP6
TP7
EN PG
TP8
EN
0603
0.1%
0.1W
75V
44.2k
R5
SS_SET OUTS
BIAS (2.2 V - 14 V)
TP9 REF FB_PG
1
2 3 4
5
J6
TP10
BIAS
1%
0805
.5W
10.0
R6 TP11
TP12
BIAS
GND STABBIAS GND
J7
TP13
0603
1%
0.1W
75V
28.0k
R7
100mW
0603
0.1%
18.0k
R8
0.1%
0603
0.1W
12.0k
R9
6032-28
10%
35V
10uF
C12
10%
1812_220
50V
4.7uF
C13
10%
1812_220
50V
4.7uF
C14
0603
0.1%
0.1W
75V
10.0k
R10
5%
0805
16V
0.01uF
C15
1
2 3 4
5
J8
BIAS
TP14
GND
J9
TP15
GND
J10
J11
VIN
1
2
3
J12
22284030
CLM
Constant CL
Turn-off CL
VIN
1
2
3
J13
22284030
OUT VOUTCOUT
EN VOUTCOUTEnable
Dis able
10%
0805
1µF
25V
C16
10%
0603
100nF
25V
C17
10%
0603
100nF
25V
C18
10%
0603
100nF
25V
C19
10%
0603
100nF
25V
C20
10%
0805
1µF
25V
C21
10%
1812_280
50V
6.8uF
C22
TP caps & additional DNP'd cap to
test placement of the small ceramic
cap for impact on magnetic coupling.
Being placed too close to the device
can theoretically cause issues.
IN
3
IN
4OUT 11
OUT 12
BIAS
1
CLM
5
EN
2
FB_PG 14
OUTS 13
PG 7
REF
8
SS_SET
9
STAB 10
Thermal_Pad 15
GND 6
TPS7H1111HBL/EM
U1
7343
20V
10%
100µF
C1
100mW
0.5%
0603
75V
5.05k
R11
0805
5%
25V
4700pF
C11
NOTE: L1 Populated with 0Ω resistor
0603
0.1%
0.1W
75V
10.0k
R12
0603
0.1%
0.1W
75V
10.0k
R3
51.0
R4
+
20V
100uF
10%
7343
C8
+
20V
100uF
10%
7343
C9
Figure 7-1. TPS7H1111EVM-CVAL (LP052B) Schematic
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8 Bill of Materials
Table 8-1. Bill of Materials
Designator Qty Description Part Number Manufacturer
C1 1 Capacitor, tantalum, 100 μF, 20 V, ±10%, 0.4 Ω, AEC-
Q200 Grade 1, SMD, 7343-43
TAJE107K020TNJV AVX
C3 1 Capacitor, ceramic, 1 μF, 25 V, ±10%, X7R, 0805 TMK212B7105KG-T Taiyo Yuden
C4 1 Capacitor, ceramic, 0.1 μF, 25 V, ±10%, X7R, 0603 8.85012E+11 Wurth Elektronik
C8, C9 2 Capacitor, tantalum Solid 100 μF 20 V E CASE 10% (7.3 x
4.3 x 4.1mm) SMD 7343-43 0.035 Ohm 125°C Bulk, 2917
TBME107K020LBLC9945 KYOCERA AVX, (alt
TRME107K020R0035)
C11 1 Capacitor, ceramic, 4700 pF, 25 V, ±5%, C0G/NP0, 0805 08053A472JAT2A AVX
C12 1 Capacitor, tantalum, 10 μF, 35 V, ±10%, 1.6 Ω, SMD,
6032-28
293D106X9035C2TE3 Vishay-Sprague
C13, C14 2 Capacitor, ceramic, 4.7 μF, 50 V, ±10%, X7R, AEC-Q200
Grade 1,
CGA8M3X7R1H475K200KB TDK
J1, J2, J7,
J9, J10, J11
6 Standard banana jack, uninsulated, 5.5 mm 575-4 Keystone
J3, J4, J5,
J8
4 SMA Connector Receptacle, Female Socket 50 Ω
Through Hole Solder, PTH_RF_CONN
733910060 Molex
J6 1 Compact Probe Tip Circuit Board Test Points, TH, 25 per,
TH Scope Probe
131-5031-00 Tektronix
J12, J13 2 Header, 2.54 mm, 3x1, tin, TH 22284030 Molex
L1, R1 2 Resistor, 0 Ω, 1%, 0.75 W, AEC-Q200 Grade 0, 1210 CRCW12100000Z0EAHP Vishay-Dale
R2 1 Resistor, 56.2 kΩ, 1%, 0.1 W, 0603 RC0603FR-0756K2L Yageo
R3, R10,
R12
3 Resistor, 10.0 kΩ, 0.1%, 0.1 W, 0603 RT0603BRD0710KL Yageo America
R4 1 Resistor, 51.0 Ω, 1%, 0.1 W, 0603 RC0603FR-0751RL Yageo
R5 1 Resistor, 44.2 kΩ, 0.1%, 0.1 W, 0603 RT0603BRD0744K2L Yageo America
R6 1 Resistor, 10.0 Ω, 1%, .5 W, AEC-Q200 Grade 0, 0805 ERJ-P6WF10R0V Panasonic
R7 1 Resistor, 28.0 kΩ, 1%, 0.1 W, 0603 RC0603FR-0728KL Yageo
R8 1 Resistor, 18.0 kΩ, 0.1%, 0.1 W, 0603 RT0603BRD0718KL Yageo America
R9 1 Resistor, 12.0 kΩ, 0.1%, 0.1 W, 0603 RT0603BRD0712KL Yageo America
R11 1 Resistor, 5.05 kΩ, 0.5%, 0.1 W, 0603 RT0603DRE075K05L Yageo America
TP1, TP2,
TP3, TP4,
TP5, TP10,
TP12
7 Test point, multipurpose, red, TH 5010 Keystone Electronics
TP6, TP7,
TP8, TP9,
TP13
5 Test point, multipurpose, yellow, TH 5014 Keystone Electronics
TP11, TP14,
TP15
3 Test point, multipurpose, black, TH 5011 Keystone Electronics
U1 1 1.5-A, Ultra-Low Noise, High PSRR, RHA, RF LDO
CFP14
TPS7H1111HBL/EM Texas Instruments
C2 0 Capacitor, tantalum polymer, 10 μF, 25 V, ± 20%, 0.15 Ω,
3216-18 SMD
TCJA106M025R0150 AVX
C5, C10,
C17, C18,
C19, C20
0 Capacitor, ceramic, 0.1 μF, 25 V, ±10%, X7R, 0603 C1608X7R1E104K080AA TDK
C6, C16,
C21
0 Capacitor, ceramic, 1 μF, 25 V, ±10%, X7R, 0805 TMK212B7105KG-T Taiyo Yuden
C7, C22 0 Capacitor, ceramic, 6.8 μF, 50 V, ± 10%, X7R, AEC-Q200
Grade 1,
CGA8P3X7R1H685K250KB TDK
C15 0 Capacitor, ceramic, 0.01 μF, 16 V, ±5%, C0G/NP0, 0805 B37947K9103J62 TDK
www.ti.com Bill of Materials
SLVUCG5 – JANUARY 2023
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TPS7H1111EVM-CVAL Evaluation Module (EVM) 17
Copyright © 2023 Texas Instruments Incorporated

STANDARD TERMS FOR EVALUATION MODULES
1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or
documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance
with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.
1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility
evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not
finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For
clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions
set forth herein but rather shall be subject to the applicable terms that accompany such Software
1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned,
or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production
system.
2Limited Warranty and Related Remedies/Disclaimers:
2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License
Agreement.
2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM
to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by
neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have
been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications
or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control
techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM.
User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10)
business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.
2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit
User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty
period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or
replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be
warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day
warranty period.
WARNING
Evaluation Kits are intended solely for use by technically qualified,
professional electronics experts who are familiar with the dangers
and application risks associated with handling electrical mechanical
components, systems, and subsystems.
User shall operate the Evaluation Kit within TI’s recommended
guidelines and any applicable legal or environmental requirements
as well as reasonable and customary safeguards. Failure to set up
and/or operate the Evaluation Kit within TI’s recommended
guidelines may result in personal injury or death or property
damage. Proper set up entails following TI’s instructions for
electrical ratings of interface circuits such as input, output and
electrical loads.
NOTE:
EXPOSURE TO ELECTROSTATIC DISCHARGE (ESD) MAY CAUSE DEGREDATION OR FAILURE OF THE EVALUATION
KIT; TI RECOMMENDS STORAGE OF THE EVALUATION KIT IN A PROTECTIVE ESD BAG.

www.ti.com
2
3Regulatory Notices:
3.1 United States
3.1.1 Notice applicable to EVMs not FCC-Approved:
FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software
associated with the kit to determine whether to incorporate such items in a finished product and software developers to write
software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or
otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition
that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference.
Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must
operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.
3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:
CAUTION
This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not
cause harmful interference, and (2) this device must accept any interference received, including interference that may cause
undesired operation.
Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to
operate the equipment.
FCC Interference Statement for Class A EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is
operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the instruction manual, may cause harmful interference to radio communications.
Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to
correct the interference at his own expense.
FCC Interference Statement for Class B EVM devices
NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of
the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential
installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance
with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference
will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which
can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
3.2 Canada
3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247
Concerning EVMs Including Radio Transmitters:
This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions:
(1) this device may not cause interference, and (2) this device must accept any interference, including interference that may
cause undesired operation of the device.
Concernant les EVMs avec appareils radio:
Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation
est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit
accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.
Concerning EVMs Including Detachable Antennas:
Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser)
gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type
and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for
successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types
listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated.
Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited
for use with this device.

www.ti.com
3
Concernant les EVMs avec antennes détachables
Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et
d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage
radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope
rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le
présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le
manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne
non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de
l'émetteur
3.3 Japan
3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に
輸入される評価用キット、ボードについては、次のところをご覧ください。
https://www.ti.com/ja-jp/legal/notice-for-evaluation-kits-delivered-in-japan.html
3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified
by TI as conforming to Technical Regulations of Radio Law of Japan.
If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the
instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs
(which for the avoidance of doubt are stated strictly for convenience and should be verified by User):
1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal
Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for
Enforcement of Radio Law of Japan,
2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to
EVMs, or
3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan
with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note
that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.
【無線電波を送信する製品の開発キットをお使いになる際の注意事項】 開発キットの中には技術基準適合証明を受けて
いないものがあります。 技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの
措置を取っていただく必要がありますのでご注意ください。
1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用
いただく。
2. 実験局の免許を取得後ご使用いただく。
3. 技術基準適合証明を取得後ご使用いただく。
なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。
上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。 日本テキサス・イ
ンスツルメンツ株式会社
東京都新宿区西新宿６丁目２４番１号
西新宿三井ビル
3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page
電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧くださ
い。https://www.ti.com/ja-jp/legal/notice-for-evaluation-kits-for-power-line-communication.html
3.4 European Union
3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive):
This is a class A product intended for use in environments other than domestic environments that are connected to a
low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this
product may cause radio interference in which case the user may be required to take adequate measures.