Texas Instruments TPS7H1111EVM-CVAL User manual

User’s Guide
TPS7H1111EVM-CVAL Evaluation Module (EVM)
ABSTRACT
This user’s guide describes operational use of the TPS7H1111EVM-CVAL evaluation module (EVM) as a
reference design for engineering demonstration and evaluation of the TPS7H1111-SP, a 1.5-A, Ultra-Low Noise,
High PSRR, Radiation-Hardness-Assured RF Low Drop Out (LDO) regulator. This user's guide provides details
about the EVM, its configuration, schematics, and bill of material (BOM).
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Related Information............................................................................................................................................................3
1.2 Features............................................................................................................................................................................. 3
1.3 Applications........................................................................................................................................................................3
2 Setup........................................................................................................................................................................................4
2.1 Input/Output Connectors and Jumper Descriptions........................................................................................................... 4
2.2 Equipment Setup................................................................................................................................................................6
3 Operation.................................................................................................................................................................................6
4 Adjustable Operation..............................................................................................................................................................7
5 Test Results.............................................................................................................................................................................8
5.1 Enable and Soft Start Timing............................................................................................................................................. 8
5.2 PSRR................................................................................................................................................................................. 9
5.3 Stability.............................................................................................................................................................................10
5.4 Noise Spectral Density..................................................................................................................................................... 11
6 Board Layout.........................................................................................................................................................................12
7 Schematic..............................................................................................................................................................................16
8 Bill of Materials..................................................................................................................................................................... 17
List of Figures
Figure 1-1. TPS7H1111EVM-CVAL (LP052B)............................................................................................................................. 2
Figure 4-1. Simplified Schematic to Configure Output Voltage....................................................................................................7
Figure 5-1. TPS7H1111 enable and soft start timing................................................................................................................... 8
Figure 5-2. TPS7H1111EVM-CVAL PSRR vs IOUT ..................................................................................................................... 9
Figure 5-3. TPS7H1111EVM-CVAL Gain and Phase vs. Frequency (Bode Plot)...................................................................... 10
Figure 5-4. Output Noise vs. Frequency across Output Current (Noise Spectral Density)........................................................11
Figure 6-1. Top Overlay Silkscreen............................................................................................................................................12
Figure 6-2. Top Solder Mask......................................................................................................................................................12
Figure 6-3. Top Signal Layer......................................................................................................................................................13
Figure 6-4. Signal 1 Layer......................................................................................................................................................... 13
Figure 6-5. Signal 2 Layer......................................................................................................................................................... 14
Figure 6-6. Bottom Signal Layer................................................................................................................................................ 14
Figure 6-7. Bottom Solder Layer................................................................................................................................................15
Figure 7-1. TPS7H1111EVM-CVAL (LP052B) Schematic..........................................................................................................16
List of Tables
Table 2-1. Jumpers...................................................................................................................................................................... 4
Table 2-2. Test Points.................................................................................................................................................................. 5
Table 8-1. Bill of Materials..........................................................................................................................................................17
Trademarks
All trademarks are the property of their respective owners.
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1 Introduction
The TPS7H1111-SP is an ultra-low noise, high PSRR, low dropout linear regulator (LDO) optimized for powering
RF (radio frequency) devices in a space environment. It is capable of sourcing up to 1.5 A over a 0.85-V to 7-V
input range with a 2.2-V to 14-V bias supply.
The EVM is configured with a default output resistor to regulate to a 1.8 V VOUT, with a usable VIN range of
(1.8 V + VDO) to 7 V with VBIAS range of (VOUT + 1.6 V to 14 V). Worst case VDO ranges from 430mV for VBIAS
≥ (VOUT + 1.6 V) to 1.4 V with VBIAS = VIN across recommended operating conditions. The EVM is intended to
aid engineers in the evaluation of the operation and performance of the TPS7H1111-SP linear regulator. The
TPS7H1111-SP low-dropout regulator allows input voltages from 0.85 V to 7 V and is capable of regulating any
output voltage between 0.4 V and up to 5.5 V by changing the VOUT current setting resistor R8. The EVM is
capable of delivering up to 1.5 A to a load. Achieving the maximum load depends on multiple variables, including
the input-output power dissipation, board thermal dissipation, and heat removal.
Figure 1-1. TPS7H1111EVM-CVAL (LP052B)
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1.1 Related Information
• TPS7H1111-SP data sheet (SLVSFT8)
1.2 Features
• Radiation Performance
– Radiation hardness assurance (RHA) up to a total ionizing dose (TID) of 100 krad(Si)
– Single-event latchup (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR) immune to
linear energy transfer (LET) = 75 MeV-cm2/mg
– Single-event functional interrupt (SEFI) and single-event transient (SET) characterized to LET = 75 MeV-
cm2/mg
Ultra-Low Noise: 1.71 µVRMS (typ), 10 Hz - 100 kHz
• High power-supply rejection ratio, PSRR (typ):
– 109 dB at 100 Hz
– 71 dB at 100 kHz
– 66 dB at 1 MHz
• Input voltage range from 0.85 V to 7 V
• Bias supply of 2.2 V to 14 V to minimize power dissipation
• Output voltage as low as 0.4 V
• Up to 1.5-A output current
• Excellent output accuracy over line and load:
– +1.1% / –1.3% across temperature
– +0.9% / -0.7% at 25°C
• Low-dropout: 215 mV (typ) at 1.5 A
• Programmable soft start control (SS_SET)
• Open-drain power good (PG) indicator
• Configurable power good threshold (FB_PG)
• Exposed control loop with the external compensation STAB pin
• Internal current limit with configurable behavior
• Capable of current sharing to enable higher currents
1.3 Applications
•Satellite electrical power system (EPS)
• Power for high-speed and high-accuracy analog circuits
– Data Converters: ADCs and DACs (analog-to-digital and digital-to-analog converters)
– VCOs (voltage controlled oscillators)
– PLLs (phase-lock-loops)
– SerDes (serializer and deserializers)
– Imaging sensors
• Accurate supply for FPGAs (field programmable gate arrays) and DSPs (digital signal processors)
• Radiation-hardened ultra-clean analog supply for space constrained areas
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2 Setup
This section describes the jumpers and connectors on the EVM as well as how to properly connect, set up, and
use the TPS7H1111EVM-CVAL.
2.1 Input/Output Connectors and Jumper Descriptions
2.1.1 Jumpers
Table 2-1 contains the list of jumpers and descriptions of their function(s).
Table 2-1. Jumpers
Schematic
Reference
Description
J1 VIN Input power banana jack. 0.85 to 7 V.
J2 VOUT Output regulated power banana jack. As configured VOUT = 1.8 V.
J3 GND for VIN banana jack.
J4 VCOUT Output regulated power SMA.
J5 VOUT Output regulated power SMA.
J6 VOUT Output regulated power cold nose probe connector.
J7 VBIAS Bias input power banana jack. 2.2 to 14 V.
J8 VBIAS Bias input power SMA.
J9 GND for VOUT banana jack.
J10 GND for VIN banana jack.
J11 GND for VBIAS banana jack.
J12 Three pin current limit mode jumper selector. Selects "Constant current" or "Turn-off" current limit mode.
J13 Three pin enable/disable jumper selector. Pulls EN signal to VIN "enable" or GND "disable". No jumper will enable LDO
based on VIN R2/R7 divider reaching 600mV enable threshold.
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2.1.2 Test Points
Table 2-2 contains the list of test point and descriptions of their function(s).
Table 2-2. Test Points
Schematic
Reference
Description
TP1 VOUT Test point. This test point is prior to 0 Ω R1, and directly connected to OUT pins of LDO.
TP2, TP3 VCOUT Test points. These test points are after the 0 Ω R1. They are on the COUT plane. TP2 is used for Bode signal
injection along with TP8.
TP4 VOUT Test point. This test point is after L1 (populated with 0 Ω) in the output path. This testpoint is outside the feedback
loop.
TP5 VIN Test point.
TP6 PG power good test point.
TP7 EN enable test point.
TP8 Feedback OUTS test point. Used for Bode signal injection along with TP2.
TP9 SS_SET test point. This node defines VOUT regulation, and soft start.
TP10 Bias test point, located on device side of the bias filter defined by R6 and C14.
TP11 GND test point.
TP12 Bias test point, located on source side of the bias filter defined by R6 and C14.
TP13 FB_PG test point.
TP14, TP15 GND test points.
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2.2 Equipment Setup
The following procedure guides the setup and testing of the TPS7H1111EVM-CVAL.
The following equipment is required for this testing:
1. Power supply PS1 capable of up to 7 V and 1.5 A for suppling VIN.
• If testing current limit functionality, PS1 should be capable of 3 A.
2. Power supply PS2 capable of up to 14 V and 100 mA.
3. Eload or resistive load capable of > 1.5 A (or desired test load).
4. Voltage meter and/or oscilloscope for monitoring VOUT.
The following procedure describes the connectivity, supplies, and load setup:
1. With PS1 disabled, setup with 2.5 V, and 1.5 A current limit.
2. Connect PS1 positive supply with banana cable to VIN + jumper J1.
3. Connect PS1 negative supply with banana cable to VIN GND jumper J10.
• Alternately, VIN can be supplied with SMA J3. Observe current ratings of SMA cable.
4. With PS2 disabled, setup with 5 V, and 100 mA current limit.
5. Connect PS2 positive supply with banana cable to VBIAS + jumper J7.
6. Connect PS2 negative supply with banana cable to VBIAS GND jumper J11.
• Alternately, VBIAS can be supplied with SMA J8.
7. Connect oscilloscope to SMA jack J5 if desired to monitor VOUT.
• Alternatively, the cold nose connector J6 or TP4 may be used for VOUT monitoring.
8. Connect voltage meter to VOUT using TP4, J6, J5, or J2 if needed.
9. Connect desired (≤1.5 A) load between the VOUT connector J2, and the GND at connector J9.
Note
Large VIN – VOUT differentials can lead to excessive internal power dissipation when operating at
higher ILOAD currents. Internal power dissipation power can be estimated with VIN – VOUT × ILOAD. See
SLVSFT8 for more information on power calculations
3 Operation
1. Set jumper J13 to the enable position.
• J13 can also be left open, as a resistor divider is used with VIN to pull the enable pin up. Enable threshold
is ~600mV. Resistor divider R2/R7 can be changed to achieve different turn on voltages for VIN. By
default, device will be enabled when VIN > ~1.8 V for default EVM. It can also be digitally controlled from
a host through J13.
2. Enable PS1, and PS2. Sequence is not important.
3. VOUT should now read ~1.8 V.
• VOUT at load will likely be lower than 1.8 V when load applied. The OUTS connection for feedback
regulation is located on the COUT plane closer to U1.
4. PG output (TP6) should also now be pulled up to VOUT and read 1.8 V.
5. Vary the load as necessary for test purposes.
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4 Adjustable Operation
The nominal output voltage for the TPS7H1111-SP is configured using equation VSS_SET = VOUT = ISET x RSET.
Therefore, RSET = VSS_SET / ISET = 1.8 V / 100 μA = 18 kΩ. ISET is determined by RREF, and is designed to be
100 uA using a precision 12 kΩ resistor. See Figure 4-1 for block diagram. See Figure 7-1 for RSET (R8), and
RREF (R9) connectivity. See SLVSFT8 for more detailed information.
IN
+
-
+
-
+
-
OUTS
OUT
1.2V VREF
REF
SS_SET
ISET = IREF
12kŸ12kŸ
RSET RSET
Input supply
Output load
AVDD
Figure 4-1. Simplified Schematic to Configure Output Voltage
It is also important to note that the TPS7H1111-SP utilizes an adjustable power good PG output threshold
FB_PG. When changing the output voltage, a suitable voltage divider needs to be set on the FB_PG pin in order
for the LDO to assert PG when appropriate threshold achieved. Additionally when PG is asserted, this turns off
internal fast charge circuit that is part of the soft start. Thus, setting appropriate divider is important for proper
startup. See SLVSFT8 for more detailed information.
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5 Test Results
This section provides typical performance waveforms for the TPS7H1111EVM-CVAL with respect to stability,
Noise Spectral Density (NSD), and PSRR. All performance data show is utilizing the the standard configuration
of the EVM. The standard configuration is based on the following conditions: Vin = 2.5 V, Vbias = 5 V, and Vout =
1.8 V
Note
The datasheet for the TPS7H1111-SP LDO contains a wide assortment of additional performance data
under various input and output conditions. See SLVSFT8
5.1 Enable and Soft Start Timing
Figure 5-1 shows the enable and soft start characteristic where VIN is 2.5 V, VBIAS is 5 V, EN is toggled from
ground to ~800 mV while the output drives a ~1.5 A resistive load. The waveforms for EN, VOUT, SS_SET, and
IOUT are shown for reference. CSS of 4.7uF results in a soft start time of approximately 3.7 ms.
Figure 5-1. TPS7H1111 enable and soft start timing
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5.2 PSRR
Figure 5-2 shows the typical PSRR performance of the TPS7H1111EVM-CVAL at various IOUT loads under the
following conditions: VIN = 2.5 V, VBIAS = 5 V, VOUT = 1.8 V, CIN removed.
Frequency (Hz)
PSRR (dB)
0
20
40
60
80
100
120
140
10 100 1k 10k 100k 1M 10M
IOUT = 1.5 A
IOUT = 1 A
IOUT = 500 mA
IOUT = 100 mA
IOUT = 10 mA
IOUT = 1 mA
Figure 5-2. TPS7H1111EVM-CVAL PSRR vs IOUT
Measuring ultra high PSRR on a device can be challenging. To obtain adequate results, the output of the LDO is
fed to a wideband amplifier with approximately 50 dB of gain. Amplifying the output effectively lowers the noise
floor of the measuring instrument. Once results are obtained, the gain curve of the amplifier in dBs is added to
the results across the frequency span.
The injected signal on VIN was -10 dBm into a 50 Ω load. This results in a 200 mV pk-pk signal. Additionally a
small variable amount of injected signal attenuation was used starting at 100 kHz to minimize signal distortion at
higher frequencies. Final injected signal power used was -17 dBm at approximatly 2 MHz.
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5.3 Stability
Figure 5-3 shows the typical Bode gain and phase plot versus frequency for minimum no load, and maximum
load of 1.5 A. Stability tests performed with the TPS7H1111EVM-CVAL operating with the following conditions:
VIN = 2.5 V, VBIAS = 5 V, VOUT = 1.8 V.
Frequency (Hz)
Gain (dB)
Phase (degrees)
-100 -200
-80 -160
-60 -120
-40 -80
-20 -40
0 0
20 40
40 80
60 120
80 160
100 200
1k 10k 100k 1M 10M
Gain 0 A
Phase 0 A
Gain 1.5 A
Phase 1.5 A
Figure 5-3. TPS7H1111EVM-CVAL Gain and Phase vs. Frequency (Bode Plot)
Measuring accurate Bode response with a high bandwidth high gain LDO required using a very small injected
signal. The signal injected used a shape for injected level with an injected signal reference level of -7 dBm. This
reference level was reduced to -27 dBm from 10 kHz to 200 kHz. Additionally, the entire injected signal was
externally attenuated with an inline attenuator by 26 dB. This was required to prevent overdriving the signal into
feedback loop and keeping response within small signal behavior.
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