Texas Instruments DAC8541EVM User manual

DAC8541EVM
August 2002 Data Acquisition
User’s Guide
SLAU085A

IMPORTANT NOTICE
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated

EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated

EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the specified input and output ranges described in
the EVM User’s Guide.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated

Information About Cautions and Warnings
iii
Preface
Read This First
About This Manual
This user’s guide describes the characteristics, operation, and the use of the
DAC8541 evaluation module. It covers all pertinent areas involved to properly
use this EVM board along with the devices that it supports. The physical PCB
layout, schematic diagram and circuit descriptions are included.
How to Use This Manual
This document contains the following chapters:
Chapter 1—EVM Overview
Chapter 2—Physical Description
Chapter 3—EVM Operation
Information About Cautions and Warnings
This book may contain cautions and warnings.
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.

Trademarks
iv
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
Related Documentation From Texas Instruments
To obtain a copy of any of the following TI documents, call the Texas Instru-
ments Literature Response Center at [phone] or the Product Informa-
tion Center (PIC) at [phone]. When ordering, identify this manual by
its title and literature number. Updated documents can also be obtained
through our website at www.ti.com.
Data Sheets: Literature Number:
DAC8541 SLAS353
REF02 SBVS003A
OPA627 PDS-998H
Questions About This or Other Data Converter EVM’s?
If you have questions about this or other Texas Instruments Data Converter
evaluation modules, feel free to e-mail the Data Converter Application Team
at [email protected]. Include in the subject heading the product you
have questions or concerns with.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It gen-
erates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other en-
vironments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
Trademarks
The TI Logo is a trademark of Texas Instruments Incorporated. SPI and QSPI
are trademarks of Motorola, Inc.

Contents
v
Contents
1 EVM Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Supply Voltage 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2 Reference Voltage 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 EVM Basic Functions 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Physical Description 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 PCB Layout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Bill of Materials 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 EVM Operation 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Factory Default Setting 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Host Processor Operation 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.1 Unity Gain Output 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.2 Output Gain of Two 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.3 Capacitive Load Drive 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2.4 Bipolar Operation Using the DAC8541 (Default Mode) 3-4. . . . . . . . . . . . . . . . . . . .
3.3 Jumper Setting Reference 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Schematic Diagram 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents
vi
Figures
1-1. EVM Block Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1. Layer One (Top Silkscreen) 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-2. Layer Two (Bottom Layer) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3. Drill Drawing 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1. Bipolar Operation With the DAC8541 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2. DAC8541 Bipolar Output of Operation 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
2-1 Parts Lists 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Factory Default Jumper Setting 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Unity Gain Output Jumper Settings 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3 Gain of Two Output Jumper Settings 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-4 Capacitive Load Drive Output Jumper Settings 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-5 Bipolar Operation Output Jumper Settings 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-6 Jumper Setting Function 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
EVM Overview
EVM Overview
This chapter gives a general overview of the DAC8541EVM and describes
some of the factors that must be considered in using this module.
Topic Page
1.1 Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 EVM Basic Functions 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1

Features
1-2
1.1 Features
This EVM features the DAC8541 digital-to-analog converter. The
DAC8541EVM is a simple evaluation module designed for a quick and easy
way to evaluate the functionality of the high resolution, single-channel, parallel
input DAC. This EVM features a parallel interface to communicate to any host
processor base system.
1.2 Power Requirements
The following sections describe the power requirements of this EVM.
1.2.1 Supply Voltage
The dc power supply range for the digital section of this EVM is from 1.8 V to
5.5 V connected to the J8-2 or J7-2 terminal and is referenced to ground
through the J8-1 or J7-1 terminal. The dc power requirements for the analog
section of this EVM range from 2.7 V to 5.5 V and connect through J9-6 or J6-4
terminal and are referenced to ground through the J9-5 or J6-2 terminal.
A dc source of ±15 V supply is required to provide the rails for the external
output op-amp provided for output signal conditioning, boost capacitive load
drive, or DAC bipolar mode operation. The 15-V supply connects through the
J6-1 or J9-2 terminal, and the -15 V supply connects through the J6-3 or J9-4
terminal. The ±15-V supply is referenced to ground through the J6-2 or J9-3
terminal.
Caution
To avoid potential damage to the EVM board, make sure that the
correct cables are connected to their respective terminals as
labeled on the EVM board.
1.2.2 Reference Voltage
A 5-V precision reference voltage is provided to supply the VREF(H) through
REF02, U3, via jumper W2 by shorting pins 1 and 2. An adjustable 100 kΩ
potentiometer, R5, is installed in series with 20 kΩ, R4, to allow the user to
adjust the reference voltage to its desired settings. TP2 and TP3 are provided
as well as J4-20, to allow the user to connect an external reference source not
to exceed 5 V dc.
The REF02 precision reference derives its power of ±15 V supply through J6
or J9 terminal. The 15 V connects through the J6-1 or J9-2 terminal, while the
-15 V connects through the J6-3 or J9-4 terminal. They are both referenced
to ground through the J6-2 or J9-1.
The VREF(L) input is normally tied to AGND, unless some minor adjustment to
the offset of the DAC is needed.

EVM Basic Functions
1-3
EVM Overview
Caution
When applying an external voltage reference through TP2 or J4-20,
make sure that it does not exceed 5 V maximum. Otherwise, this
damages U1 part, DUT.
1.3 EVM Basic Functions
The DAC8541EVM is a functional evaluation platform to test certain functional
characteristics of the DAC8541 digital-to-analog converter. Functional
evaluation of the DAC device can be accomplished with the use of any
microprocessor, DSP, or some sort of a waveform generator.
The 20-pin headers, J1, J2, and J3, are provided to channel in the necessary
control signals and data needed to interface a microprocessor/microcontroller,
TI’s DSP starter kit, or waveform generator to the DAC8541 EVM, through a
custom cable.
A specific adapter card is also available for most of TI’s DSP starter kit. Make
sure to specify the DSP that is used to interface with the right adapter card. Call
or email TI for more information regarding the adapter card.
A precision reference voltage provided onboard, can be adjusted to the user’s
preference through the R5 potentiometer. This sets the effective range of the
DAC’s output signal.
The output of the DAC can be monitored through two different access points
which are as follows: a BNC connector (J5, if installed), and a header through
pin 2 of J4. The 6-pin header, W5, provides different levels of the DAC output,
but requires the output op-amp, U2, to be configured correctly first for the
desired waveform characteristic. Shorting pins 1 and 2 of W5 allows the user
to monitor the raw output of the DAC.
A bipolar mode of operation is integrated into the EVM board through the
output op-amp, U2. This option to operate in bipolar mode yields a rail-to-rail
output voltage range of 5 V maximum. This is the default configuration mode
of the EVM when it ships from the factory.
A block diagram of the EVM is shown in Figure 1-1.

EVM Basic Functions
1-4
Figure 1-1.DAC8541EVM Block Diagram
DAC Module
Output
Buffer
Module
W6 Reference
Module
W6
TP2
VREF
Ext. Ref. Input
VCC
DVCC
15 V
-15 V (J6)
(J7)
(J6)
(J7)
(J1)
TP1-VREF Ext. Ref. Input
W1
W5
(J1)
DAC Out
15 V
GND
-15 V
GND
VCC
DVDD
PD0
PD1
LDAC
RST
RSTSEL
BTC/USB
CS
R/W
DB15 (MSB)
DB1 (LSB)

2-1
Physical Description
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM
and lists the components used on the module.
Topic Page
2.1 PCB Layout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Bill of Materials 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2

PCB Layout
2-2
2.1 PCB Layout
The DAC8541EVM is constructed on two-layer printed-circuit board using a
copper-clad FR-4 laminate material. The printed-circuit board has a dimension
of 99,06 mm (3.90 inch)× 104, 14 mm (4.10 inch), and the board thickness is
1,57 mm (0.062 inch). Figures 2-2 through 2-4 show the individual artwork
layers.
Figure 2-1. Layer One (Top Silkscreen)

PCB Layout
2-3
Physical Description
Figure 2-2. Layer Two (Bottom Layer)

PCB Layout
2-4
Figure 2-3. Drill Drawing

Bill of Materials
2-5
Physical Description
2.2 Bill of Materials
Table 2-1.Parts Lists
Item # Qty Designator Manufacturer Part Number Description
1 1 R2 Panasonic ERJ-8GEY0R00V 0 Ω, 1/4 W, 1206 chip resistor
2 2 C8, C9 Panasonic ECUV1H103KBM 0.01 µF, 1206 multilayer ceramic
capacitor
3 4 C4, C5, C6, C7 Panasonic ECJ3VB1C104K 0.01 µF, 1206 multilayer ceramic
capacitor
4 1 C11 Panasonic ECUV1H102JCH 1 nF, 1206 multilayer ceramic
capacitor
5 3 W6, W7, W8 Samtec TSW-102-07-L-S 2 position jumper_0.1 ’’ spacing
6 4 W1, W2, W3, W4 Samtec TSW-103-07-L-S 3 position jumper_0.1 ’’ spacing
7 2 J8, J9 Samtec IPT1-105-01-S-D-VS 5X2X0.1 10-pin 3A isolated power
header
8 3 R6, R7, R8 Panasonic ERJ-8ENF1002V 10 kΩ, 1/4 W 1206 chip resistor
9 1 R3 Bourns 3214W-103E 10 kΩ, BOURNS_32X4W series 5T
Pot
10 4 C1, C2, C3, C10 Kemet C1210C106K8PAC 10 µF, 1206 multilayer ceramic X5R
capacitor
11 1 R4 Panasonic ERJ-8ENF2002V 20 kΩ, 1/4 W 1206 chip resistor
12 3 J2, J3, J4 Samtec TSM-110-01-S-DV-M 10X2X0.1 20-pin 0.025”” sq SMT
terminal strips
13 1 J1 Samtec TSM-116-01-S-DV-M 16X2X0.1 32-pin 0.025”” sq SMT
terminal strips
14 1 R1 Panasonic ERJ-8GEYJ330V 33 Ω, 1/4 W, 1206 chip resistor
15 1 R5 Bourns 3214W-104E 100 kΩ, BOURNS_32X4W series 5T
Pot
16 1 J5 (see Note) AMP (Tyco) 227699-2 PCB mounted BNC—amphenol
17 1 U1 Texas Instruments DAC8541 16-bit, 32-TQFP DAC
18 1 J7 Lumberg KRMZ2 2-pin terminal screw connector
19 1 J6 Lumberg KRMZ4 4-pin terminal screw connector
20 1 U2 Texas Instruments OPA627AU 8-SOP (D) precision op amp
21 1 U3 Texas Instruments REF02AU 5 V, 8-SOP (D) precision voltage
reference
22 3 TP1, TP2, TP3 Cambion 180-7337-02-05 Turret terminal test point
23 1 W5 Samtec TSW-103-07-L-D 3X2X0.1 6-pin IDC header
24 3 P2, P3, P4
(see Note) Samtec SSW-110-22-S-D-VS-P 20 pin 0.025”” sq SMT socket
25 1 P1 (see Note) Samtec SSW-116-22-S-D-VS-P 32 pin 0.025”” sq SMT socket
26 2 P8, P9 (see Note) Samtec IPS1-105-01-S-D-VS 3A isolated power socket
Note: P1, P2, P3, P4, P8, and P9 parts are not shown in the schematic diagram. All the P designated parts are installed in the
bottom side of the PC board opposite the J designated counterpart. Example, J1 is installed on the topside while P1 is
installed in the bottom side opposite of J1.
J5 is an optional output terminal and is not installed.

2-6

3-1
EVM Operation
EVM Operation
This chapter covers the operation of the DAC8541EVM and provides
guidance to the user in evaluating the onboard DAC and interfacing the EVM
to a specific host processor.
For information about its parallel interface and other related topics, refer to the
DAC8541 data sheet, TI literature number SLAS353.
The EVM board is factory-tested and configured to operate in the bipolar
output mode.
Topic Page
3.1 Factory Default Setting 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Host Processor Operation 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Jumper Setting Reference 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3

Factory Default Setting
3-2
3.1 Factory Default Setting
The EVM board is set as default from the factory to the configuration below to
operate in bipolar mode through U2.
Table 3-1.Factory Default Jumper Setting
Reference Jumper Position Function
W1 1-2 VREF(L) tied to AGND
W2 1-2 Adjustable onboard VREF(H) is supplied by U3.
W3 1-2 Negative supply rail of U2 is tied to -15 V.
W4 1-2 Positive supply rail of U2 is tied to 15 V.
W5 3-4 DAC output signal is directed to J5 and J4-2 output terminals.
W6 Close Midscale for bipolar operation is set to VREF(H).
W7 Open U2 is set for 2x gain for bipolar mode of operation.
W8 Close AGND and DGND are tied together.
3.2 Host Processor Operation
The host processor drives the DAC, so the DAC’s proper operation depends
on the successful configuration between the host processor and the EVM
board, and of course a properly written code to run the DAC.
A custom cable can be made specific to the host interface platform. The EVM
allows interface to the host processor through J2 and J3 header connectors
for control signals, and J1 header connector for the data input. The output can
be monitored through the J5 BNC connector (if installed) or J4 header
connector. An interface adapter card is also available for specific DSP starter
kits as mentioned in Chapter 1.
The EVM incorporates four different options for the DAC output through an
external operational amplifier, U2. This requires some jumper setting
configuration, particularly around the op-amp (U2) circuitry, and other required
equipment. Each option is discussed individually.
The raw output of the DAC can be probed through W5 pin 2 so that it can be
compared with the output of U2 if necessary. The output terminals J5 and J4-2
can be used to monitor the raw output of the DAC by shorting pins 1 and 2 of
W5.
3.2.1 Unity Gain Output
The buffered output should closely match the raw output of the DAC with some
slight distortion because of the feedback resistor and capacitor. The user can
tailor the feedback circuit to closely match their desired wave shape by
desoldering R7 and C11 and replacing it with the desired values. You can also
simply get rid of R7 and C11 altogether and just solder a 0 Ωresistor in
replacement of R7, if desired.
Table 3-2 shows the jumper setting relating to the unity gain configuration of
the output buffer.