Texas Instruments ADS8568EVM-PDK User manual

User’s Guide
ADS8568EVM-PDK Evaluation Module
ABSTRACT
This user's guide describes the operation and use of the ADS8568 evaluation module (EVM). The ADS8568 is
an 8-channel, simultaneous sampling, 16-bit successive approximation (SAR) analog-to-digital converter (ADC).
Each input channel on the device can support true bipolar input ranges up to ±12 V. The device includes
a programmable internal buffered voltage reverence. The ADC includes a serial SPI interface and a parallel
interface for data communication. Configuration of the device is achieved through simple static digital input pins
(hardware mode) or through communications to the SPI interface. This user's guide covers circuit description,
schematic diagram, and bill of materials for the ADS8568 circuit board.
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Table of Contents
1 EVM Overview......................................................................................................................................................................... 4
1.1 ADS8568EVM-PDK Kit Features....................................................................................................................................... 4
1.2 ADS8568EVM Board Features ......................................................................................................................................... 4
1.3 Related Documentation From Texas Instruments.............................................................................................................. 4
2 EVM Analog Interface.............................................................................................................................................................5
2.1 ADC Supply, Input, Voltage Reference, and Digital Connections...................................................................................... 5
2.2 ADC Amplifier Drive .......................................................................................................................................................... 6
3 Digital Interface.......................................................................................................................................................................7
3.1 Parallel Interface................................................................................................................................................................ 7
3.2 Serial Interface (SPI)..........................................................................................................................................................7
3.3 Connections to PHI connector........................................................................................................................................... 7
3.4 Static Signals for ADS8568................................................................................................................................................8
3.5 I2C Bus for Onboard EEPROM..........................................................................................................................................8
4 Power Supplies....................................................................................................................................................................... 9
4.1 Low Dropout Regulator...................................................................................................................................................... 9
4.2 Power Connections and LED Indicators............................................................................................................................ 9
5 Installing ADS8568EVM Software....................................................................................................................................... 10
6 ADS8568EVM Operation...................................................................................................................................................... 13
6.1 Connecting the Hardware and Running the GUI..............................................................................................................13
6.2 Jumper Settings for ADS8568EVM..................................................................................................................................14
6.3 EVM GUI Global Settings for ADC Control...................................................................................................................... 15
6.4 Time Domain Display....................................................................................................................................................... 16
6.5 Frequency Domain Display.............................................................................................................................................. 17
6.6 Histogram Display............................................................................................................................................................ 18
7 Modifying Hardware and Using Software to Evaluate ADS8548 and ADS8528.............................................................. 19
A Bill of Materials, Layout, and Schematic............................................................................................................................20
A.1 Bill of Materials................................................................................................................................................................ 20
A.2 Layout.............................................................................................................................................................................. 23
A.3 Schematic........................................................................................................................................................................ 26
B Revision History...................................................................................................................................................................29
List of Figures
Figure 1-1. System Connection for Evaluation............................................................................................................................ 4
Figure 2-1. ADC Signal and Supply Connection..........................................................................................................................5
Figure 2-2. Amplifier Drive Circuit................................................................................................................................................6
Figure 3-1. PHI to ADS8568EVM connector............................................................................................................................... 7
Figure 3-2. Static Digital Input Configuration............................................................................................................................... 8
Figure 3-3. EEPROM for EVM ID................................................................................................................................................ 8
Figure 4-1. Low Dropout Regulator for AVDD (5v Supply).......................................................................................................... 9
Figure 4-2. Supply Connections and Led Monitors......................................................................................................................9
Figure 5-1. ADS8568 Software Installation Prompts................................................................................................................. 10
Figure 5-2. Device Driver Installation Wizard Prompts.............................................................................................................. 11
Figure 5-3. LabVIEW Run-Time Engine Installation.................................................................................................................. 11
Figure 5-4. ADS8568EVM GUI Folder Post-Installation............................................................................................................ 12
Figure 6-1. ADS8568EVM Hardware Setup and LED Indicators...............................................................................................13
Figure 6-2. Launch the EVM GUI Software............................................................................................................................... 14
Figure 6-3. Global Settings for ADC Control..............................................................................................................................15
Figure 6-4. Time Domain Display.............................................................................................................................................. 16
Figure 6-5. Frequency Domain Display..................................................................................................................................... 17
Figure 6-6. Histogram Display................................................................................................................................................... 18
Figure 7-1. Enable EEPROM for Writing................................................................................................................................... 19
Figure 7-2. Configure EEPROM and Software for New Device.................................................................................................19
Figure A-1. Top and Bottom Layer ADS8568EVM.....................................................................................................................23
Figure A-2. Inner Power Layer...................................................................................................................................................24
Figure A-3. Inner Ground Layer.................................................................................................................................................25
Figure A-4. ADC schematic....................................................................................................................................................... 26
Figure A-5. ADC Drive Schematic............................................................................................................................................. 27
Figure A-6. Power and PHI Connections schmatic....................................................................................................................28
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List of Tables
Table 1-1. Related Documents.................................................................................................................................................... 4
Table 6-1. Jumper Settings........................................................................................................................................................ 14
Trademarks
All trademarks are the property of their respective owners.
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1 EVM Overview
This document describes how to connect the EVM to your computer and test equipment to evaluate device
performance and understand device features. The document also describes how to install and use the
associated evaluation module software.
1.1 ADS8568EVM-PDK Kit Features
The ADS8568 evaluation module kit includes the following features:
• Hardware and software required for diagnostic testing as well as accurate performance evaluation of the
ADS8568 ADC
• Digital and analog interface power with USB power. External power required for high voltage ±15 V supply.
• Easy-to-use evaluation software for 64-bit Microsoft Windows™7, Windows 8, and Windows 10 operating
systems.
• PHI controller translates USB (2.0) or higher to parallel, or serial digital communications.
Signal
Source
Included in kit
ADS8568EVM
PHI Board
x
x
x
x
x
ADS8568
GUI
Signal
Source
Signal
Source
A0 A0
B0
B1
C1
D1 D0
C0
+/-15V
lab supply
J9
Figure 1-1. System Connection for Evaluation
1.2 ADS8568EVM Board Features
• Eight input channels connected to external single ended signals source applied to SMA connectors or header
• Serial and parallel interface connects to the PHI controller via 60 pin connector (J10)
• High voltage power supplies (HVDD, and HVSS) are not included. Connect common lab supplies via terminal
strip J9.
• Low voltage supplies (AVDD, and DVDD) generated using USB power from the PHI controller.
• Integrated or external voltage reference options available.
1.3 Related Documentation From Texas Instruments
Related Documents lists devices that are used in this EVM and may be useful in related designs.
Table 1-1. Related Documents
Device Literature Number
ADS8568 SBAS543
OPA2211 SBOS377
TPS7A4700 SLVS493
REF6025 SBOS708
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2 EVM Analog Interface
2.1 ADC Supply, Input, Voltage Reference, and Digital Connections
Figure 2-1 illustrates the decoupling on AVDD, DVDD, HVDD, HVSS, and the reference IO. The capacitors
for decoupling match the recommendations in the ADS8568 data sheet. The layout (see Figure 2-1) uses the
shortest possible connections to the decoupling capacitors and connections the ground end to the GND plane
using vias. The ADS8568 can use an external or internal voltage reference. This can be selected by changing
the position of JP9 to “INT” for internal, or “EXT” for external. Figure 2-1 also illustrates the analog input signal
and digital signal connections.
A0
A1
B0
B1
C0
C1
D0
D1
GND
AVDD
GND
DB0_DCIND
DB1_DCINC
DB2_DCINB
DB3_DCINA
DB4
DB5_SELCD
DB6_SELB
DB7
DB8_DCEN
DB9_SDI
DB10_SCLK
DB11_REFBUFEN
DB12_SDOA
DB13_SDOB
DB14_SDOC
DB15_SDOD
GND
GND
GND
GND
BUSY
RANGE_XCLK
~HW_SW
REFEN_~WR
~STBY
~CS_~FS
~RD
ASLEEP
~PAR_SER
CONVSTA
CONVSTB
CONVSTC
CONVSTD
DVDD
HVDD
HVSS
HVSS 1
CH_D1
2
REFDN
3
AVDD
4
AGND 5
REFDP
6
CH_D0
7
PAR/SER 8
STBY 9
RESET 10
REFEN/WR 11
RD 12
CS/FS 13
AVDD
14
AGND 15
DB15/SDO_D16
DB14/SDO_C17
DB13/SDO_B18
DB12/SDO_A19
DB11/REFBUFEN 20
DB10/SCLK 21
DB9/SDI 22
DB8/DCEN 23
DGND 24
DVDD
25
DB7 26
DB6/SEL_B 27
DB5/SEL_CD 28
DB4 29
DB3/DCIN_A30
DB2/DCIN_B31
DB1/DCIN_C32
DB0/DCIN_D33
RANGE/XCLK 34
BUSY/INT 35
ASLEEP 36
CONVST_A
37
CONVST_B
38
CONVST_C
39
CONVST_D
40
HW/SW 41
CH_A0
42
REFAP
43
AGND 44
AVDD
45
REFBN
53
CH_A1
47
HVDD
48
CH_B0
49
REFBP
50
AGND 51
AVDD
52
REFAN
46
CH_B1
54
REFN
55
REFIO
56
AVDD
57
AGND 58
CH_C1
59
REFCN
60
AVDD
61
AGND 62
REFCP
63
CH_C0
64
ADS8568SPM
U5
GND
GND
GND
GND
GND
GND
VIN
1
SS
3
FILT
4
EN
2
OUT_S 5
OUT_F 6
GND_F 7
GND_S 8
REF6025IDGKR
U6
AVDD
GND
GND
GND
GND
120k
R108
GND
10uF
C43
10uF
C45
10uF
C46
10uF
C47
10uF
C48
10uF
C53
10uF
C54
0.47uF
C49
22uF
C55
0.22
R109
RET_RD
RET_SCLK
10uF
C51
49.9
R71
49.9
R70
49.9
R73
49.9
R74
49.9
R75
49.9
R79
49.9
R76
49.9
R80
49.9
R81
49.9
R82
49.9
R83
49.9
R84
49.9
R85
49.9
R87
49.9
R88
49.9
R89
49.9
R65
49.9
R92
49.9
R93
49.9
R94
49.9
R96
49.9
R68
49.9
R66
49.9
R67
49.9
R95
49.9
R97
49.9
R98
49.9
R100
49.9
R99
49.9
R101
~CS_~FS
~RD
ASLEEP
~PAR_SER
RANGE_XCLK
~HW_SW
REFEN_~WR
~STBY
RESET
100nF
C37
100nF
C38
100nF
C39
100nF
C40
100nF
C41
100nF
50V
C42
100nF
50V
C44
100nF
C50
100nF
C52
0
R69
0
R86
0
R107
1
2
3
JP9
TP4
Vref
RESET
1.00
R104
1.00
R72
EXT INT
Figure 2-1. ADC Signal and Supply Connection
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2.2 ADC Amplifier Drive
Figure 2-2 shows the op amp configuration for each ADC drive input. The default configuration is and inverting
configuration. This can be converted to a non-inverting configuration but uninstalling R6, and R14, and installing
R11. Also, R11 and C11 can be used to create a low pass filter. The jumper JP1 can be used to completely
bypass the amplifier. This diagram only shows one channel but this circuit is repeated 8 times. For other
channels, see Appendix A.
GND
GND
GND
1
2
3
4 8 9
OPA2211AI DDA
U1A
39pFC4
1.00kR4
1.00kR6
0R3 DNP
0R11
DNP
10.0R8
2200pF
C12
1
2
3
JP1
GND
100nF
C11 DNP
1
2
3 4 5
J1
A0I A0
35V
1uF
C5
GND
HVDD
HVDD
HVSS
HVSS
1 2 3
J9
HVDDHVSS
GND
HVSS
HVDD
A0
GND
Bypass w/Amp
100nF
50V
C1
100nF
50V
C7
0R12
0
R14
Figure 2-2. Amplifier Drive Circuit
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3 Digital Interface
As noted in Section 1, the EVM interfaces with the PHI and communicates with the computer over the USB.
There are two devices on the EVM with which the PHI communicates: the ADS8568 ADC (over SPI) and the
EEPROM (over I2C). The EEPROM comes pre-programmed with the information required to configure and
initialize the ADS8568 platform. When the hardware is initialized, the EEPROM is no longer used.
3.1 Parallel Interface
The parallel interface signals are generated on the PHI controler and connected through J10. Each of these
signals has a 47-Ω resistor between the device and the controler to slow down the signal edges in order to
minimize signal overshoot. The digital signals can be monatored on J11 test header.
3.2 Serial Interface (SPI)
The ADS8568 ADC uses SPI serial communication in mode 2 (CPOL=1 and CPHA=0). Because the serial clock
(SCLK) frequency can be as fast as 45 MHz, the ADS8568EVM offers 47-Ω resistors between the controler
and device to aid with signal integrity. Typically, in high-speed SPI communication, fast signal edges can cause
overshoot; these 47-Ω resistors slow down the signal edges in order to minimize signal overshoot.
3.3 Connections to PHI connector
Connector J10 is used to connect the PHI digital controller PCB to the ADS8568EVM. This connector has all the
digital signals as well as the 5.5V regulated supply and the DVDD supply. The power for the two supplies is from
the USB connection. The 5.5V supply is used to generate the AVDD supply. This connector also provides I2C
signals that are used on the EEPROM identification circuit.
GND GND
1 1
3 3
5 5
7 7
9 9
11 11
13 13
15 15
17 17
19 19
21 21
23 23
25 25
27 27
29 29
31 31
33 33
35 35
37 37
39 39
41 41
43 43
45 45
47 47
49 49
51 51
53 53
55 55
57 57
59 59
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
32
32
34
34
36
36
38
38
40
40
42
42
44
44
46
46
48
48
50
50
52
52
54
54
56
56
58
58
60
60
GND
MP1
GND
MP2 GND MP3
GND MP4
J10
QTH-030-01-L-D-A
CONVSTA
CONVSTB
CONVSTC
CONVSTD
~PAR_SER
~STBY
REFEN_~WR
BUSY
ASLEEP
~HW_SW
5.11R113
EVM_ID_SDA
EVM_ID_SCL
ID_PWR
ID_PWR
GND
GND
DB0_DCINDDB1_DCINC
DB2_DCINBDB3_DCINA
DB4DB5_SELCD
DB6_SELBDB7
DB8_DCENDB9_SDI
DB10_SCLKDB11_REFBUFEN
DB12_SDOADB13_SDOB
DB14_SDOCDB15_SDOD
~RD~CS_~FS
DVDD
TP2
5.5V
TP1
DVDD
GND
5V
D5
DB0/DCIN_DDB1/DCIN_C
DB2/DCIN_BDB3/DCIN_A
DB4DB5/SEL_CD
DB6/SEL_BDB7
DB8/DCENDB9/SDI
DB10/SCLKDB11/REFBUFEN
DB12/SDO_ADB13/SDO_B
DB14/SDO_CDB15/SDO_D
RANGE/XCLK
~RD~CS/~FS
BUSY
~HW/SW
ASLEEP
REFEN/~WR RESET
~STBY ~PAR/SER
CONVST_A
CONVST_B CONVST_C
CONVST_D
RANGE_XCLK BUSY
~HW_SW
ASLEEP
~STBY
10uF
C61
REFEN_~WR
~PAR_SER
CONVSTA
CONVSTB CONVSTC
CONVSTD
DB0_DCIND
DB1_DCINC
DB2_DCINB
DB3_DCINA
DB4
DB5_SELCD
DB6_SELB
DB7
DB8_DCEN
DB9_SDI
DB10_SCLK
DB11_REFBUFEN
DB12_SDOA
DB13_SDOB
DB14_SDOC
DB15_SDOD
~CS_~FS
~RD
RANGE_XCLK
RET_RD
RET_SCLK
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15
17
19
21
23
25
27
29
31
16
18
20
22
24
26
28
30
32
J11
TSW-116-07-G-D
GND GND
EVM_ID_WP
RESET1
RESET1
Figure 3-1. PHI to ADS8568EVM connector
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3.4 Static Signals for ADS8568
The ADS8568 has several static digital configuration pins. The logic state of the pin will determine the operation
of the device. For example, the PAR/SER digital pin will determine if the communication is in parallel or serial
mode. These pins are automatically controlled by the PHI digital controller when the GUI is in "hardware mode".
The logic level on these pins can be monitored using test points on J11 or as shown in Figure 3-2. Some
of these digital control pins also have resistors that can be used to configure the logic levels when the PHI
controller is not used. Figure 3-2 shows the static logic configuration. To set a pin to logic high the resistor
connected to DVDD is installed. To set an input to logic low the resistor connected to GND needs to be installed.
It is important to understand that the configuration of these resistors does not matter when the PHI is used as
it will drive the logic level to whatever the GUI setting is. These digital input configuration resistors only matter
when the EVM is disconnect from the PHI and used with a different digital controller.
Figure 3-2 also shows the operation of the reset control line. This reset can be initiated by the PHI controller or
by the push button switch. Note that RESET is an active high signal so the two reset signals are applied to an
OR function so that the device will be reset if either the push button is pressed or the PHI drives the signal active
high.
DVDD
GND
DVDD DVDD
DVDD
DVDD
DVDD
DVDD
GND
GND GND
GND
GND
GND
10.0k
R59
ASLEEP
DNP
10.0k
R64
~STBY
DNP
1000pF
C56
1 2
S1
GND
ASLEEP ~STBY
~HW_SW ~PAR_SER
RANGE_XCLK REFEN_~WR
HIGHLOW
10.0k
R61
NORM
10.0k
R62
NORM
10.0k
R77
SW
DNP 10.0k
R78
SER
DNP
10.0k
R90
~HW
10.0k
R91
~PAR
10.0k
R102
2Vref
DNP 10.0k
R103
INT
10.0k
R105
4Vref
10.0k
R106
EXT
DNP
10.0k
R110
10.0k
R111
TP10
REFEN_~WR
TP9
~PAR_SER
TP8
~HW_SW
TP11
RANGE_XCLK
4
1
2
SN74AHC1G32DRLR
U9A
RESET
RESET1
TP13
~STBY
TP12
ASLEEP
Figure 3-2. Static Digital Input Configuration
3.5 I2C Bus for Onboard EEPROM
The circuit shown in Figure 3-3 is used with our EVM controler (PHI), for EVM identification. This circuit is not
required by the ADS8568 for operation. The switch (S2) is a write protect and does not need to be changed for
EVM operation.
GND
GND
ID_PWR
EVM_ID_SCL
EVM_ID_SDA
GND
GND
A0
1
A1
2
A2
3
VSS
4 SDA 5
SCL 6
WP 7
VCC 8
U7
BR24G32FVT-3AGE2
2
1
3
S2
EVM_ID_WP
100nFC59
100nF
C60
10.0k
R112
Figure 3-3. EEPROM for EVM ID
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4 Power Supplies
The ADS8568EVM has four power supplies: AVDD (5 V), DVDD (3.3 V), HVDD (15 V), and HVSS (-15 V).
The two high voltage power supplies require an external ±15 V supply and are connected on a screw terminal
strip (J9). The lower voltage supplies (AVDD and DVDD), are generated with the USB power and low dropout
regulators (LDO).
4.1 Low Dropout Regulator
U8 is a low dropout regulator (LDO) used to convert the 5.5 V regulated supply from the PHI to a low noise 5 V
supply. The input and output of this LDO can be monitored on TP2 and TP3.
AVDD
GND
GND
OUT 1
NC 2
SENSE 3
6P4V2
4
6P4V1
5
3P2V
6
GND 7
1P6V
8
0P8V
9
0P4V
10
0P2V
11
0P1V
12
EN
13
NR 14
IN
15
IN
16
NC 17
NC 18
NC 19
OUT 20
PAD 21
TPS7A4700RGWR
U8
1uF
C64
GND
TP3
AVDD
GND
100k
R114
GND
10uF
C63
22uF
C62
0
R115
0
R116
HVDD
Figure 4-1. Low Dropout Regulator for AVDD (5v Supply)
4.2 Power Connections and LED Indicators
The screw terminal block J9 is used to connect the external high voltage supplies. These supplies are not
provided in the evaluation module kit and it is expected that you will use low noise lab supply to provide this
power (for example, Keysight E3632a). The high voltage supplies have transient voltage suppressor diodes to
help protect the ADC from transients. These supplies are typically connected to +/-15 V. For details on operation,
see the ADS8568 data sheet. Figure 4-2 also shows how each supply has an LED monitor for quick verification
that power is applied.
Green
12
D6
6.65k
R117
GND
AVDD
Green
12
D7
6.65k
R118
GND
DVDD
5.11R113
GND
DVDD
TP1
GND
5V
D5
DVDD
10uF
C61
1 2 3
J9
HVDDHVSS
GND
HVSS
HVDD
GND
15V
D1
Green
12
D3
GND
Green
1 2
D4
GND
HVDD HVSS
15V
D2
HVDD HVSS
GND GND
20.0k
R43
20.0k
R44
Figure 4-2. Supply Connections and Led Monitors
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5 Installing ADS8568EVM Software
Download the latest version of the EVM GUI installer from the Tools and Software folder of the ADS8568EVM
and run the GUI installer to install the EVM GUI software on your computer.
CAUTION
Manually disable any anti-virus software running on the computer before downloading the EVM GUI
installer onto the local hard disk. Depending on the anti-virus settings, an error message may appear
or the installer. The exe file can be deleted.
Accept the license agreements and follow the on-screen instructions shown in Figure 5-1 to complete the
installation.
Figure 5-1. ADS8568 Software Installation Prompts
As a part of the ADS8568EVM GUI installation, a prompt with a Device Driver Installation (as shown in Figure
5-2) appears on the screen. Click Next to proceed.
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Figure 5-2. Device Driver Installation Wizard Prompts
The ADS8568EVM requires the LabVIEW™ run-time engine and may prompt for the installation of this software,
as shown in Figure 5-3, if not already installed.
Figure 5-3. LabVIEW Run-Time Engine Installation
Verify that C:\Program Files (x86)\Texas Instruments\ADS8568EVM is as shown in Figure 5-4 after these
installations.
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Figure 5-4. ADS8568EVM GUI Folder Post-Installation
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6 ADS8568EVM Operation
The following instructions are a step-by-step guide to connecting the ADS8568EVM to the computer and
evaluating the performance of the ADS8568:
6.1 Connecting the Hardware and Running the GUI
1. Set the jumpers according to Table 6-1.
2. Physically connect P2 of the PHI to J10 of the ADS8568EVM. Install the screws to assure a robust
connection.
3. Connect USB on PHI to the computer first.
a. LED D5 on the PHI lights up, indicating that the PHI is powered up.
b. LEDs D1 and D2 on the PHI start blinking to indicate that the PHI is booted up and communicating with
the PC; Figure 6-1 shows the resulting LED indicators.
4. Start the software GUI as shown in Figure 6-2. You will notice that the LEDs blink slowly as the FPGA
firmware is loaded on the PHI. This will take a few seconds then the AVDD and DVDD power supplies will
turn on.
5. Connect the high voltage power supplies (HVDD = +15 V, HVSS = -15 V, and GND).
6. Connect the signal generator. The default input range is ±10 V (or 10Vpk). A common input signal applied is
a sinusoidal 1kHz, 9.9Vpk signal with a 0 V offset. Note that this signal is adjusted just below the full scale
range to avoid clipping.
3. Connect USB power before
applying signal source.
4. Start the software GUI.
1. Set jumpers according to
your requirements. Review
Table 6-1 for details.
6. Apply input signals.
Input range = ±10V in the
default configuration.
Connect the eight input
channels as desired.
D5
D1
D2
2. Connect PHI to ADS8568EVM
and install screws.
ADS8568EVM PHI
HVSS
GND
HVDD
HVSS
-15V GND HVDD
+15V
5. Apply high voltage power supplies using
external DC lab supply (not provided).
HVDD = +15V, HVSS = -15V, and GND = 0V.
Figure 6-1. ADS8568EVM Hardware Setup and LED Indicators
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Figure 6-2 shows how the software can be started on the start menu or using a desktop icon.
Select EVM GUI
from start menu,
or associated
shortcut
Figure 6-2. Launch the EVM GUI Software
6.2 Jumper Settings for ADS8568EVM
The amplifiers and reference can be configured with jumpers. The amplifier jumpers (JP1-JP8) determine if the
amplifier is used or if an external signal is directly connected to the ADC input. JP9 is used to select either the
internal reference option or external reference option. Take care to make sure that the GUI configuration for the
device reference matches the setting of JP9. The GUI software starts up in the "internal" reference mode, so
make sure the JP9 is in the "INT" position.
Table 6-1. Jumper Settings
Jumper Setting Default Function
JP1 to JP8 wAmp / Bypass wAmp These eight jumpers determine if the amplifier is used to buffer the inputs signals or if it
is bypassed. Choosing wAmp will connect the amplifier between each SMA connector
(J1 to J8) and the ADC input. The default amplifier configuration is inverting (Gain =
-1V/V). The amplifier gain configuration can be adjusted by soldering and de-soldering
different resistors. Choosing the Bypass configuration will connect the SMA connectors
directly to the ADC input.
JP9 EXT / INT INT This jumper will select internal vs external mode on the voltage reference. Using
internal mode will disconnect the external reference. Using external mode will connect
the external REF6025 2.5 V reference to the ADC reference input. Take care to make
sure that the GUI settings for the voltage reference match this jumpers setting.
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6.3 EVM GUI Global Settings for ADC Control
Figure 6-3 shows that the EVM Global controls are located on the right hand side of the GUI. These controls
choose the page display, SPI Mode, SCLK frequency, and sampling frequency.
Pages selects the
analysis display.
Toggles Reset pin on
ADC.
This device can use different input
voltage ranges, serial or parallel
communications, hardware or
software mode, and internal or
external reference. Refer to the
data sheet for details on these
modes.
The maximum clock is 45MHz and
the maximum sampling rate is
494.5kHz for this device.
Figure 6-3. Global Settings for ADC Control
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6.4 Time Domain Display
The time domain display tool allows visualization of the ADC response to a given input signal. This tool is useful
for both studying the behavior and debugging any gross problems with the ADC or drive circuits.
The user can trigger a capture of the data of the selected number of samples from the ADS8568EVM, as per the
current interface mode settings indicated in Figure 6-4 by using the Capture button. The sample indices are on
the x-axis and there are two y-axes showing the corresponding output codes as well as the equivalent analog
voltages based on the specified reference voltage. Switching pages to any of the Analysis tools described in the
subsequent sections causes calculations to be performed on the same set of data.
Figure 6-4. Time Domain Display
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6.5 Frequency Domain Display
The spectral analysis tool, shown in Figure 6-5, is intended to evaluate the dynamic performance (SNR, THD,
SFDR, SINAD, and ENOB) of the ADS8568 ADC through single-tone sinusoidal signal FFT analysis using the 7-
term Blackman-Harris window setting. The FFT tool includes windowing options that are required to mitigate the
effects of non-coherent sampling (this discussion is beyond the scope of this document). The 7-Term Blackman
Harris window is the default option and has sufficient dynamic range to resolve the frequency components of up
to a 24-bit ADC. The None option corresponds to not using a window (or using a rectangular window) and is not
recommended.
Figure 6-5. Frequency Domain Display
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6.6 Histogram Display
Noise degrades ADC resolution and the histogram tool can be used to estimate effective resolution, which
is an indicator of the number of bits of ADC resolution losses resulting from noise generated by the various
sources connected to the ADC when measuring a DC signal. The cumulative effect of noise coupling to the
ADC output from sources such as the input drive circuits, the reference drive circuit, the ADC power supply,
and the ADC itself is reflected in the standard deviation of the ADC output code histogram that is obtained by
performing multiple conversions of a DC input applied to a given channel. As shown in Figure 6-6, the histogram
corresponding to a DC input is displayed on clicking the Capture button.
Figure 6-6. Histogram Display
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7 Modifying Hardware and Using Software to Evaluate ADS8548 and ADS8528
The ADS8568 is part of a family of related devices. This EVM hardware and software will support the entire
family as all the devices are pin-for-pin compatable. The ADS8548 is the 14 bit version of the device, and the
ADS8528 is the 12 bit version of the device. The procedure below shows how to modify the hardware and
software to evaluate the other devices in this family.
1. Desolder the ADS8568 device an replace it with the device you want to evaluate.
2. Enable the EEPROM for writing. This is done by changing switch S2 to the top position using tweezers. For
details, see Figure 7-1.
3. Connect EVM and start GUI as described in Connecting the Hardware and Running the GUI.
4. Use the "Tools" menu to "Load EEPROM" according to the device that is currently installed. When this
procedure is successfully completed, you will see the status bar at the top of the software update according
to the device installed on the hardware. For details, see Figure 7-2.
Use tweezers to change position of
Switch S2 to up as shown to allow
the EEPROM write operation.
Figure 7-1. Enable EEPROM for Writing
1. KvšZ^d}}o•_uvµ
•oš^>}WZKD_
2. hvŒ^^µ‰‰}ŒšÀ]•_
select the desired device and
‰Œ••^>}WZKD_
3. (šŒ‰Œ••]vP^o}
WZKD_]šÁ]oošl(Á
minutes to load the EEPROM.
4. The top of status bar on the
software will indicate what the EVM
Connected has been updated to.
Figure 7-2. Configure EEPROM and Software for New Device
www.ti.com Modifying Hardware and Using Software to Evaluate ADS8548 and ADS8528
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A Bill of Materials, Layout, and Schematic
Schematics for the ADS8568EVM are appended to this user's guide. The bill of materials is provided in Bill of
Materials. Layout shows the PCB layouts for the ADS8568EVM.
A.1 Bill of Materials
Designator Qty Value Description Part Number Manufacturer
!PCB1 1 Printed Circuit Board DC121 Any
C1, C2, C7, C8, C13, C14,
C17, C18, C37, C38, C39,
C40, C41, C42, C44, C50,
C52, C59, C60, C65
20 0.1 μF CAP, CERM, 0.1 μF, 50 V, ±
10%, X7R, 0603
C0603C104K5RACTU Kemet
C3, C4, C19, C20, C25,
C26, C31, C32
8 39 pF CAP, CERM, 39 pF, 50 V, ± 5%,
C0G/NP0, 0603
CGA3E2C0G1H390J080AA TDK Corporation
C5, C6, C15, C16, C64 5 1 μF CAP, CERM, 1 μF, 35 V, ± 10%,
X5R, 0603
GMK107BJ105KA-T Taiyo Yuden
C10, C12, C22, C24, C28,
C30, C34, C36
82200 pF CAP, CERM, 2200 pF, 50 V, ±
5%, C0G/NP0, 0603
GRM1885C1H222JA01D MuRata
C43, C45, C46, C47, C48,
C51, C53, C54, C61, C63
10 10uF CAP, CERM, 10 μF, 35 V, ±
10%, X5R, 0805
C2012X5R1V106K125AC TDK
C49 1 0.47 μF CAP, CERM, 0.47 μF, 50 V, ±
10%, X5R, 0603
C1608X5R1H474K080AB TDK
C55, C62 2 22 μF CAP, CERM, 22 uF, 35 V, +/-
20%, X5R, 0805
C2012X5R1V226M125AC TDK
C56 1 1000 pF CAP, CERM, 1000 pF, 50 V, ±
10%, C0G/NP0, 0603
06035A102KAT2A AVX
D1, D2 2 15 V Diode, TVS, Uni, 15 V, 24.4 Vc,
SMB
SMBJ15A-13-F Diodes Inc.
D3, D4, D6, D7 4 Green LED, Green, SMD APT2012LZGCK Kingbright
D5 1 5 V Diode, TVS, Uni, 5 V, 9.2 Vc,
400 W, 43.5 A, SMA
SMAJ5.0A Littelfuse
H1, H2, H3, H4 4 Hex Standoff Threaded #4-40
Aluminum 0.250" (6.35mm) 1/4"
1891 Keystone
H5, H6, H7, H8 4 MACHINE SCREW PAN
PHILLIPS 4-40
PMSSS 440 0025 PH B&F Fastener
Supply
H9, H10 2 ROUND STANDOFF M3 STEEL
5MM
9774050360R Wurth Elektronik
H11, H12 2 Machine Screw Pan PHILLIPS
M3
RM3X4MM 2701 APM HEXSEAL
H13 1 Cable, USB-A to micro USB-B,
1 m - Kitting item
102-1092-BL-00100 CnC Tech
H14 1 PHI-EVM Controller Kitting item
Edge# 6591636
PA007 Texas Instruments
J1, J2, J3, J4, J5, J6, J7,
J8
8 Connector, SMA, TH 142-0701-201 Cinch Connectivity
J9 1 Terminal Block, 3.5 mm, 3x1,
Tin, TH
0393570003 Molex
J10 1 Header(Shrouded), 19.7 mil,
30x2, Gold, SMT
QTH-030-01-L-D-A Samtec
J11 1 Header, 100 mil, 16x2, Gold, TH TSW-116-07-G-D Samtec
JP1, JP2, JP3, JP4, JP5,
JP6, JP7, JP8, JP9
9 Header, 100 mil, 3x1, Gold, TH TSW-103-07-G-S Samtec
LBL1 1 Thermal Transfer Printable
Labels, 0.650" W x 0.200" H -
10,000 per roll
THT-14-423-10 Brady
Bill of Materials, Layout, and Schematic www.ti.com
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