Texas Instruments ADS5560EVM User manual

User's GuideSLAU260 – December 2008
ADS5560/62EVM
Contents1 Overview ...................................................................................................................... 21.1 ADS556xEVM Quick-Start Procedure ........................................................................... 22 Circuit Description ........................................................................................................... 22.1 Schematic Diagram ................................................................................................. 22.2 EVM Circuit Function ............................................................................................... 23 Serial Interface Control ...................................................................................................... 43.1 Installing the AD SPI Control Software .......................................................................... 43.2 Using the ADC SPI Interface Software .......................................................................... 53.3 TSW1200 Capture Board ......................................................................................... 64 ADC Evaluation .............................................................................................................. 74.1 Hardware Selection ................................................................................................. 74.2 Coherent Input Frequency Selection ............................................................................. 85 Physical Description ......................................................................................................... 85.1 PCB Layout .......................................................................................................... 85.2 Bill of Materials .................................................................................................... 115.3 EVM Schematics .................................................................................................. 14
List of Figures
1 TI ADC SPC Interface Screen ............................................................................................. 52 TSW1200 GUI Introduction ................................................................................................. 73 Top Silkscreen ............................................................................................................... 94 Ground Plane ................................................................................................................. 95 Power Plane ................................................................................................................ 106 Bottom Silkscreen .......................................................................................................... 107 TSW12XXEVM – Connector .............................................................................................. 13
List of Tables
1 EVM Power Supply Connections .......................................................................................... 32 Analog Input Selection Through Surface-Mount Jumpers .............................................................. 33 Jumper Setting for Control Interface ..................................................................................... 44 Jumper Setting for Control Pins SEN, DFS, and MODE at Parallel Interface ...................................... 45 Jumper Setting for Control Pins SDATA and SCLK at Parallel Interface ............................................ 46 Frequently Used Registers ................................................................................................. 67 ADS61B49EVM Bill of Materials ......................................................................................... 11
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1 Overview
1.1 ADS556xEVM Quick-Start Procedure
2 Circuit Description
2.1 Schematic Diagram
2.2 EVM Circuit Function
2.2.1 EVM Power Connections
Overview www.ti.com
This user’s guide gives a general overview of the ADS556xEVM evaluation module (EVM) and provides ageneral description of the features and functions to be considered while using this module. This manual isapplicable to the ADS556x. The ADS556xEVM provides a platform for evaluating the 16-bit, 40-/80-MSPS,analog-to-digital converter (ADC) parallel and DDR data output.
Use this document in combination with the respective ADC data sheet.
Using the quick-start procedure, many users can begin evaluating the ADC in a short time. The quick-startprocedure uses the default conditions of the EVM as shipped from the factory.1. Five power supply connectors (banana jack), J11 (3.3 V), J13 (3.3 V), J16 (Vss– for amplifier), J20 (5V), and J12 (GND) on the EVM are used to connect the EVM with offboard dc power supply. Itprovides supply voltage for all devices on the board. A few options for using supply pairs are shown inTable 1 . The default option uses J20 (+5 V) and J12 (GND) to connect with the power supply because3.3-V and 3.3-V supply voltages are generated on the board for the LDO solution (from 5-V supplyvoltage).
2. Connector J9 (SMA) is connected to the path of the ADC clock input. It is used to connected ADCclock input with the offboard clock source. A sine-wave clock source is recommended for the defaultEVM setting.3. Connectors J6 (SMA) and J8 (SMA) are used to connect the ADC with the offboard analog signalsource. At default, J8 is not installed as it is connected to GND. A single-ended analog signal, forexample a sine wave, is input to J6. Then, it is converted into a differential signal through transformersT1 and T2 or through T5 and THS4509 to the ADC’s differential analog input pins. A few configurationsare possible for the analog input path; the default one is the transformer-coupling configuration throughT1 and T2.4. By default the DDR LVDS digital output is brought to connector J10 (Samtec).5. If using TSW1200 capture board from TI, connect TSW1200 to J10 of the ADS556x EVM and followthe instructions found in Section 4 .
The schematic diagram for the EVM is in Section 5.3 .
The following sections describe the functions of individual circuits. See the relevant data sheet for deviceoperating characteristics.
Five power supply connectors (banana jack) J11 (3.3 V), J13 (3.3 V), J16 (Vss– for amplifier), J20 (5 V),and J12 (GND) on the EVM are used to connect the EVM to offboard dc power supply to support alldevices onboard. A few options for supply connection are shown in Table 1 . The default one is using J20(5 V) and J12 (GND) as well as J16 (for OPA) to connect the EVM with the offboard supply. Two 3.3-Vsupply voltages can be generated on board from 5 V through U3(TPS79633DCQ), U8 (TPS79633DCQ),and U9 (TPS79601DCQ) as the EVM default setting. Two 3.3-V supply voltages can also be providedfrom the offboard power supplies through J13 and J11 (see Table 1 ).
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2.2.2 ADC Analog Input
2.2.3 ADC Clock Input
2.2.4 ADC Digital Output
2.2.5 Jumper Selections for ADS556x Configuration
www.ti.com Circuit Description
Table 1. EVM Power Supply Connections
Shorted 1 and 2 Shorted 2 and 3 Default Setting
JP16 3.3 Va is from LDO solution external 3.3-V supply connects to J13 Shorted 2 and 1
JP17 3.3 Vd is from LDO solution external 3.3-V supply connects to J11 Shorted 2 and 1
ADS556x EVM also can be powered from the TSW1200EVM (optional). On the TSW1200EVM, J7 is a6-V wall power supply connector; connect it to 6 V with JP8 (1 to 2 short) and J22 open. TheTSW1200EVM can provide a 5-V output at the J15 connector. Connect J15 to the 5-V banana jack on theADS556xEVM to provide a 5-V supply for the ADS556xEVM.
Connectors J6 (SMA) and J8 (SMA) are used to connect the ADC with the offboard analog signal source.At default, J8 is not installed as it is connected to GND. A single-ended analog signal, for example a sinewave, is input to J6; then, it is converted into a differential signal through transformers T1 and T2 orthrough T5 and THS4509 to the ADC’s differential analog input pins. A few configurations are possible forthe analog input path. The default one is a transformer-coupling configuration through T1 and T2. Thetotal ratio of transformers T1 and T2 is 1:1. This configuration gives an equivalent load of 50 Ωto thesignal source in a certain frequency range, and it is a default setting from the factory. The common-modevoltage Vcm for the analog input of ADC is provided from the ADC’s CM pin. R81, C74, and R68 form alow-pass filter to filter the glitch from the sample and hold stage.
Another analog input configuration for the ADC input is through the fully differential THS4509 amplifier. Toreceive an analog signal from the THS4059, it needs to switch the connection on SJP5 and SJP3, andSJP1 and SJP2 (see Table 2 ); the analog source signal is connected to J6 for a signal-ended signalsource. The source signal is coupled by the 1:1 transformer T5 to THS4509. It is gained by 10 dB throughthe amplifier and filtered by a LC low-pass or band-pass filter (users can configure it through a flexiblelayout), then through transformers T1 and T2 to the ADC differential input. The ADC’s CM pin provides thecommon-mode voltage Vcm for the THS4509. By default, the THS4509 path is not connected to the inputof ADS556x. To use THS4509 driving the analog input of ADS556x, JP1, JP2, JP3, and JP5 need to bereconnected from the default position as shown in the Table 2 .
Table 2. Analog Input Selection Through Surface-Mount Jumpers
SJP3 SJP5 SJP1 SJP2
Transformer single-ended (SE) input through J6 Short 1 to 2 Short 1 to 2 Short 1 to 2 Short 1 to 2OPA SE input through J6 Short 2 to 3 Short 2 to 3 Short 2 to 3 Short 2 to 3
The ADC clock input is from connector J9, a single-ended (SE) clock source connector. The SE clock isconverted into a differential clock through the 1:4 transformer to the ADC clock input pins. The resistorR29 is a 50- Ωsource termination. A sine wave with a 1.5-V amplitude can be used for the evaluation test.
The digital output of ADS556x is brought to the 40-pin IDC connector J5 for CMOS parallel output; it isalso brought to a high-density Samtec connector J10 for DDR LVDS output as a default setting (interfaceto TSW1200). The connectors J5 and J10 can be accessed by a logic analyzer and other CMOS digitalinterface directly, for example, the TSW1200 data capture board (through J10). The connector J10 can beextended by the TI ADC breakout board to interface with the LVDS receiver including the logic analyzer. Ifthe CMOS parallel output is used, the U7 (SN74AVC16244DGGR) must be installed.
The EVM features different models of the ADS556x for evaluation. The model selection is based on aninternal control register setting. To access the internal control registers, the ADS556x provides threeaccess interfaces, parallel interface, serial interface, and parallel and serial mixed interface. The default
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3 Serial Interface Control
3.1 Installing the AD SPI Control Software
Serial Interface Control www.ti.com
setting for the EVM is parallel interface, where the RESET pin is tied to high (AVdd) through JP12. Theinterface includes six pins: SCLK, SEN, SDATA, DFS, and MODE plus a RESET pin. The detail functionsof these pins are described in the data sheet. On the EVM, these control pins are connected to jumpersJP9, JP11, J12, and J1 to J3. Table 3 to Table 5 describe all possible settings of these jumpers. For thefunction of each setting, see the data sheet.
Table 3. Jumper Setting for Control Interface
Parallel interface (default setting) Serial interfaceJP12 (RESET) Short 1 to 2 Short 2 to 3JP11 (SDATA) Floating 2 (normal) or Short 1 to 2 Short 2 to 3JP9 (SEN) Short 1 to 2 Short 2 to 3
Table 4. Jumper Setting for Control Pins SEN, DFS, and MODE at Parallel Interface
AVdd (5/8)AVdd (3/8)AVdd GND
J1 (SEN: short 1 to 2 on JP9) Short 7 to 8 Short 5 to 6 Short 3 to 4 Short 1 to 2J2 (DFS) Short 7 to 8 Short 5 to 6 Short 3 to 4 Short 1 to 2J3 (MODE) Short 7 to 8 Short 5 to 6 Short 3 to 4 Short 1 to 2
Table 5. Jumper Setting for Control Pins SDATA and SCLK at Parallel Interface
3.3 V GND (default setting)
JP11 (SDATA) Short 2 to 1 Pin 2 is floatSCLK Float
For serial interface access, SEN, SDATA, and SCLK function as serial interface pins and are used toaccess the internal registers of the ADC. Their relative jumper settings are shown in Table 3. The pinsDFS and MODE must be set to GND through jumpers J2 (short 1 to 2) and J3 (short 1 to 2) at serialinterface control. The serial interface control is implemented by an ADC SPI control software installed onthe PC and a USB port (J17) on the EVM. For evaluating the ADC, it is unnecessary for users to use aserial interface. Users only need the serial interface software when the desired feature is inaccessible bythe parallel interface mode.
The ADC SPI control software can be installed on a personal computer by running the setup.exe filelocated on the CD. This file installs the graphical user interface (GUI) along with the USB drivers neededto communicate to the USB port that resides on the EVM. After the software is installed and the USBcable has been plugged in for the first time, the user is prompted to complete the installation of the USBdrivers. When prompted, allow the Windows™ operating system to search for device drivers. Itautomatically finds the TI ADC SPI Interface drivers. Figure 1 shows the SPI interface. Click the right topbutton to select the ADS556x device.
Note: Before plugging in the USB cable for the first time, install the TI ADC SPI software. Thesoftware installs the necessary drivers for USB communication.
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3.2 Using the ADC SPI Interface Software
3.2.1 SPI Register Writes
www.ti.com Serial Interface Control
Figure 1. TI ADC SPC Interface Screen
Once the software is installed and the USB cable is connected, three primary modes of operating thesoftware are available: SPI Register Writes, SPI Register Write Using a Script File, and ADC FrequentlyUsed Registers.
The most basic mode of operation allows full control of writing to individual register addresses. In the topleft corner of the interface screen, select the ADS5545/46/47/25/27/60/62 from the ADC SPI Protocoldrop-down list. Next, type the Address Bytes(s) in hexadecimal (hex) and Data Byte(s) in hex which canbe found in the device data sheet. When you are ready to send this command to the ADC, press "Enter"on your keyboard, or press "Send Data". The graph indicator is updated with the patterns sent to the ADC.The default inputs to both the Address Byte(s) and Data Byte(s) fields are hex inputs as designated by thesmall "x" in the control. Users can change the default input style by clicking on the "x" to binary, decimal,octal, or hex. Multiple register writes can be written simply by changing the contents of the AddressByte(s) and Data Byte(s) field, and pressing Enter again.
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3.2.2 SPI Register Write Using a Script File
3.2.3 ADS556x Frequently Used Registers
3.2.4 Using Both Serial Interface and Parallel Controls
3.3 TSW1200 Capture Board
Serial Interface Control www.ti.com
For situations where the same multiple registers need to be written on a frequent basis, users can easilycreate a script file using a test editor containing all ADC register writes. An example Script File is locatedin the \\Install Directory\Script Files\ADS6145_LVDS_CourseGain.txt . Users who wish to take advantageof writing their own script files can start by using the ADS6145_LVDS_CourseGain.txt as a template file.When ready to write the contents of the script file to the ADC, users can press the Load Script button, andthey are prompted for the file location of their script file. The commands are sent to the ADC when theuser acknowledges the selection of the file.
For ease of use, several buttons have been added that allow one-click register writes of commonly usedfeatures found in Table 6 . The software writes to the ADC both the contents of the associated addressand data when the button is clicked. When the ADSxxxx Reset button is pressed, it issues a softwarereset to the ADC, and it resets the button values to match the contents inside of the ADC. The graphindicator plots the SPI commands written to the ADC when a button has been depressed.
Table 6. Frequently Used Registers
Default Value Alternate Value
ADSxxxx Reset2s Complement Straight binaryCMOS/LVDS : DFS pin determines DDR LVDS/CMOSPowerdown: OFF Powerdown onFine gain: 1 Up to 6-dB gainINT reference EXT referenceLVDS current: 3.5 mA Multiple optionsTest mode: None Multiple optionsLow sampling speed: off Low sampling speed: onLF noise suppression: off LF noise suppression: on
For increased flexibility, a combination of serial interface registers and parallel pin controls (DFS, MODE)also can be used to configure the device. For more details, see the data sheet .
The TSW1200 board can be used to analyze the performance of the EVM. The TSW1200EVM is a circuitboard that assists designers in prototyping and evaluating the performance of high-speed ADCs thatfeature parallel or serialized LVDS outputs. The TSW1200 has the LVDS 100- Ωtermination resistor on theinput interface for ADC outputs. For more information, see the TSW1200EVM user's guide (SLAU212 ).
To start the TSW1200 software, note the following points.1. Select the ADC type to be used before capturing.2. For test, select Single Tone FFT plot.3. For the ADC Sampling Rate, type in the value.4. Type in the ADC Input Frequency. Auto calculation of the input frequency depends on the FFT recordlength. As soon as the number is entered, the software calculates the coherent input frequencycorresponding to that FFT length. This frequency signal must be supplied through the signal generator.5. Select the FFT Record Length.6. Select Capture to obtain the plot.7. The Continuous Capture option is used if the user wants to continuously capture the FFT.
Adjust the input level signal to attain the dBFs of approximately –1.
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4 ADC Evaluation
4.1 Hardware Selection
4.1.1 Analog Input Signal Generator
www.ti.com ADC Evaluation
Figure 2. TSW1200 GUI Introduction
This section describes how to set up a typical ADC evaluation system that is similar to what TI uses toperform testing for data-sheet generation. Consequently, the information in this section is generic in natureand is applicable to all high-speed, high-resolution ADC evaluations. This section covers signal toneanalysis, which yields ADC data-sheet figures of merit such as signal-to-noise ratio (SNR) and spuriousfree dynamic range (SFDR).
To reveal the true performance of the ADC under evaluation, take great care in selecting both the ADCsignal source and the ADC clocking source.
When choosing the quality of the ADC analog input source, consider both harmonic distortion performanceof the signal generator and the noise performance of the source. In many cases, the harmonic distortionperformance of the signal generator is inferior to that of the ADC, and additional filtering is needed if usersexpect to reproduce the ADC SFDR numbers found in the data sheet. Users can easily evaluate theharmonic distortion of their signal generator by hooking it directly to a spectrum analyzer and measuringthe power of the output signal and comparing that to the power of the integer multiples of the outputsignal's frequency. If the harmonic distortion is worse than the ADC under evaluation, the ADC digitizesthe performance of the signal generator and the true SFDR of the ADC is masked. To avoid this, TIrecommends that users provide additional LC filtering (BPF) after the signal generator output. Anotherimportant metric when deciding on a signal generator is its noise performance. As with the distortionperformance, if the noise performance is worse than that of the ADC under evaluation, the ADC digitizes
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4.1.2 Clock Signal Generator
4.2 Coherent Input Frequency Selection
5 Physical Description
5.1 PCB Layout
Physical Description www.ti.com
the performance of the source. Noise can be broken into two components, broadband noise and close-inphase noise. Broadband noise can be improved by the LC filter added to improve distortion performance.The close-in phase noise, however, typically cannot be improved by additional filtering. Therefore, whenselecting an analog signal source, it is important to review the manufacturer's phase noise plots and takecare to choose a signal generator with the best phase-noise performance.
Equally important in the high-performance ADC evaluation setup is the selection of the clocking source.Most modern ADCs accept either a sinusoidal or a square-wave clock input. The key metric in selecting aclocking source is selecting a source with the lowest jitter. This becomes increasingly important as theADC input frequency (Fin) increases, because the ADC SNR evaluation setups can become jitter-limited(To) as shown by the following equation.
SNR (dBc) = 20 log [2 π × Fin ×Tj(rms)]
In theory, a square-wave source with femtosecond jitter is ideal for an ADC evaluation setup. However, inpractical terms, most commercially available square-wave generators offer jitter measured in picoseconds,which is too great for high-resolution ADC evaluation setups. Therefore, most evaluation setups rely onthe ADC's internal clock buffer to convert a sinusoidal input signal into a ultralow-jitter square wave. Whenselecting a sinusoidal clocking source, it has been shown that phase noise has a direct impact on jitterperformance. Consequently, great scrutiny must be applied to the phase-noise performance of theclocking signal generator. TI has found that high-Q monolithic crystal filters can improve the phase noiseof the signal generator, and these filters become essential elements of the evaluation setup when highADC input frequencies are being evaluated.
Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fouriertransform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that thesignal must be continuous-time. However, this is impractical when looking at a finite set of ADC samples,usually collected from a logic analyzer. Consequently, users typically apply a window function to minimizethe time-domain discontinuities that arise when analyzing a finite set of samples. For ADC analysis,window functions have their own frequency signatures or lobes that distort both SNR and SFDRmeasurements of the ADC. TI uses the concept of coherent sampling to work around the use of a windowfunction. The central premise of coherent sampling entails that the input signal into the ADC is carefullychosen such that when a continuous-time signal is reconstructed from a finite sample set, no time-domaindiscontinuities exist. To achieve this, the input frequency must be an integer multiple of the ratio of theADC's sample rate (f
s
) and the number of samples collected from the logic analyzer (N
s
). The ratio of f
s
toN
s
is typically referred to as the fundamental frequency (f
f
). Determining the ADC input frequency is atwo-step process. First, users select the frequency of interest for evaluating the ADC; then, they divide thisby the fundamental frequency. This typically yields a noninteger value, which must be rounded to thenearest odd, preferably prime, integer. Once that integer, or frequency bin (f
bin
), has been determined,users multiply this with the fundamental frequency to obtain a coherent frequency to program into theirADC input signal generator. The procedure is summarized as follows.f
f
= f
s
/N
sf
bin
= Odd_round(f
desired
/f
f
)Coherent frequency = f
f
×f
bin
This section describes the physical characteristics and PCB layout of the EVM.
The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers areshown in Figure 3 through Figure 6 . The layout features a split ground plane; however, similarperformance can be had with a careful layout using a common ground plane.
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www.ti.com Physical Description
Figure 3. Top Silkscreen
Figure 4. Ground Plane
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Physical Description www.ti.com
Figure 5. Power Plane
Figure 6. Bottom Silkscreen
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5.2 Bill of Materials
www.ti.com Physical Description
Table 7. ADS61B49EVM Bill of MaterialsQTY Reference Not Installed Part Foot Print Part Number Manufacturer Toleran Volt Wattce
5 C1, C5, C8, C35, 33 µF TANT_B B45196H2336M209 Kemet 20% 10VC52
5 C2, C9, C30, C36, 10 µF 805 ECJ-2FB0J106K Panasonic 10% 6.3VC57
2 C3, C6 1 µF 603 ECJ-1VB1A105K Panasonic 10% 10V
32 C4, C7, C11–C13, 0.1 µF 603 ECJ-1VB1C104K Panasonic 10% 16VC16–C19, C32,C37, C53, C70,C72, C78–C81,
C83, C85,C87–C89, C92,C96–C103
2 C10, C14 22 µF TANT_B T491B226M016AT KEMET 20% 16V
5 C15, C33, C34, 0.1 µF 603 GRM188R71H104KA93D Murata 5% 50VC68, C69
4 C31, C40, C43, 1 µF 603 GRM188R61E105KA12D Murata 10% 25VC45
3 C38, C41, C44 2.2 µF 805 GRM21BR71E225KA73L Murata 10% 25V
2 C39, C46 0.01 µF 603 GCM188R71H103KA37D Murata 10% 50V
1 C42 33 pF 603 06031A330FAT2A AVX 1% 100V
1 C51 33 nF 603 06035C333KAT2A AVX 10% 50V
4 C71, C73, C82, 10uF 805 ECJ-2FB1A106K Panasonic 10% 10VC84
1 C74 3.3 pF 603 GRM1885C1H3R3CZ01D Murata ±0.25 pF 50V
0 C75, C77 Not Installed 47 pF 603 ECJ-1VC1H470J Panasonic 5% 50V
0 C76, C104 Not Installed 5 pF 603 ECJ-1VC1H050C Panasonic ±0.25 pF 50V
1 C86 10 µF TANT_A T491A106M010AT Kemet 20% 10V
2 C90, C91 27 pF 603 GRM1885C2A270JA01D Murata 5% 100V
1 C93 0.01 µF 603 C0603C103K1RACTU Kemet 10% 100V
2 C94, C95 5.6 pF 603 GRM1885C1H5R6DZ01D Murata ±0.5 pF 50V
1 D1 Green diode_0603 LNJ312G8TRA Panasonic
1 D2 Yellow diode_0603 SML-311YTT86 ROHM
1 JP11 Jumper_1x3 HDR_THVT_1x3_100 22-28-4030 Molex
5 JP9,JP7, JP12, Header 3POS 0.1 CTR JUMPER3 22-28-4030 Molex Short pins 1-2 with shuntJP16, JP17 connector DigiKey #S9000-ND (see Figure 7 )
1 JP15 Header 2/SM JUMPER2 22-28-4020 Molex
3 J1, J2, J3 Header 4x2 hdr4X2_100ctr 90131-0124 Molex Short pins 1-2 with shuntconnector DigiKey #S9000-ND (see Figure 7 )
1 J5 Header male 20x2 POS CON20X2_100ctr_M_tsw PBC20DAAN Samtec0.100 VERT 1100_mate
2 J6, J9 SMA SMA_THVT_320x320 142-0701-201 Johnson Components
0 J8 Not Installed SMA SMA_THVT_320x320 142-0701-201 Johnson Components
1 J10 CONN_QTH_30X2-D-A conn_QTH_30X2-D-A QTH-060-02-F-D-A Samtec
4 J11, J13, J16, J20 RED BANANA_JACK ST-351A Allied Electronics
1 J12 BLK BANANA_JACK ST-351B Allied Electronics
1 J17 CONN USB TYP B conn_usb_typb_fem 897-43-004-90-000 MilmaxFEM
5 L1–L3, L8, L9 68 603 MI0603J680R-10 Steward
0 L6, L7 Not Installed 150nH 603 0603-151J API Delavan Inc. 5%
1 L10 1K at 100 MHz 805 BLM21AG102SN1D Murata
0 L11, L12 Not Installed 47 nH 603 PE-0603CD470JTT Pulse 5%
2 RN1, RN2 22 rnet8_16_0603 MNR18E0APJ220 ROHM 5% 62.5mW
4 RN3–RN6 0 Ωrnet4_8_0603 TC164-JR-070RL
1 R1 750 603 ERJ-3EKF7500V Panasonic 1%
1 R2 402 603 MCR03EZPFX4020 ROHM 1%
9 R3–R5, R58–R60, 1K 603 ERJ-3EKF1001V Panasonic 1% 1/10WR62–R64
5 R6, R10, R15, 10K 603 ERJ-3EKF1002V Panasonic 1% 1/10WR18, R35
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Physical Description www.ti.com
Table 7. ADS61B49EVM Bill of Materials (continued)QTY Reference Not Installed Part Foot Print Part Number Manufacturer Toleran Volt Wattce
6 R7, R65–R67, 0 Ω603 ERJ-3GEY0R00V Panasonic 5% 1/10WR69, R70
1 R12 14K 603 RC0603FR-0714KL Yageo 1% 1/10W
5 R13, R19, R20, 100 603 ERJ-3EKF1000V Panasonic 1% 1/10WR40, R44
1 R16 Not Installed 10 603 ERJ-3EKF10R0V Panasonic 1% 1/10W
1 R17 30.1K 603 MCR03EZPFX3012 ROHM 1% 1/10W
2 R21, R26 4.99 603 CRCW06034R99FNEA Dale/Vishay 1% 1/10W
0 R22 ,R25 Not Installed 49.9 603 ERJ-3EKF49R9V Panasonic 1% 1/10W
2 R23, R24 24.9 603 ERJ-3EKF24R9V Panasonic 1% 1/10W
0 R27, R28 Not Installed 121 603 ERJ-3EKF1210V Panasonic 1% 1/10W
3 R29, R68, R81 49.9 603 ERJ-3EKF49R9V Panasonic 1% 1/10W
2 R36, R48 348 603 ERJ-3EKF3480V Panasonic 1% 1/10W
0 R38, R46 Not Installed 68 603 MCR03EZPFX68R0 ROHM 1% 1/10W
1 R49 10K 603 ERJ-3GEYJ103V Panasonic 5% 1/10W
1 R50 2.21K 603 ERJ-3EKF2211V Panasonic 1% 1/10W
1 R51 4.7K 603 ERJ-3EKF4R71V Panasonic 1% 1/10W
0 R52 Not Installed 10K 603 ERJ-3EKF1002V Panasonic 1% 1/10W
1 R53 1.5K 603 ERJ-3EKF1501V Panasonic 5% 1/10W
0 R54 Not Installed 0 Ω603 ERJ-3GEY0R00V Panasonic 5% 1/10W
2 R55, R56 26.7 603 ERJ-3EKF26R7V Panasonic 1% 1/10W
0 R82 Not Installed ZERO 603 ERJ-3GEY0R00V Panasonic 5% 1/10W
2 R84, R87 ZERO 603 ERJ-3GEY0R00V Panasonic 5% 1/10W
1 R85 ZERO 603 ERJ-3GEY0R00V Panasonic 5% 1/8W
0 R86 Not Installed ZERO 603 ERJ-3GEY0R00V Panasonic 5% 1/8W
4 SJP1–SJP3, SJP5 JUMPER_1x3_SMT smd_bridge_0603 Short 1-2 using 0 Ωresistors
1 SW1 SW Pushbutton SW_RESET_PTS635 PTS635SL43 C & K Switch
5 TP1, TP3, TP6, Test Point Black testpoint 5001 KeystoneTP11, TP13
5 TP2, TP4, TP5, Test Point White testpoint 5002 KeystoneTP10, TP12
3 T1, T2, T5 WBC1-1 XFMR_WBC4-1W WBC1-1TL Coilcraft
1 T3 TC4-1T XFMR_TC4-1W TC4-1T Mini Circuits
1 U1 ADS61X9 QFN48 TI
2 U3, U8 TPS79633DCQ SOT_223_6_TG TPS79633DCQR TI
1 U4 THS4509 QFN16 THS4509RGTT TI
1 U5 93C66B TSSOP8 93C66B-I/ST Microchip
1 U6 FT245BM PQFP32 FT245BM Future Technology
Devices
0 U7 Not Installed SN74AVC16244DGGR TSSOP_48_496x244_20
1 U9 TPS79601DCQ SOT_223_6_TG TPS79601DCQR TI
1 Y1 6.0000 MHz smd_csm-7_xtal ECS-60-32-5PDN-TR ECS
Screw machine, PMS 440 0038 PH Building Fasteners PCB legsph 4-40 X 3/8
Stand-off hex 1902C Keystone Electronic0.5/4-40THR
ADS5560/62EVM 12 SLAU260 – December 2008Submit Documentation Feedback

www.ti.com Physical Description
Figure 7. TSW12XXEVM – Connector
SLAU260 – December 2008 ADS5560/62EVM 13Submit Documentation Feedback

5.3 EVM Schematics
AMP_PD
AMP+ AMP-
AMP_IN- AMP_IN+
AMP-
AMP_IN-
IN-
AMP_IN+
IN+
AMP+
CLKIN
CLK-
CLK+
VSS+
VSS-
VSS+
AMP_VCMSH2
IN_P SH2 IN_M SH2
VCM SH2
ICLKP SH2
ICLKM SH2
Default: Short 1-2
DNI: Do Not Install
DNI DNI DNI
DNI
DNI DNI
DNI
DNI
DNI
DNI DNI
DNI
DNI
DNI
DNI
DNI DNI
VSS- = VSS+ minus 5V
NOTE: R23, R24 = 33ohm + 150pF in same space (stacked in parallel)
*
*
*
R44
100
R44
100
C71
10uF
10V
C71
10uF
10V
12
R46
68
R46
68
T5 WBC1-1 T5 WBC1-1
3 2 1
6 5 4
C95 120pF C95 120pF
L7
150nH
L7
150nH
12
C77
47pF
C77
47pF
C79
.1uF
16V C79
.1uF
16V
C18
.1uF 16V
C18
.1uF 16V
12
MS A
DE N
J8
MS A
DE N
J8
1
5234
R35
10K 1/10W
1%
R35
10K 1/10W
1%
C70
.1uF
16V C70
.1uF
16V
R27
121 1/10W
1%
R27
121 1/10W
1%
C15 .1uF C15 .1uF
12
C75
47pF
C75
47pF
L12 47nH L12 47nH
1 2
SJP1
(SHORT 1-2)
SJP1
(SHORT 1-2)
1 3
2
R36
348
R36
348
SJP3
(NO SHUNT)
SJP3
(NO SHUNT)
1 3
2
C74
3.3pF
DNI
C74
3.3pF
DNI
R22
49.9
R22
49.9
R23
33
R23
33
R26
12.1
R26
12.1
C104 5pF C104 5pF
L11
47nH
L11
47nH
1 2
R29
49.9 1/10W
1%
R29
49.9 1/10W
1%
T3
TC4-1T
T3
TC4-1T
3 2 1
6 5 4
L6 150nH L6 150nH
12
C16
.1uF 16V
C16
.1uF 16V
12
C33 .1uF C33 .1uF
1 2
C69
33uH
C69
33uH
12
R28
121 1/10W
1%
R28
121 1/10W
1%
R24
33
R24
33
JP7JP7
1 3
2
C80
.1uF
16V C80
.1uF
16V
SJP2
(SHORT 1-2)
SJP2
(SHORT 1-2)
1 3
2
U4
THS4509
U4
THS4509
NC
1
VIN-
2
CM1
4
VS+
5
VS+
6
VOUT+ 3
VS+
7
VS+
8
CM2 9
VOUT- 10
VIN+
11
PD 12
VS- 13
VS- 14
VS- 15
VS- 16
PAD
17
MS A
DE N
J9
SMA
MS A
DE N
J9
SMA
1
5234
R86 ZERO R86 ZERO
R40
100
R40
100
T1
WBC1-1
T1
WBC1-1
3 2 1
6 5 4
C73
10uF
10V
C73
10uF
10V
12
C82
10uF
10V
C82
10uF
10V
12
C72
.1uF
16V C72
.1uF
16V
R38
68
R38
68
R84
ZERO
R84
ZERO
12
R25
49.9
R25
49.9
C78
.1uF
16V C78
.1uF
16V
R81
49.9
DNI R81
49.9
DNI
R48
348
R48
348
C76 5pF C76 5pF
C81
.1uF
16V C81
.1uF
16V
R87 ZERO R87 ZERO
C19
.1uF
16V C19
.1uF
16V
R82 ZERO R82 ZERO
1
2
C68
33uH
C68
33uH
12
C84
10uF
10V
C84
10uF
10V
12
C17
.1uF
16V C17
.1uF
16V
T2
WBC1-1
T2
WBC1-1
3 2 16
5 4
C34 .1uF C34 .1uF
1 2
MS A
DE N
J6
MS A
DE N
J6
1
5234
C94 120pF C94 120pF
C83
.1uF
16V C83
.1uF
16V
R68
49.9
DNI R68
49.9
DNI
R21
12.1
R21
12.1
SJP5
(SHORT 1-2)
SJP5
(SHORT 1-2)
1 3
2
Physical Description www.ti.com
ADS5560/62EVM 14 SLAU260 – December 2008Submit Documentation Feedback

SEN
SDA
SEN
RESET
DFS
SCL
MODE
+3.3VD
+3.3VA
+3.3VA
+3.3VD
+3.3VA
+3.3VA
+3.3VA
+3.3VA
+3.3VA
+3.3VA
IN_MSH1 IN_PSH1
D2_D3-P SH3
D0_D1-P SH3 D0_D1-M SH3
D2_D3-M SH3
D4_D5-P SH3
D4_D5-M SH3
D6_D7-P SH3
D6_D7-M SH3
CLKOUT_PSH3 CLKOUT_MSH3
D8_D9-P SH3
D8_D9-M SH3
D10_D11-P SH3
D10_D11-M SH3
D12_D13-P SH3
D12_D13-M SH3
ICLKPSH1
ICLKMSH1
SDATA SH4
VCMSH1
CS SH4
SCLK SH4
FPGA_SEN SH3
FPGA_SCLK SH3
FPGA_SDATA SH3
OVRSH3
AMP_VCMSH1
RESERVED-P SH3 RESERVED-M SH3
PARALLEL INTERFACE SERIAL INTERFACE
Defaut OPEN
DNI
DNI
DNI
TP11 TP11
R58
1K
R58
1K
12
R64 1K R64 1K
12
C97
.1uF
C97
.1uF
12
R20 100 R20 100
12
R60
1K
R60
1K
12
R63 1K R63 1K
12
TP10TP10
C13 .1uF C13 .1uF
12
R85 ZERO R85 ZERO
R15 10K R15 10K
12
JP9JP9
1 3
2
C32 .1uF C32 .1uF
12
R67 0 OHM R67 0 OHM
TP13TP13
R66 0 OHM R66 0 OHM
R13 100 R13 100
12
JP11JP11
1 3
2
JP12JP12
1 3
2
C12
.1uF
C12
.1uF
12
U1
ADS556X
U1
ADS556X
DRGND
1
DRVDD
2
OVR
3
CLKOUTM
4
CLKOUTP
5
DFS
6
OE
7
AVDD
8
AGND
9
CLKP
10
CLKM
11
AGND
12
VCM
13
AGND
14
INP
15
INM
16
AGND
17
AVDD
18
AGND
19
AVDD
20
NC
21
AVDD
22
MODE
23
AVDD
24
AGND 25
AVDD 26
SEN 27
SDATA 28
SCLK 29
RESET 30
NC1 31 NC2 32
GND
49
D0_D1_M 33
D0_D1_P 34
D2_D3_M 37
D2_D3_P 38
DRVDD 35
DRGND 36
D4_D5_P 40
D4_D5_M 39
D6_D7_P 42
D6_D7_M 41
D8_D9_P 44
D8_D9_M 43
D10_D11_P 46
D10_D11_M 45
D12_D13_P 48
D12_D13_M 47
R18 10K R18 10K
12
R7 0 OHM R7 0 OHM
JP15JP15
1 2
TP6TP6 R65 0 OHM
R65 0 OHM
R10 10K R10 10K
12
TP1TP1
J2J2
2 4 6 8
1 3 5 7
C96
.1uF
C96
.1uF
12
R19 100 R19 100
12
R6 10K R6 10K
12
TP2TP2
TP3TP3
J1J1
2 4 6 8
1 3 5 7
TP5TP5
C85
.1uF
C85
.1uF
12
SW1SW1
TP4TP4
C11 .1uF C11 .1uF
12
R3 1K R3 1K
12
J3J3
2 4 6 8
1 3 5 7
R5 1K R5 1K
12
C98
.1uF
C98
.1uF
12
R59
1K
R59
1K
12
R16 10 R16 10
R4 1K R4 1K
12
C99
.1uF
C99
.1uF
12
TP12TP12
R62 1K R62 1K
12
www.ti.com Physical Description
SLAU260 – December 2008 ADS5560/62EVM 15Submit Documentation Feedback

CLKOUT
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12
CLKOUT
CLKOUTP CLKOUTM D12_D13_P D10_D11_P D8_D9_P D12_D13_M D10_D11_M D8_D9_M
CLKOUTM CLKOUTP
D6_D7_P D6_D7_M D4_D5_P D2_D3_P D0_D1_P D4_D5_M D2_D3_M D0_D1_M
D4 D5 D0 D1 D2 D3
D12 D13 D9 D10 D11
D6 D7
D8
RESERVED_P RESERVED_M
RESERVED_P RESERVED_M D12_D13_M D12_D13_P D10_D11_M D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P
+3.3V_AUX
+3.3V_AUX
+3.3V_AUX
FPGA_SDATA SH2 FPGA_SEN SH2 FPGA_SCLK SH2
D6_D7-PSH2 D6_D7-MSH2
D4_D5-PSH2 D4_D5-MSH2 D2_D3-PSH2 D2_D3-MSH2 D0_D1-PSH2 D0_D1-MSH2 D6_D7-PSH2 D6_D7-MSH2
D12_D13-PSH2 D10_D11-PSH2
D8_D9-PSH2
D12_D13-MSH2 D10_D11-MSH2
D8_D9-MSH2
CLKOUT_PSH2 CLKOUT_MSH2
D8_D9-PSH2 D8_D9-MSH2 D4_D5-MSH2 D4_D5-PSH2
D12_D13-PSH2 D12_D13-MSH2
D0_D1-PSH2 D0_D1-MSH2 D2_D3-PSH2 D2_D3-MSH2
D10_D11-PSH2 D10_D11-MSH2 CLKOUT_PSH2 CLKOUT_MSH2
OVRSH2
RESERVED-PSH2 RESERVED-MSH2
RN1
22 RN1 22
116 215 314 413 512 611 710 89
J10
CONN_QTH_30X2-D-A
J10
CONN_QTH_30X2-D-A
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 G1
G2
G3
G4
G5
G6
G7
G8
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
C100 .1uF C100 .1uF
12
RN2
22 RN2 22
116 215 314 413 512 611 710 89
C102 .1uF C102 .1uF
12
R70 0 OHM R70 0 OHM
C103 .1uF C103 .1uF
12
RN3 0 ohm RN3 0 ohm
1 2 3 45
6 7 8
C101
.1uF
C101
.1uF
12
RN4 0 ohm RN4 0 ohm
1 2 3 45
6 7 8
R69 0 OHM R69 0 OHM
U7
SN74AVC16244DGGR
U7
SN74AVC16244DGGR
1Y1 2 1Y2 3 1Y3 5 1Y4 6 2Y1 8 2Y2 9 2Y3 11 2Y4 12 3Y1 13 3Y2 14 3Y3 16 3Y4 17 4Y1 19 4Y2 20 4Y3 22 4Y4 23
1A4
43 1A3 44 1A2 46 1A1 47
2A4
37 2A3 38 2A2 40 2A1 41
3A4
32 3A3 33 3A2 35 3A1 36
4A4
26 4A3 27 4A2 29 4A1 30
1OE
1
4OE
24 3OE 25 2OE 48
GND1
4
GND2
10
GND3
15
GND4
21 GND5 28
GND6 34 GND7 39 GND8 45
VCC1
7
VCC2
18 VCC3 31
VCC4 42
RN5 0 ohm RN5 0 ohm
1 2 3 45
6 7 8
RN6 0 ohm RN6 0 ohm
1 2 3 45
6 7 8
J5
HEADER MALE 20x2 POS .100 VERT
DATA_OUT
J5
HEADER MALE 20x2 POS .100 VERT
DATA_OUT
1
2 4 6 8
10 12 14 16 18 20 22 24 26 28 30 32
3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33
34
35
36
37
38
39
40
Physical Description www.ti.com
ADS5560/62EVM 16 SLAU260 – December 2008Submit Documentation Feedback

SDATA
CS SCLK
5V
5V
+3.3V_AUX
5V
5V
5V
5V
SCLK SH2 SDATA SH2 CS SH2
Do Not Install
Do Not Install
L10
1K @ 100MHZ
L10
1K @ 100MHZ
12
R54
0 OHM
R54
0 OHM
12
C87 .1uF C87 .1uF
12
U5
93C66B U5 93C66B
CS 1
CLK 2
DI 3
DOUT 4
VSS
5NC 6ORG 7VCC 8
R49 10K R49 10K
12
R52
10K
R52
10K
12
R55 26.7 R55 26.7
12
C89 .1uF C89 .1uF
12
C92
.1uF
C92
.1uF
12
J17
CONN USB TYP B FEM
J17
CONN USB TYP B FEM
1 23
4
R50
2.21K
R50
2.21K
12
C88 .1uF C88 .1uF
12
C91 27pF C91 27pF
12
U6
FT245BM
U6
FT245BM
EESK
1
EEDATA
2
VCC
3
RESET
4
RSTOUT
5
3V3OUT
6
USBDP
7
USBDM
8
RD
16 WR
15 TXE
14 VCCIO
13 RXF
12 SI/WU
11 PWREN
10 GND
9
D1 24 D2 23 D3 22 D4 21 D5 20 D6 19 D7 18
GND 17
D0 25
VCC 26
XTIN 27
XTOUT 28
AGND 29
AVCC 30
TEST 31
EECS 32
R56
26.7
R56
26.7
12
C90
27pF
C90
27pF
12
C51 33nF C51 33nF
12
+
C86 10uF
+
C86 10uF
12
Y1
6.0000MHz
Y1
6.0000MHz
C93 .01uF C93 .01uF
1 2
R53 1.5K R53 1.5K
12
R51
4.7K
R51
4.7K
12
www.ti.com Physical Description
SLAU260 – December 2008 ADS5560/62EVM 17Submit Documentation Feedback

5V_IN +3.3V_IN
+3.3VA
5V
VSS+ VSS-
+3.3VD
5V +3.3V_AUX
5V
3.3V_LDO
+3.3V_LDO
3.3V_LDO
5V +3.3V_LDO
C37
.1uF
16V C37
.1uF
16V
L1 68 L1 68
12
R12 51K R12 51K
12
C3 1uF C3 1uF
12
C41
2.2uF
10%
25V
C41
2.2uF
10%
25V
J13 RED
+3.3V_IN
J13 RED
+3.3V_IN
C4 .1uF C4 .1uF
12
U9
TPS79601DCQ
U9
TPS79601DCQ
EN
1
IN
2
GND
3
OUT 4
NR/FB 5
GND 6
JP17
(SHORT 1-2)
JP17
(SHORT 1-2)
1 3
2
C30
10uF
6.3V
C30
10uF
6.3V
12
C46 0.01uF C46 0.01uF
+
C10 22uF
+
C10 22uF
12
U8
TPS79633DCQ
U8
TPS79633DCQ
EN
1
IN
2
GND
3
OUT 4
NR/FB 5
GND 6
C40 1uF 10%
25V
C40 1uF 10%
25V
R1 750 R1 750
12
C45 1uF 10%
25V
C45 1uF 10%
25V
D2 Yellow D2 Yellow
12
+
C52 33uF
10V
+
C52 33uF
10V
12
C38
2.2uF
10%
25V
C38
2.2uF
10%
25V
+
C8 33uF
+
C8 33uF
12
J16 RED J16 RED
R2 820 R2 820
12
C53
.1uF
16V C53
.1uF
16V
+
C1 33uF
+
C1 33uF
12
L9 68 L9 68
12
L2 68 L2 68
12
J20 RED
+5V_IN
J20 RED
+5V_IN
+
C5 33uF
+
C5 33uF
12
C39 0.01uF C39 0.01uF
C6 1uF C6 1uF
12
C31
1uF
25V
C31
1uF
25V
12
C44
2.2uF
10%
25V
C44
2.2uF
10%
25V
C7 .1uF C7 .1uF
12
R17 30.1K R17 30.1K
12
J11 RED
3.3VD_IN
J11 RED
3.3VD_IN
U3
TPS79633DCQ
U3
TPS79633DCQ
EN
1
IN
2
GND
3
OUT 4
NR/FB 5
GND 6
C9
10uF
6.3V
C9
10uF
6.3V
12
C43 1uF 10%
25V
C43 1uF 10%
25V
D1 GREEN D1 GREEN
12
JP16
(SHORT 1-2)
JP16
(SHORT 1-2)
1 3
2
L8 68 L8 68
12
C57
10uF
6.3V
C57
10uF
6.3V
12
+
C14 22uF
+
C14 22uF
12
C36
10uF
6.3V
C36
10uF
6.3V
1 2
C2
10uF
6.3V
C2
10uF
6.3V
12
J12 BLK GND J12 BLK GND
L3
68
L3
68
12
C42 16pF C42 16pF
+
C35 33uF
10V
+
C35 33uF
10V
12
Physical Description www.ti.com
ADS5560/62EVM 18 SLAU260 – December 2008Submit Documentation Feedback

EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claimsarising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANYINDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents orservices described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. Thisnotice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/orsafety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the analog input voltage range of -0.3 V to AVDD + 0.3 V and the analog output voltage range of-0.3 V to DRVDD. AVDD and DRVDD voltage range is -0.3 V to 3.9 V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than 25 °C. The EVM is designed to operateproperly with certain components above 50 °C as long as the input and output ranges are maintained. These components include but arenot limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identifiedusing the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.
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