4.1.2 Clock Signal Generator
4.2 Coherent Input Frequency Selection
5 Physical Description
5.1 PCB Layout
Physical Description
www.ti.com
the performance of the source. Noise can be broken into two components, broadband noise and close-inphase noise. Broadband noise can be improved by the LC filter added to improve distortion performance.The close-in phase noise, however, typically cannot be improved by additional filtering. Therefore, whenselecting an analog signal source, it is important to review the manufacturer's phase noise plots and takecare to choose a signal generator with the best phase-noise performance.
Equally important in the high-performance ADC evaluation setup is the selection of the clocking source.Most modern ADCs accept either a sinusoidal or a square-wave clock input. The key metric in selecting aclocking source is selecting a source with the lowest jitter. This becomes increasingly important as theADC input frequency (Fin) increases, because the ADC SNR evaluation setups can become jitter-limited(To) as shown by the following equation.
SNR (dBc) = 20 log [2 π × Fin ×Tj(rms)]
In theory, a square-wave source with femtosecond jitter is ideal for an ADC evaluation setup. However, inpractical terms, most commercially available square-wave generators offer jitter measured in picoseconds,which is too great for high-resolution ADC evaluation setups. Therefore, most evaluation setups rely onthe ADC's internal clock buffer to convert a sinusoidal input signal into a ultralow-jitter square wave. Whenselecting a sinusoidal clocking source, it has been shown that phase noise has a direct impact on jitterperformance. Consequently, great scrutiny must be applied to the phase-noise performance of theclocking signal generator. TI has found that high-Q monolithic crystal filters can improve the phase noiseof the signal generator, and these filters become essential elements of the evaluation setup when highADC input frequencies are being evaluated.
Typical ADC analysis requires users to collect the resulting time-domain data and perform a Fouriertransform to analyze the data in the frequency domain. A stipulation of the Fourier transform is that thesignal must be continuous-time. However, this is impractical when looking at a finite set of ADC samples,usually collected from a logic analyzer. Consequently, users typically apply a window function to minimizethe time-domain discontinuities that arise when analyzing a finite set of samples. For ADC analysis,window functions have their own frequency signatures or lobes that distort both SNR and SFDRmeasurements of the ADC. TI uses the concept of coherent sampling to work around the use of a windowfunction. The central premise of coherent sampling entails that the input signal into the ADC is carefullychosen such that when a continuous-time signal is reconstructed from a finite sample set, no time-domaindiscontinuities exist. To achieve this, the input frequency must be an integer multiple of the ratio of theADC's sample rate (f
s
) and the number of samples collected from the logic analyzer (N
s
). The ratio of f
s
toN
s
is typically referred to as the fundamental frequency (f
f
). Determining the ADC input frequency is atwo-step process. First, users select the frequency of interest for evaluating the ADC; then, they divide thisby the fundamental frequency. This typically yields a noninteger value, which must be rounded to thenearest odd, preferably prime, integer. Once that integer, or frequency bin (f
bin
), has been determined,users multiply this with the fundamental frequency to obtain a coherent frequency to program into theirADC input signal generator. The procedure is summarized as follows.f
f
= f
s
/N
sf
bin
= Odd_round(f
desired
/f
f
)Coherent frequency = f
f
×f
bin
This section describes the physical characteristics and PCB layout of the EVM.
The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers areshown in Figure 3 through Figure 6 . The layout features a split ground plane; however, similarperformance can be had with a careful layout using a common ground plane.
8ADS5560/62EVM SLAU260 – December 2008Submit Documentation Feedback
