Texas Instruments BQ25616 User manual

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BQ25616, BQ25616J BMS026 Evaluation Module
User's Guide
SLUUC73–March 2020
BQ25616, BQ25616J BMS026 Evaluation Module
This user's guide provides detailed testing instructions for the BQ25616 and BQ25616J evaluation
modules (EVM). Also included are descriptions of the necessary equipment, equipment setup, and
procedures. The reference documentation also contains the printed-circuit board layouts, schematics, and
the bill of materials (BOM).
Throughout this user's guide, the abbreviations EVM,BQ25616EVM, BQ25616JEVM, BMS026, and the
term evaluation module are synonymous with the BMS026 evaluation module, unless otherwise noted.
Contents
1 Introduction ................................................................................................................... 2
1.1 EVM Features....................................................................................................... 2
1.2 I/O Descriptions..................................................................................................... 2
2 Test Summary................................................................................................................ 4
2.1 Equipment ........................................................................................................... 4
2.2 Equipment Setup.................................................................................................... 4
2.3 Test Procedure...................................................................................................... 5
3 PCB Layout Guideline....................................................................................................... 7
4 Board Layout ................................................................................................................. 8
5 Schematic ................................................................................................................... 12
6 Bill of Materials ............................................................................................................. 14
List of Figures
1 Original Test Setup for BMS026 EVM .................................................................................... 4
2 BMS026 EVM Top Overlay................................................................................................. 8
3 BMS026 EVM Top Solder Mask........................................................................................... 8
4 BMS026 EVM Top Layer .................................................................................................. 8
5 BMS026 EVM Signal Layer 1 ............................................................................................. 8
6 BMS026 EVM Signal Layer 2 ............................................................................................. 9
7 BMS026 EVM Bottom Layer .............................................................................................. 9
8 BMS026 Bottom Solder Mask ............................................................................................ 10
9 BMS026 Bottom Overlay.................................................................................................. 10
10 BQ25616EVM Schematic ................................................................................................ 12
11 BQ25616JEVM Schematic................................................................................................ 13
List of Tables
1 Device Data Sheets ......................................................................................................... 2
2 EVM I/O Connections ....................................................................................................... 2
3 EVM Jumper, Shunt and Switch Installation ............................................................................. 2
4 Recommended Operating Conditions..................................................................................... 3
5 BQ25616EVM Bill of Materials .......................................................................................... 14
6 BQ25616JEVM Bill of Materials.......................................................................................... 18
Trademarks
All trademarks are the property of their respective owners.

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1 Introduction
1.1 EVM Features
For detailed features and operation, refer to Table 1 for a list of devices and their data sheets.
Table 1. Device Data Sheets
Device Data Sheet EVM Label Variant
BQ25616 SLUSDF7 BQ25616EVM 001
BQ25616J SLUSDF7 BQ25616JEVM 002
The BMS026 evaluation module (EVM) is a complete charger module for evaluating the standalone single-
cell NVDC charger using any of the devices above.
This EVM features adjustable input current limit, charging current, and charging voltage. It also has the
abilty to test the D+/D- input source type detection, external input over-voltage protection, and simulate
battery high and low temperature conditions.
1.2 I/O Descriptions
Table 2 lists the input and output connections available on this EVM and their respective descriptions.
Table 2. EVM I/O Connections
Jack Description
J1(2) – VAC Positive rail of the charger input voltage
J1(1) – GND Ground
J2(1) – SYSTEM Positive rail of the charger system output voltage, typically connected to the
system load
J2(2) – GND Ground
J3(1) – PMID Positive rail of the charger output voltage for power bank applications in
reverse boost mode (OTG). This output also shares the rail with the VIN
input rail in forward buck mode
J3(2) – GND Ground
J4 Input source Micro B USB port
J5-BATSNS_ICHG BATSNS or ICHG pin connection
J5(3) – ICHG ICHG pin external connection
J5(2) – BATTERY Positive rail of the charger battery input, connected to the positive terminal of
the external battery
J5(1) – GND Ground
J6 USB2ANY 10-pin connector
J7 I2C 4-pin connector for the EV2300/2400 interface board
Table 3 lists the jumepr, shunt and switch installations available on this EVM and their respective
descriptions.
Table 3. EVM Jumper, Shunt and Switch Installation
Jack Description BQ25616 Setting BQ25616J Setting
JP1 VBUS additional capacitance connection Not Installed Not Installed
JP2 SYS additional capacitance connection Not Installed Not Installed
JP3 PMID additional capacitance connection Not Installed Not Installed
JP4 BAT additional capacitance connection Not Installed Not Installed
JP5 I/O Pullup rail selection. Selection will have
either BAT or SYS as the pullup rail for /CE,
STAT, OTG, and /PG pins
Short PULLUP to
SYS Short PULLUP to SYS

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Table 3. EVM Jumper, Shunt and Switch Installation (continued)
Jack Description BQ25616 Setting BQ25616J Setting
JP6 Micro B USB input D+ connection to charger
D+ pin Installed Installed
JP7 ICHG to BAT or BATTERY connection Not Installed Not Installed
JP8 ICHG resistor setting connection. Must be
connected for charging to operate correctly. Installed Installed
JP9 Micro B USB input D+ connection to charger
D+ pin Installed Installed
JP10 PSEL pin input current selection. Connect this
to HIGH on PSEL enabled chargers to select
500mA default input current limit. Connect
this to LOW on PSEL enabled chargers to
select 2.4-A default input current limit
Not Installed Not Installed
JP11 REGN connection to TS network. Must be
connected for thermistor sensing to operate
correctly.
Installed Installed
JP12 ILIM resistor setting connection. Must be
connected for ‘Unknown Adapter’ input
current limiting to operate correctly.
Installed Installed
JP13 STAT pin LED indicator connection. This
indicates the current charger Status Installed Installed
JP14 /PG pin LED indicator connection. On /PG
enabled chargers, this indicates the Power
Good status
Installed Installed
JP15 ICHG, ILIM, AGND header connection point. Not Installed Not Installed
JP16 Thermistor NORMAL temperature setting.
Connect jumper to simulate charger entering
TNORMAL (T2-T3) temperature region.
Installed Installed
JP17 /CE pin connection to ground to enable
charging. When removed, /CE pin will pull up
to disable charge
Installed Installed
JP18 Thermistor HOT temperature setting. Connect
jumper to simulate charger entering THOT
(>T5) temperature region.
Not Installed Not Installed
JP19 D- to /PG rail connection Not Installed Not Installed
JP20 OTG pin connection to ground to disable OTG
boost mode. When removed, OTG boost
mode is enabled only in battery-only
operation
Installed Installed
JP21 VSET pin setting connection. Leave floating
to set VBATREG to 4.208V. Connect to 10-
kOhm to ground to set VBATREG to 4.100V.
Connect to ground directly to set VBATREG
to 4.352V
Not Installed Not Installed
S1 /QON pin pull-down. No function. Not Populated Not Populated
S2 STAT and /PG LED bypass switches 1-4: Open, 2-3: Open 1-4: Open, 2-3: Open
Table 4 lists the recommended operating conditions for this EVM.
Table 4. Recommended Operating Conditions
Symbol Description MIN TYP MAX Unit
VVBUS,VVAC Input voltage applied to VAC and VBUS pins 4.0 13.5 V
VBAT Battery voltage applied to BAT pin 4.35 V
IVBUS Input current into VBUS 3.2 A
ISW Output current (SW) 3.2 A
IBAT Fast charging current 3.0 A
RMS Discharging current through internal
BATFET 6.0 A

Load #1
V
V
+
-
+
-
V
+
-
Power Supply
#1 V
+
-
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2 Test Summary
2.1 Equipment
This section includes a list of supplies required for testing this EVM.
1. Power Supplies: Power supply #1 (PS1): A power supply capable of supplying 5 V at 3 A is required.
While this part can handle larger voltage and current, it is not necessary for this procedure.
2. Loads: Load #1 (4-Quadrant Supply, Constant Voltage < 4.5 V): A "Kepco" Load, BOP, 20-5M, DC 0
to ±20 V, 0 to ±5 A (or higher)
Alternative Option: A 0-20V/0-5A >30-W DC electronic load set in a constant voltage loading mode.
Load #2 (Electronic or Resistive Load): 10 Ω, 5 W (or higher)
3. Meters: (6x) "Fluke 75" multi-meters, (equivalent or better).
Alternative Option: (4x) equivalent voltage meters and (2x) equivalent current meters. The current
meters must be capable of measuring at least 5-A.
2.2 Equipment Setup
Use the following instructions to set up the equipment:
1. Review EVM connections in Table 2.
2. Set PS1 for 5-V DC, 3-A current limit and then turn off the supply.
3. Connect the output of PS1 in series with a current meter to J1 (VAC and GND).
4. Connect a voltage meter across TP7 (VBUS) and TP25 (PGND), or across J1.
5. Turn on Load #1, set to constant voltage mode, and output to 3.7-V. Disable Load. Connect Load in
series with a current meter (multimeter), ground side, to J5 (BATTERY and GND) as shown in
Figure 1.
6. Connect one voltage meter across TP15 (BAT) and TP24 (PGND), or across J4-2 and J4-1 as shown
in Figure 1.
7. Connect one voltage meter across TP14 (SYS) and TP24 (PGND), or across J2-1 and J2-2 as shown
in Figure 1.
8. Install shunts as shown in Table 3.
Figure 1. Original Test Setup for BMS026 EVM

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2.3 Test Procedure
2.3.1 Initial Settings
1. Ensure Section 2.2 steps have been followed.
2. Adjust R22 potentiometer to increase input current limit to the maximum value. To do this, turn R22
clockwise until a click is heard.
3. Turn on PS1
• Measure →VSYS (SYS-TP14 and PGND-TP24) = 4.20V±0.3V
NOTE: Completely disconnect Load #1 from BAT pin if different voltage value is seen.
2.3.2 Charge Mode Verification
1. PS1 should be on from Section 2.3.1.
2. Enable Load #1.
3. Adjust R12 potentiometer to increase the charge current limit to 1A
• Measure →IBAT (current into Load #1) = 1.0A±25mA
• Record IBAT measurement
4. Change Load #1 to 2.5V
• Measure →VSYS (SYS-TP14 and PGND-TP24) = 3.65V±0.3V
• Measure →IBAT (current into Load #1) = 5% of previous IBAT result ≈50mA±15mA
2.3.3 Boost Mode Verification
1. Turn off and disconnect PS1.
2. Set Load #1 to 3.7V and 2A current limit.
NOTE: If Load #1 connected from BATTERY-J5(2) to PGND-J5(1) is not a four quadrant supply,
remove Load #1 and use PS1 (disconnected previously), set to 3.7V, 2A current limit and
connect across BATTERY-J5(2) to PGND-J5(1).
3. Remove shunt JP20 to enable boost mode.
4. Connect Load #2 across VAC-J1(2) and GND-J1(1).
• Measure →VBUS (VBUS-TP7 and PGND-TP25) = 5.0V±0.2V
5. Turn off and disconnect power supply.
6. Remove Load #2 from connection.
7. Reconnect shunt JP20.
2.3.4 Helpful Tips
• The leads and cables to the various power supplies, batteries and loads have resistance. The current
meters also have series resistance. The charger dynamically reduces charge current depending on the
voltage sensed at its VAC/VBUS pin (using the VINDPM feature), BAT pin (as part of normal
termination), and TS pin (through its battery temperature monitoring feature via battery thermistor).
Therefore, voltmeters must be used to measure the voltage as close to the IC pins as possible instead
of relying on the digital readouts of the power supply. If a battery thermistor is not available, make sure
shunt jp16 is in place.
• When using a source meter that can source and sink current as your battery simulator, TI highly
recommends adding a large (1000+ μF) capacitor at the EVM BATTERY and GND connectors in order
to prevent oscillations at the BAT pin due to mismatched impedances of the charger output and source
meter input within their respective regulation loop bandwidths.
Configuring the source meter for 4-wire sensing eliminates the need for a separate voltmeter to

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measure the voltage at the BAT pin. When using 4-wire sensing, always ensure that the sensing leads
are connected in order to prevent accidental overvoltage by the power leads
• For precise measurements of input and output currents, especially battery charging current regulation
near termination, the current meter in series with the battery or battery simulator should not be set to
auto-range and may need be removed entirely. An alternate method for measuring charge current is to
either use an oscilloscope with hall effect current probe or by a differential voltage measurement
across the relevant sensing resistors populated on the BMS026 EVM.

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3 PCB Layout Guideline
Minimize the switching node rise and fall times for minimum switching loss. Proper layout of the
components minimizing high-frequency current path loop is important to prevent electrical and magnetic
field radiation and high-frequency resonant problems. This PCB layout priority list must be followed in the
order presented for proper layout:
1. Place the input capacitor as close as possible to the PMID pin and PGND pin connections and use the
shortest copper trace connection or PGND plane.
2. Place the inductor input terminal as close to the SW pin as possible. Minimize the copper area of this
trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the
charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
3. Put an output capacitor near to the inductor and the IC. Tie ground connections to the IC ground with a
short copper trace connection or PGND plane.
4. Route and connect analog ground (AGND) separately from the power ground (PGND).Connect AGND
and PGND together using a power pad as the single ground connection point or use a 0-Ωresistor to
tie.
5. Use a single ground connection to tie PGND to the charger ANGD just beneath the IC. Use ground
copper pour but avoid power pins to reduce inductive and capacitive noise coupling.
6. Place decoupling capacitors next to the IC pins and make the trace connection as short as possible.
7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB
ground. Ensure that there are sufficient thermal vias directly under the IC connecting to the ground
plane on the other layers.
8. The via size and number should be enough for a given current path.
See the EVM design for the recommended component placement with trace and via locations. For the
QFN information, see Quad Flatpack No-Lead Logic Packages and QFN/SON PCB Attachment.

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4 Board Layout
Figure 2 through Figure 9 show the EVM PCB layout images.
Figure 2. BMS026 EVM Top Overlay Figure 3. BMS026 EVM Top Solder Mask

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Figure 4. BMS026 EVM Top Layer Figure 5. BMS026 EVM Signal Layer 1

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Figure 6. BMS026 EVM Signal Layer 2 Figure 7. BMS026 EVM Bottom Layer