Texas Instruments TPSM63608 User manual

User’s Guide
TPSM63610 36-V, 8-A Buck Regulator Evaluation Module
User's Guide
ABSTRACT
With an input operating voltage range from 3 V to 36 V and rated output current from 6 A to 8 A, the TPSM63608
and TPSM63610 family of synchronous buck power modules provides flexibility, scalability, and optimized
solution size for a wide range of applications. With integrated power MOSFETs, buck inductor and PWM
controller, these modules enable DC/DC solutions with high density, low EMI, and increased flexibility. Available
EMI mitigation features include dual random spread spectrum (DRSS), RBOOT-configured switch-node slew
rate control, and integrated input bypass capacitors.
Table 1-1. TPSM63608 and TPSM63610 Synchronous Buck DC/DC Power Module Family
DC/DC MODULE RATED IOUT PACKAGE DIMENSIONS FEATURES EMI MITIGATION
TPSM63608 6 A B3-QFN (22) 6.5 mm × 7.5 mm RT adjustable FSW,
external synchronization
DRSS, slew-rate control, integrated
input, VCC and BOOT capacitors
TPSM63610 8 A
The TPSM63610EVM uses the TPSM63610 easy-to-use synchronous buck module IC with a wide output
voltage range of 1 V to 20 V and an output current up to 8 A. The default output voltage of the EVM is set to 5 V
can be adjusted to 3.3 V through a jumper setting.
The solution supports adjustable input voltage UVLO for application-specific power-up and power-down
requirements, external clock synchronization to mitigate beat frequencies in noise-sensitive applications,
PGOOD indicator for sequencing and output voltage monitoring, pin-selectable spread spectrum control for
EMI mitigation, and pin selectable MODE control for light-load performance with AUTO mode or fixed switching
frequency with FPWM mode.
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Table of Contents
1 High-Density EVM Description.............................................................................................................................................. 4
1.1 Typical Applications............................................................................................................................................................4
2 Test Setup and Procedure......................................................................................................................................................5
2.1 EVM Connections.............................................................................................................................................................. 5
2.2 EVM Setup......................................................................................................................................................................... 6
2.3 Test Equipment.................................................................................................................................................................. 7
2.4 Recommended Test Setup.................................................................................................................................................7
2.5 Test Procedure................................................................................................................................................................... 7
3 Test Data and Performance Curves...................................................................................................................................... 8
3.1 Efficiency and Load Regulation Performance.................................................................................................................... 8
3.2 Waveforms....................................................................................................................................................................... 10
3.3 Bode Plot..........................................................................................................................................................................11
3.4 EMI Performance............................................................................................................................................................. 13
4 EVM Documentation.............................................................................................................................................................14
4.1 Schematic........................................................................................................................................................................ 14
4.2 Bill of Materials.................................................................................................................................................................15
4.3 PCB Layout...................................................................................................................................................................... 17
4.4 Multi-Layer Stackup......................................................................................................................................................... 19
5 Device and Documentation Support...................................................................................................................................20
5.1 Device Support.................................................................................................................................................................20
5.2 Documentation Support................................................................................................................................................... 20
6 Revision History................................................................................................................................................................... 21
List of Figures
Figure 2-1. EVM Test Setup.........................................................................................................................................................5
Figure 3-1. Efficiency, VOUT = 5 V, FSW = 1 MHz, FPWM Mode.................................................................................................. 8
Figure 3-2. Efficiency, VOUT = 5 V, FSW = 1 MHz, AUTO Mode................................................................................................... 8
Figure 3-3. Load Regulation, VOUT = 5 V, FSW = 1 MHz, FPWM Mode.......................................................................................8
Figure 3-4. Load Regulation, VOUT = 5 V, FSW = 1 MHz, AUTO Mode........................................................................................ 8
Figure 3-5. Efficiency, VOUT = 3.3 V, FSW = 1 MHz, FPWM Mode............................................................................................... 8
Figure 3-6. Efficiency, VOUT = 3.3 V, FSW = 1 MHz, AUTO Mode................................................................................................ 8
Figure 3-7. Load Regulation, VOUT = 3.3 V, FSW = 1 MHz, FPWM Mode....................................................................................9
Figure 3-8. Load Regulation, VOUT = 3.3 V, FSW = 1 MHz, AUTO Mode.....................................................................................9
Figure 3-9. Start-Up to VIN = 24 V............................................................................................................................................. 10
Figure 3-10. Shutdown ............................................................................................................................................................. 10
Figure 3-11. Enable ON and OFF .............................................................................................................................................10
Figure 3-12. Load Transient, 4 A to 8 A at 1 A/µs......................................................................................................................10
Figure 3-13. Infrared Thermal Image VIN = 12 V, VOUT = 5 V....................................................................................................10
Figure 3-14. Infrared Thermal Image VIN = 24 V, VOUT = 5 V....................................................................................................10
Figure 3-15. Infrared Thermal Image VIN = 12 V, VOUT = 3.3 V................................................................................................. 11
Figure 3-16. Infrared Thermal Image VIN = 24 V, VOUT = 3.3 V................................................................................................. 11
Figure 3-17. Bode Plot With Four 47-µF, 16-V Output Capacitors (110 µF Effective at 5 VDC, 25°C)...................................... 11
Figure 3-18. Output Capacitor Voltage Derating Curve............................................................................................................. 12
Figure 3-19. CISPR 11/32 Class B Conducted Emissions: VIN = 24 V, SPSP ON.................................................................... 13
Figure 3-20. CISPR 11 Class B Radiated Emissions: VIN = 24 V, SPSP ON............................................................................ 13
Figure 4-1. EVM Schematic.......................................................................................................................................................14
Figure 4-2. 3D Top View............................................................................................................................................................ 17
Figure 4-3. 3D Bottom View.......................................................................................................................................................17
Figure 4-4. Top Layer Copper....................................................................................................................................................18
Figure 4-5. Layer 2 Copper........................................................................................................................................................18
Figure 4-6. Layer 3 Copper........................................................................................................................................................19
Figure 4-7. Bottom Layer Copper (Viewed From Top)...............................................................................................................19
Figure 4-8. Layer Stackup......................................................................................................................................................... 19
List of Tables
Table 1-1. TPSM63608 and TPSM63610 Synchronous Buck DC/DC Power Module Family..................................................... 1
Table 2-1. EVM Power Connections............................................................................................................................................ 5
Table 2-2. EVM Signal Connections............................................................................................................................................ 5
Table 4-1. Component BOM...................................................................................................................................................... 15
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Trademarks
HotRod™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
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1 High-Density EVM Description
The TPSM63610EVM features the TPSM63610 synchronous buck power module configured for operation with
typical 3-V to 36-V input bus applications. This wide-VIN range DC/DC solution offers outsized voltage rating and
operating margin to withstand supply-rail voltage transients.
The output voltage can be set to either 3.3 V or 5 V and switching frequency can each be set to one of five
popular values (400 kHz, 700 kHz, 1 MHz, 1.4 MHz, and 2.2 MHz) by using configuration jumpers. Additionally,
a resistor placeholder footprint is on the backside of the EVM to allow adjustment of the switching frequency
outside of the five jumper settings.
The EVM provides the full 8-A output current rating of the device. The selected input and output capacitors
accommodate the entire range of input voltage and the selectable output voltages on the EVM and are available
from multiple component vendors. Input and output voltage sense terminals and a test point header facilitate
measurement of the following:
• Efficiency and power dissipation
• Line and load regulation
• Load transient response
• Enable ON, OFF
• Bode plot (crossover frequency and phase margin)
The header also provides connections for features such as remote enable (EN), external clock synchronization
through mode pin (MODE), power-good monitor (PGOOD), spread-spectrum frequency modulation (SPSP)
and AUTO/FPWM mode control (MODE). The recommended PCB layout maximizes thermal performance and
minimizes output ripple and noise.
A 0-Ω resistor is placed between RBOOT and CBOOT to short the internal 100-Ω resistor for highest
efficiency. Modifying the 0-Ω resistor allows adjustment of the internal resistance to balance EMI and efficiency
performance.
1.1 Typical Applications
•Test and measurement, aerospace and defense
•Factory automation and control, power delivery
•Inverting buck-boost (IBB) circuits requiring negative output voltage
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2 Test Setup and Procedure
2.1 EVM Connections
Referencing the EVM connections described in Table 2-1, use the recommended test setup in Figure 2-1
to evaluate the TPSM63610. Working at an ESD-protected workstation, make sure that any wrist straps,
bootstraps, or mats are connected and referencing the user to earth ground before power is applied to the
EVM.
ACOM
Ammeter 1 Electronic Load
+ -
V
Voltmeter 1
COM V
Voltmeter 2
COM
Oscilloscope
+
Power Supply
ACOM
Ammeter 2
-
Figure 2-1. EVM Test Setup
SPACER
Table 2-1. EVM Power Connections
LABEL DESCRIPTION
VIN+ Positive input power connection
VIN– Negative input power connection
VOUT+ Positive output power connection
VOUT– Negative output power connection
Table 2-2. EVM Signal Connections
LABEL DESCRIPTION
VIN S+ Positive input sense terminal. Connect the multimeter positive lead for measuring efficiency.
VIN S– Negative input sense terminal. Connect a multimeter negative lead for measuring efficiency.
VOUT S+ Positive output sense terminal. Connect a multimeter positive lead for measuring efficiency and line and load regulation.
VOUT S– Negative output sense terminal. Connect the multimeter negative lead for measuring efficiency and line and load
regulation.
GND Ground reference point
SW Switch node monitor output
EN Precision enable input and input voltage UVLO protection. Tie EN to GND to disable the regulator. Use a logic signal to
control EN for remote ON/OFF functionality. Leave EN open for UVLO turn-on thresholds set at 6 V.
MODE Mode select and synchronization input. For synchronization, connect a valid clock signal to synchronize the switching
frequency from 200 kHz to 2.2 MHz. Connect MODE to VCC for FPWM mode. Connect MODE to GND for AUTO mode.
PG Power-good monitor output. PG is an open-drain flag with a 100-kΩ pullup resistor to VOUT.
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Table 2-2. EVM Signal Connections (continued)
LABEL DESCRIPTION
SPSP
Spread spectrum control. Connect SPSP to GND to disable spread spectrum. Connect SPSP to VCC to enable spread
spectrum. Leave SPSP floating to enable spread spectrum with ripple cancellation. Power cycle the device when changing
the spread spectrum configuration.
CHA, CHB
Bode plot measurement and signal injection. A 10-Ω resistor from CHA to CHB facilitates oscillator signal injection for bode
plot measurement. Remove the jumper and apply a swept-frequency signal between CHA and CHB while measuring the
respective response at each terminal for loop gain measurement.
2.2 EVM Setup
• Use the VIN S+ and VIN S– test points along with the VOUT S+ and VOUT S– test points located near the
power terminal blocks as voltage monitoring points where voltmeters are connected to measure the input and
output voltages, respectively. Do not use these sense terminals as the input supply or output load connection
points. The PCB traces connected to these sense terminals are not designed to support high currents.
• Header J3 provides access to the following test points:
– VIN
– EN
– MODE
– PG
– VCC
– SPSP
The MODE test point provides a convenient location to connect an external clock signal. The power-good
(PG) test point is available to monitor when a valid output voltage is present on the EVM. Refer to EVM
Connections for specific information related to the various test points.
• The VOUT SELECT header (J4) allows selection of either 3.3 V or 5 V. Before applying power to the EVM,
make sure that the jumper is present and properly positioned for the intended output voltage. Always remove
input power before changing the jumper settings.
• The FSW SELECT header (J5) allows selection of a suitable switching frequency:
– 400 kHz
– 700 kHz
– 1 MHz
– 1.4 MHz
– 2.2 MHz
Before applying power to the EVM, make sure that the jumper is present and properly positioned for the
intended switching frequency. Always remove input power before changing the jumper settings.
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2.3 Test Equipment
Voltage Source: The input voltage source VIN must be a 36-V variable DC source capable of supplying 6 A.
Multimeters:
•Voltmeter 1: Measure the input voltage at VIN S+ to VIN S–.
•Voltmeter 2: Measure the output voltage at VOUT S+ to VOUT S–.
•Ammeter 1: Measure the input current. Set the ammeter to 1-second aperture time.
•Ammeter 2: Measure the output current. Set the ammeter to 1-second aperture time.
Electronic Load: Use an electronic load set to constant-resistance (CR) or constant-current (CC) mode and
capable of 0 ADC to 6 ADC. For a no-load input current measurement, disconnect the electronic load as it can
draw a small residual current.
Oscilloscope: With the scope set to 20-MHz bandwidth and AC coupling, measure the output voltage ripple
directly across an output capacitor with a short ground lead normally provided with the scope probe. Place the
oscilloscope probe tip on the positive terminal of the output capacitor, holding the ground barrel of the probe
through the ground lead to the negative terminal of the capacitor. TI does not recommend using a long-leaded
ground connection because this may induce additional noise given a large ground loop. To measure other
waveforms, adjust the oscilloscope as needed.
Safety: Always use caution when touching any circuits that can be live or energized.
2.4 Recommended Test Setup
2.4.1 Input Connections
• Prior to connecting the DC input source, set the current limit of the input supply to 0.1-A maximum. Ensure
the input source is initially set to 0 V and connected to the VIN+ and VIN– connection points as shown in
Figure 2-1.
• Connect voltmeter 1 at VIN S+ and VIN S– connection points to measure the input voltage.
• Connect ammeter 1 to measure the input current and set it to at least a 0.1-second aperture time.
2.4.2 Output Connections
• Connect an electronic load to the VOUT+ and VOUT– connections as shown in Figure 2-1. Set the load to
constant-resistance mode or constant-current mode at 0 A before applying input voltage.
• Connect voltmeter 2 at VOUT S+ and VOUT S– sense points to measure the output voltage.
• Connect ammeter 2 to measure the output current.
2.5 Test Procedure
2.5.1 Line, Load Regulation and Efficiency
• Set up the EVM as described in Test Setup and Procedure.
• Set load to constant resistance or constant current mode to sink 0 A.
• Increase the input source voltage from 0 V to 24 V; use voltmeter 1 to measure the input voltage.
• Increase the current limit of the input supply to 8 A.
• Use voltmeter 2 to measure the output voltage, VOUT, and vary the load current from 0 A to 8 A DC; VOUT
must remain within the load regulation specification.
• Set the load current to 4 A (50% rated load) and vary the input source voltage from 6 V to 36 V; VOUT must
remain within the line regulation specification.
• Set the load current to 8 A (100% rated load) and measure the efficiency at typical input voltages (12 V, 24 V,
and 36 V).
• Decrease the load to 0 A. Decrease the input source voltage to 0 V.
CAUTION
Extended operation at high output current can raise component temperatures above 55°C. To
avoid risk of a burn injury, do not touch the components until they have cooled sufficiently after
disconnecting power.
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3 Test Data and Performance Curves
Because actual performance data can be affected by measurement techniques and environmental variables,
these curves are presented for reference and can differ from actual field measurements. Unless otherwise
indicated, VIN = 24 V, VOUT = 5 V, IOUT = 8 A, and FSW = 1 MHz.
3.1 Efficiency and Load Regulation Performance
This section provides efficiency and load regulation plots for the EVM.
Output Current (A)
Efficiency (%)
0 1 2 3 4 5 6 7 8
70
75
80
85
90
95
100
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-1. Efficiency, VOUT = 5 V, FSW = 1 MHz,
FPWM Mode
Output Current (A)
Efficiency (%)
0 1 2 3 4 5 6 7 8
70
75
80
85
90
95
100
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-2. Efficiency, VOUT = 5 V, FSW = 1 MHz,
AUTO Mode
Output Current (A)
Output Voltage (V)
0 1 2 3 4 5 6 7 8
4.95
4.975
5
5.025
5.05
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-3. Load Regulation, VOUT = 5 V, FSW = 1
MHz, FPWM Mode
Output Current (A)
Output Voltage (V)
0 1 2 3 4 5 6 7 8
4.95
4.975
5
5.025
5.05
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-4. Load Regulation, VOUT = 5 V, FSW = 1
MHz, AUTO Mode
Output Current (A)
Efficiency (%)
0 1 2 3 4 5 6 7 8
70
75
80
85
90
95
100
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-5. Efficiency, VOUT = 3.3 V, FSW = 1 MHz,
FPWM Mode
Output Current (A)
Efficiency (%)
0 1 2 3 4 5 6 7 8
70
75
80
85
90
95
100
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-6. Efficiency, VOUT = 3.3 V, FSW = 1 MHz,
AUTO Mode
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Output Current (A)
Output Voltage (V)
0 1 2 3 4 5 6 7 8
3.255
3.27
3.285
3.3
3.315
3.33
3.345
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-7. Load Regulation, VOUT = 3.3 V, FSW = 1
MHz, FPWM Mode
Output Current (A)
Output Voltage (V)
0 1 2 3 4 5 6 7 8
3.255
3.27
3.285
3.3
3.315
3.33
3.345
VIN = 12 V
VIN = 24 V
VIN = 36 V
Figure 3-8. Load Regulation, VOUT = 3.3 V, FSW = 1
MHz, AUTO Mode
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3.2 Waveforms
CH 1 ( VIN )
CH 2 ( VOUT )
CH 3 ( PG )
Figure 3-9. Start-Up to VIN = 24 V Figure 3-10. Shutdown
Figure 3-11. Enable ON and OFF
CH 3 ( VOUT )
CH 4 ( IOUT )
Figure 3-12. Load Transient, 4 A to 8 A at 1 A/µs
FSW = 1 MHz IOUT = 8 A PDIS = 3.49 W
Figure 3-13. Infrared Thermal Image VIN = 12 V,
VOUT = 5 V
FSW = 1 MHz IOUT = 8 A PDIS = 4.06 W
Figure 3-14. Infrared Thermal Image VIN = 24 V,
VOUT = 5 V
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FSW = 1 MHz IOUT = 8 A PDIS = 3.27 W
Figure 3-15. Infrared Thermal Image VIN = 12 V,
VOUT = 3.3 V
FSW = 1 MHz IOUT = 8 A PDIS = 3.84 W
Figure 3-16. Infrared Thermal Image VIN = 24 V,
VOUT = 3.3 V
3.3 Bode Plot
Figure 3-17 provides the bode plot at VIN = 24 V, VOUT = 5 V, FSW = 1 MHz, and IOUT = 8 A. Figure 3-18 shows
a typical capacitance versus voltage curve for a 47-µF, 16-V, X6S output capacitor to highlight the effective
capacitance value of a ceramic. See component details in Bill of Materials.
Figure 3-17. Bode Plot With Four 47-µF, 16-V Output Capacitors (110 µF Effective at 5 VDC, 25°C)
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DC Bias (V)
Effective Capacitance (µF)
Figure 3-18. Output Capacitor Voltage Derating Curve
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3.4 EMI Performance
See the Schematic and Bill of Materials for details of the input EMI filter to pass CISPR 11/32 Class B conducted
emissions.
Frequency (MHz)
Magnitude (dBµV)
0.1 0.2 0.3 0.5 0.7 1 2 3 4 5 6 78 10 20 3030
-15
0
15
30
45
60
75
CISPR 11/32 Class B QP detector
CISPR 11/32 Class B AVG detector
Evaluation Board
Default EVM VOUT = 5 V FSW = 1 MHz
Figure 3-19. CISPR 11/32 Class B Conducted
Emissions: VIN = 24 V, SPSP ON
Frequency (MHz)
Magnitude (dBµV/m)
0 100 200 300 400 500 600 700 800 900 1000
0
5
10
15
20
25
30
35
40
45
50
CISPR11 Class B Limit
Evaluation Board (Horizontal)
Evaluation Board (Vertical)
Additional 2 × 10
pF CIN with EMI
filter removed
VOUT = 5 V FSW = 1 MHz
Figure 3-20. CISPR 11 Class B Radiated
Emissions: VIN = 24 V, SPSP ON
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4 EVM Documentation
4.1 Schematic
Figure 4-1 illustrates the EVM schematic.
Figure 4-1. EVM Schematic
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4.2 Bill of Materials
Table 4-1. Component BOM
REF DES QTY VALUE DESCRIPTION PACKAGE PART NUMBER MANUFACTURER
C1 1 100 µF CAP, AL, 100 µF, 50 V, 0.34 Ω, 8x10 UUD1H101MNL1GS Nichicon
C2, C3, C4, C5 4 10 µF CAP, CERM, 10 µF, 50 V, X7R 1210 GRM32ER71H106KA12L MuRata
C6, C7, C8, C9 4 2.2 µF CAP, CERM, 2.2 µF, 50 V, X7R 0805 CGA4J3X7R1H225K125AB TDK
C10, C11, C12, C13 4 47 µF CAP, CERM, 47 µF, 16 V, X6S 1210 GRM32EC81C476ME15L MuRata
C14 1 0.1 µF CAP, CERM, 0.1 µF, 25 V, X7R 0603 CGA3E2X7R1E104K080AA TDK
C15 1 1 µF CAP, CERM, 1 µF, 25 V, X7R 0603 C0603C105K3RACTU Kemet
C16 1 0.1 µF CAP, CERM, 0.1 µF, 50 V, X7R 0402 CGA2B3X7R1H104K050BB TDK
C17 1 0.15 µF CAP, CERM, 0.15 µF, 50 V, X7R 0603 CGA3E3X7R1H154K080AB TDK
C18 0 10 pF CAP, CERM, 10 pF, 50 V, C0G/NP0 0402 CGA2B2C0G1H100D050BA TDK
H1, H2, H3, H4 4 Standoff, Hex, 0.5"L #4-40 Nylon - 1902C Keystone
H5, H6, H7, H8 4 Screw, Pan Head , 4-40, 3/8", Nylon - NY PMS 440 0038 PH B&F Fastener Supply
J1, J2 2 TERM BLOCK 2POS 5mm, TH - 1729018 Phoenix Contact
J3 1 Header, 100mil, 10 × 1, Gold, TH - TSW-110-07-G-S Samtec
J4 1 Header, 100mil, 2 × 1, Gold, TH - PBC02SAAN Sullins Connector Solutions
J5 1 Header, 100mil, 5 × 2, Tin, TH - PEC05DAAN Sullins Connector Solutions
J6 1 Header, 100mil, 3 × 1, Gold, TH - PBC03SAAN Sullins Connector Solutions
L1 1 1.5 µH Shielded power inductor 1.5 µH, 10.2A 10.5 mΩ Max - XGL4030-152MEC Coilcraft
R1 1 0 RES, 0, 5%, 0.1 W 0603 CRCW06030000Z0EA Vishay-Dale
R2 1 0 RES, 0, 0%, 0.2 W 0402 CRCW04020000Z0EDHP Vishay-Dale
R3 1 187 kΩ RES, 187 kΩ, 1%, 0.1 W 0603 CRCW0603187KFKEA Vishay-Dale
R4 1 49.9 kΩ RES, 49.9 kΩ, 1%, 0.1 W 0603 CRCW060349K9FKEA Vishay-Dale
R5 1 10 Ω RES, 10.0 Ω, 1%, 0.063 W 0402 CRCW040210R0FKED Vishay-Dale
R6 1 100 kΩ RES, 100 kΩ, 1%, 0.1 W 0603 CRCW0603100KFKEA Vishay-Dale
R7 1 100 kΩ RES, 100 kΩ, 1%, 0.063 W 0402 CRCW0402100KFKED Vishay-Dale
R8 1 43.2 kΩ RES, 43.2 kΩ, 1%, 0.063 W 0402 CRCW040243K2FKED Vishay-Dale
R9 1 59.0 kΩ RES, 59.0 kΩ, 1%, 0.063 W 0402 CRCW040259K0FKED Vishay-Dale
R10 1 40.2 kΩ RES, 40.2 kΩ, 1%, 0.063 W 0402 CRCW040240K2FKED Vishay-Dale
R11 1 22.6 kΩ RES, 22.6 kΩ, 1%, 0.063 W 0402 CRCW040222K6FKED Vishay-Dale
R12 1 15.8 kΩ RES, 15.8 kΩ, 1%, 0.063 W 0402 CRCW040215K8FKED Vishay-Dale
R13 1 11.0 kΩ RES, 11.0 kΩ, 1%, 0.063 W 0402 CRCW040211K0FKED Vishay-Dale
R14 1 6.8 kΩ RES, 6.8 kΩ, 5%, 0.063 W 0402 CRCW04026K80JNED Vishay-Dale
R15 0 4.99 kΩ RES, 4.99 kΩ, 1%, 0.063 W 0402 CRCW04024K99FKED Vishay-Dale
R16 1 16.5 kΩ RES, 16.5 kΩ, 1%, 0.1 W 0603 CRCW060316K5FKEA Vishay-Dale
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Table 4-1. Component BOM (continued)
REF DES QTY VALUE DESCRIPTION PACKAGE PART NUMBER MANUFACTURER
R17 0 4.99 MΩ RES, 4.99 MΩ, 1%, 0.1 W 0603 CRCW06034M99FKEA Vishay-Dale
SH-J1, SH-J2, SH-J3,
SH-J4, SH-J5, SH-J6 6 1 × 2 Shunt, 100mil, Gold plated, Black Shunt SNT-100-BK-G Samtec
TP1, TP2, TP3, TP4,
TP5, TP6, TP7, TP8 8 Test Point, Miniature, SMT - 5019 Keystone
U1 1 TPSM63610RDFR B3QFN-22 TPSM63610RDFR Texas Instruments
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4.3 PCB Layout
Figure 4-2 through Figure 4-7 show the PCB layout images, including 3D views, copper layers, assembly
drawings, and layer stackup diagram. The PCB is 62-mils standard thickness with 2-oz copper on all layers.
Figure 4-2. 3D Top View
Figure 4-3. 3D Bottom View
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Figure 4-4. Top Layer Copper
Figure 4-5. Layer 2 Copper
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Figure 4-6. Layer 3 Copper
Figure 4-7. Bottom Layer Copper (Viewed From Top)
4.4 Multi-Layer Stackup
Figure 4-8. Layer Stackup
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5 Device and Documentation Support
5.1 Device Support
5.1.1 Development Support
For development support see the following:
• For TI's reference design library, visit TI Reference Design library
• For TI's WEBENCH Design Environment, visit the WEBENCH® Design Center
• To design a low-EMI power supply, review TI's comprehensive EMI Training Series
• To design an inverting buck-boost (IBB) regulator, visit DC/DC inverting buck-boost modules
• TI Reference Designs:
–Multiple output power solution for Kintex 7 application
–Arria V power reference design
–Altera Cyclone V SoC power supply reference design
–Space-optimized DC/DC inverting power module reference design with minimal BOM count
–3- to 11.5-VIN, –5-VOUT, 1.5-A inverting power module reference design for small, low-noise systems
• Technical Articles:
–Powering medical imaging applications with DC/DC buck converters
–How to create a programmable output inverting buck-boost regulator
• To view a related device of this product, see the LM61495 36-V, 10-A synchronous buck converter
5.1.1.1 Custom Design With WEBENCH® Tools
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance.
• Run thermal simulations to understand board thermal performance.
• Export customized schematic and layout into popular CAD formats.
• Print PDF reports for the design, and share the design with colleagues.
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
5.2 Documentation Support
5.2.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Innovative DC/DC Power Modules selection guide
• Texas Instruments, Enabling Small, Cool and Quiet Power Modules with Enhanced HotRod™ QFN Package
Technology white paper
• Texas Instruments, Benefits and Trade-offs of Various Power-Module Package Options white paper
• Texas Instruments, Simplify Low EMI Design with Power Modules white paper
• Texas Instruments, Power Modules for Lab Instrumentation white paper
• Texas Instruments, An Engineer's Guide To EMI In DC/DC Regulators e-book
• Texas Instruments, Soldering Considerations for Power Modules application report
• Texas Instruments, Practical Thermal Design With DC/DC Power Modules application report
• Texas Instruments, Using New Thermal Metrics application report
• Texas Instruments, AN-2020 Thermal Design By Insight, Not Hindsight application report
• Texas Instruments, Using the TPSM53602/3/4 for Negative Output Inverting Buck-Boost Applications
application report
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