Texas Instruments TSW3003 User manual

User's GuideSLWU029D – October 2006 – Revised August 2007
TSW3003 Demonstration Kit
Contents1 Demonstration Kit Configuration Options ................................................................................. 32 Block Diagrams .............................................................................................................. 43 Key Texas Instruments Components ..................................................................................... 54 Software Installation ......................................................................................................... 55 Software Operation .......................................................................................................... 56 Board Setup ................................................................................................................. 127 Demo Kit Test Configuration .............................................................................................. 138 Basic Test Procedure ...................................................................................................... 239 Optional Configurations.................................................................................................... 2710 Filter Specifications ........................................................................................................ 2911 Bill of Materials and Schematics ......................................................................................... 30
List of Figures
1 System Block Diagram ...................................................................................................... 42 Demo Kit Block Diagram .................................................................................................... 43 TSW3003 Startup Screen .................................................................................................. 64 Default CDCM7005 SPI GUI ............................................................................................... 75 TRF3761 GUI - Main Menu ................................................................................................ 86 TRF3761 GUI - Advanced Menu .......................................................................................... 87 DAC5687 GUI ................................................................................................................ 98 Test System Block Diagram .............................................................................................. 139 Single-Carrier Test Mode 1 WCDMA, Typical Performance With IF=30.72 MHz, LO=2.14 GHz ............... 1510 Missing Middle-Carrier Test Mode 1 WCDMA, Typical Performance With IF=30.72 MHz, LO=2.14 GHz ..... 1611 Four-Carrier Test Mode 1 WCDMA, Typical Performance With IF=153.6 MHz, LO=2.14 GHz ................. 1712 ACPR Versus Output Power for 1Carrier WCDMA .................................................................... 1813 ACPR Versus Output Power for 2 Carriers WCDMA .................................................................. 1814 ACPR Versus Output Power for 3 Carriers WCDMA .................................................................. 1915 ACPR Versus Output Power for 4 Carriers WCDMA .................................................................. 1916 Optimum ACPR for 1 Carrier WCDMA, -7-dB Pad .................................................................... 2017 Optimum ACPR for 2 Carrier WCDMA, -7-dB Pad .................................................................... 2118 Optimum ACPR for 3 Carrier WCDMA, -7-dB Pad .................................................................... 2219 Optimum ACPR for 4 Carrier WCDMA, -7-dB Pad .................................................................... 2320 Default DAC GUI With f
DAC
/8 Tone From NCO ........................................................................ 2521 Single Sideband Spectrum Output Before DAC Offset and QMC Adjustments ................................... 2522 DAC GUI With Typical Settings To Minimize LO and Sideband ..................................................... 2623 Sideband and LO Compensated Using QMC Settings ................................................................ 2724 Board Modifications for External LO ..................................................................................... 2825 Jumper Settings to Disable TRF3761 ................................................................................... 2826 Jumper Changes for External VCXO .................................................................................... 29
List of Tables
1 Frequency Bands ............................................................................................................ 32 CDCM7005 Register Values ............................................................................................... 7Windows is a trademark of Microsoft Corporation.
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 1Submit Documentation Feedback

www.ti.com
3 Jumper List .................................................................................................................. 124 Input/Output Connections ................................................................................................. 125 Demo Kit Typical Specifications .......................................................................................... 146 Frequency Designations ................................................................................................... 247 Bill of Materials ............................................................................................................. 30
2TSW3003 Demonstration Kit SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
1 Demonstration Kit Configuration Options
1.1 DAC Component
1.2 VComm Configuration
1.3 VCXO
1.4 LO Generation
Demonstration Kit Configuration Options
The TSW3003 Demonstration (Demo) Kit can be configured in different ways to evaluate differentcomponents in different frequency bands. This section outlines the various component configurations.Based on the configuration, testing and board setup must be altered to accommodate the givencomponents and features.
The TSW3003 Demo Kit is built for the DAC5687, although this Demo Kit can also support the DAC5686because the two devices are pin compatible. The procedures outlined in this document are primarily suitedfor the DAC5687, but can be modified easily for the DAC5686 if desired.
The analog quadrature modulator requires a common-mode dc voltage of approximately 3.3 V. In order touse the dc-offset adjustment capabilities of the DAC5687 for carrier suppression, it is imperative tomaintain a dc path from the DAC output to the modulator input. The common-mode voltage for themodulator is maintained with a passive resistor network that is designed to provide the proper operationpoint for the DAC5687 and the TRF3703 modulator. By design, in order to preserve the proper dc levels,the DAC coarse gain should be kept at the maximum (15), though deviation by a few steps is generallyacceptable with no degradation in performance.
The CDCM7005 requires a VCXO source to derive its output clock signals. The VCXO is at referencedesignator U1. The frequency of the VCXO can be changed to operate the Demo Kit with differentclocking schemes for different modulation standards or for specific customer requirements. Denote whichVCXO frequency is on the board so that the CDCM7005 part can be set up properly. The followingconventions are typically used:•WCDMA: Derivatives of 61.44 MHz (i.e., 122.88 MHz, 245.76 MHz, 491.52 MHz)•GSM: Derivatives of 52 MHz (i.e., 104 MHz, 208 MHz)•CDMA2K: Derivatives of 78.6432 (i.e., 157.2864 MHz, 314.5728 MHz)
The integrated VCO of the TRF3761 outputs the RF signal used for the LO drive on the analog quadraturemodulator. The RF output frequency is contingent on the LO frequency value. The default TRF3761-Htypically has a tuning range from 2028 to 2175 MHz. Other frequency bands will require the existingTRF3761 to be changed to another pin-compatible part in a different frequency band. Using the TRF3761internal divider or another TRF3761 part to generate frequencies outside this range requires the outputterminations to be changed. Contact TI for support in this situation.
The RF frequency band of the VCO must be noted in order to know how to program the TRF3761 and atwhat frequency to measure the output RF signal from the modulator. The typical bands of operation areshown in Table 1 .
Table 1. Frequency Bands
UMTS PCS GSM900 DCS1800
FREQUENCY 2110-2170 MHz 1930-1990 MHz 935-960 MHz 1805-1880 MHz
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 3Submit Documentation Feedback

www.ti.com
2 Block Diagrams
2.1 System Block Diagram
DAC
I/Q
Modulator
90°
0°
LPA TX
Diplexer
ANT
RX
LNA
A/D I/Q
Demod
2.2 Demo Kit Block Diagram
16
DAC5687
16
CLK1
TRF3703
I/Q
Modulator RF Out
TRF3750
VCXO
TRF3761
PLL
LO Generator
Ref Osc
CDCM7005
Clock Gen
CLK2
Block Diagrams
The basic radio system block diagram in Figure 1 demonstrates where the TSW3003 Demo Kit fits in theoverall transceiver. The dash-line box illustrates the components found on the TSW3003 Demo Kit board.
Figure 1. System Block Diagram
The basic Demo Kit block diagram is shown in Figure 2 . The shaded boxes illustrate the key TexasInstruments components found on the TSW3003 Demo Kit board.
Figure 2. Demo Kit Block Diagram
TSW3003 Demonstration Kit4 SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
3 Key Texas Instruments Components
3.1 CDCM7005
3.2 DAC5687
3.3 TRF3703
3.4 TRF3761
4 Software Installation
5 Software Operation
Key Texas Instruments Components
The CDCM7005 clock distribution chip is used to generate and synchronize the clock outputs to thesystem. The device has five outputs which can be either LVPECL or LVCMOS and can be divided downby 1, 2, 3, 4, 6, 8, and 16. The divide by 16 can be replaced with a divide by 4 or 8 with a 90 degreephase shift.
The DAC5687 is a 16-bit interpolating dual digital-to-analog converter (DAC). The device incorporates adigital modulator, independent differential offset control, and I/Q amplitude control. The device is typicallyused in baseband mode or in low IF mode with an analog quadrature modulator.
The TRF3703 is a direct upconversion IQ modulator. This device accepts a differential input voltagequadrature signal at baseband or low IF frequencies and outputs a modulated RF signal based on the LOdrive frequency.
The TRF3761 is a family of high performance, highly integrated frequency synthesizers, optimized forwireless infrastructure applications. The TRF3761 includes an integrated VCO and integer-N PLL.Different members of the TRF3761 family can be chosen for application specific VCO frequency ranges.
This section summarizes the installation procedures for the software required to operate the Demo Kit.Once all of the software is loaded, it is recommended to reboot the computer. This software has beenverified to be functional on Win2K and WinXP.•Execute setup.exe•Reboot computer as required by the Windows™ operating system.•Power up the TSW3003EVM, and plug in the USB cable.•Allow the Windows™ operating system to automatically find and install the TSW3003 USB drivers.•Start the TSW3003 USB Vx.x software.
The following describes the use of the software required to set the TSW3003 Demo Kit in the baselineconfiguration for the CDCM7005, TRF3761, and DAC5687. The software should be configured in theorder presented below. The first step requires starting the TSW3003 software. This opens a window asshown in Figure 3 . The tabs on the left side of the window allow selection of different GUI controllers forthe DAC5687, TRF3761, and CDCM7005. The lower left portion of the screen contains links to this user'sguide as well as the data sheets for the DAC5687, TRF3761, and the CDCM7005.
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 5Submit Documentation Feedback

www.ti.com
5.1 CDCM7005 Software
Software Operation
Figure 3. TSW3003 Startup Screen
By using the provided CDCM7005 serial peripheral interface (SPI) software, the user can load settings tothe CDCM7005 internal registers. This must be performed every time the TSW3003 Demo Kit is poweredup, because the CDCM7005 has default settings that are loaded at power up and the settings may beslightly different than the ones required to operate the Demo Kit. Executing the program brings up theinterface seen in Figure 4 . The default settings are correct for a VCXO of 491.52 MHz and a 10 MHzreference as on the TSW3003. The CDCM7005 GUI allows register settings to be saved and can beloaded back in afterwards. This can be accomplished with the Save and Load Settings buttons near theright side of the GUI.
It is recommended that any unused output clocks be tri-stated. In this case the TSW3003 only usesOUT_MUX_1 to drive the DAC5687. OUT_MUX_0, OUT_MUX_2, OUT_MUX_3, OUT_MUX_4 should betri-stated unless there is a need to use the other output clocks.
6TSW3003 Demonstration Kit SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
Software Operation
Figure 4. Default CDCM7005 SPI GUI
The divider parameters, M and N, are determined according to the following equation based on theinternal reference frequency and internal VCXO frequency.
F
REF
= (F
VCXO
×M)/(N ×P)
The p parameter is the VCXO input divider and set through the FB_MUX value. The M and N countervalues need to be adjusted depending on the board configuration. The M and N counter registers aredetermined by the reference frequency and the VCXO frequency. The OUT_MUX sets the divide ratios forthe individual output clocks. The OUTSEL determines whether the output clocks will be used assingle-ended CMOS or differential LVPECL. With a 10-MHz reference oscillator the CDCM7005 settingsare shown in Table 2 for a variety of common VCXO frequencies. A calculator is included in theCDCM7005 GUI software to calculate the M and N values based on Ref and VCXO frequencies.
Table 2. CDCM7005 Register Values
VCXO Freq. (MHz) 491.52 245.76 122.88 61.44
Divider M 125 125 125 125Divider N 768 768 768 768FB_MUX 8 4 2 1
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 7Submit Documentation Feedback

www.ti.com
5.2 TRF3761 Software
Software Operation
The TRF3761 software is used to program the internal PLL chip to lock the integrated VCO onto a desiredfrequency output. The main menu of the program is shown in Figure 5 .
Figure 5. TRF3761 GUI - Main Menu
The options in the front panel allow the user to program the desired frequency of the VCO, the desiredfrequency of the PFD, the reference frequency, and the prescaler selection. The software then displaysthe actual VCO frequency, PFD frequency and the R, N, A, and B counter values to be programmed intothe TRF3761. Hitting the Send button writes these values to the TRF3761. In default mode on a defaultboard, only the desired VCO frequency (2028 MHz to 2175 MHz) needs to be changed. For other VCOranges, a different member of the TRF3761 family needs to be selected and other parameters may needto be changed. The Advanced Operation button will bring up another user interface as shown in Figure 6 .
Figure 6. TRF3761 GUI - Advanced Menu
This menu allows control of more register settings. For details on these settings, see the TRF3761 data
8TSW3003 Demonstration Kit SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
5.3 DAC5687 Software
5.4 DAC5687 GUI Register Descriptions
5.4.1 Register Controls
Software Operation
sheet (SLWS181 ). The register of interest in this menu is the MUXOUT CONTROL which can be used todetermine the function of LED D4. This mode defaults to Digital PLL Lock Detect and causes the LED D4to light up when the PLL successfully locks. Normally, these menu settings do not need to be changed. Ifthe divider ratios are changed, the TRF3761 output termination needs to be modified to accommodate thenew output frequency. Otherwise, the performance may be degraded. Contact TI in this situation.
By using the provided software, the user can write and read control register information to the DAC5687.Once the Demo Kit is powered on and connected properly, then the GUI shown in Figure 7 is displayedwith the default settings read from the device. If there is a problem with the communication, such as theDemo Kit is not powered on or the USB cable is not connected, an error message will be displayedinstructing the user to correct the problem. Once corrected, hit the Read All button to read the defaultsettings of the device.
Figure 7. DAC5687 GUI
For normal operation, the user needs only to select values and switches as desired. The values areautomatically sent to the device and read back to verify their configuration.
•Load Regs – Loads register values from a saved file to the DAC5687 and updates the GUI.•Save Regs – Saves current GUI registers settings to a text file for future use.•Read All – Reads the current registers of the DAC5687. This is used to verify settings on the frontpanel.
•Send All – Sends the current front panel registers to the device. This is generally only used when theDemo Kit power has recycled or the device has been reset and the user wants to load the displayedsettings to the device.•Load Factory Optimization – Load default LO and sideband optimized values for the default boardcondition.
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 9Submit Documentation Feedback

www.ti.com
5.4.2 Configuration Controls
Software Operation
•Full Bypass – When set, all filtering, QMC, and NCO functions are bypassed.•FIR Bypass – Bypass all interpolation filters. QMC INCO functional. Limited to FDAC = 250 MHz•FIFO Bypass – When set to bypass, the internal four sample FIFO is disabled. When cleared, theFIFO is enabled.•FIR A – A side first FIR filter in high-pass mode when set, low-pass mode when cleared.•FIR B – B side first FIR filter in high-pass mode when set, low-pass mode when cleared.•Dual Clk – Only used when the PLL is disabled. When set, two differential clocks are used to input thedata to the chip; CLK1/CLK1C is used to latch the input data into the chip, and CLK2/CLK2C is usedas the DAC sample clock.•Interleave – When set, interleaved input data mode is enabled; both A and B data streams are input atthe DA(15:0) input pins.•Inverse Sinc – Enables inverse sinc filter.•Half Rate Input – Enables half rate input mode. Input data for the DAC A data path is input to the chipat half speed using both the DA(15:0) and DB(15:0) input pins.•Sif – Sets sif_4-pin bit. A 4-pin serial interface mode is enabled when on, 3-pin mode when off. TheDAC5687 Demo Kit is configured for a 3-pin serial interface, so setting to a 4-bit serial interface makesreading registers impossible with the GUI.•Inv. PLL Lock – Only used when PLL is disabled and dual clock mode is disabled. When cleared,input data is latched into the chip on rising edges of the PLLLOCK output pin. When set, input data islatched into the chip on falling edges of the PLLLOCK output pin.•PLL Freq – Sets PLL VCO center frequency to low or high center frequency.•PLL Kv – Sets PLL VCO gain to either high or low gain.•Qflag – Sets qflag bit. When set, the QFLAG input pin operates as a B sample indicator wheninterleaved data is enabled. When cleared, the TXENABLE rising determines the A/B timingrelationship.
•2's Comp – When set, input data is interpreted as 2's complement. When cleared, input data isinterpreted as offset binary.•Rev A Bus – When cleared, DA input data MSB to LSB order is DA(15) = MSB and DA(0) = LSB.When set, DA input data MSB to LSB order is reversed, DA(15) = LSB and DA(0) = MSB.•Rev B Bus – When cleared, DB input data MSB to LSB order is DB(15) = MSB and DB(0) = LSB.When set, DB input data MSB to LSB order is reversed, DB(15) = LSB and DB(0) = MSB.•USB – When set, the data to DACB is inverted to generate upper side band output.•Inv. Clk I(Q) – Inverts the DAC core sample clock when set, normal when cleared.•Sync_Phstr – When set, the internal clock divider logic is initialized with a PHSTR pin low to hightransition.
•Sync_cm – When set, the coarse mixer is synchronized with a PHSTR low-to-high transition.•Sync_NCO – When set, the NCO phase accumulator is cleared with a phstr low-to-high transition.•Phstr Clk Div Select – Selects the clock used to latch the PHSTR input when restarting the internalclock dividers. When set, the full rate CLK2 signal latches PHSTR and when cleared, the divided downinput clock signal latches PHSTR.•DAC Serial Data – When set, both DAC A and DAC B input data is replaced with fixed data loadedinto the 16-bit serial interface DAC Static Data.–Counter Mode – Controls the internal counter that can be used as the DAC data source: {off; all16b; 7b LSBs; 5b MIDs; 5b MSBs}.–DAC Static Data – When DAC Serial Data is set, both DAC A and DAC B input data is replacedwith fixed data loaded with this value. Range = 0 - 65535.•Alt. PLLLOCK Output – Can be used to determine alternate outputs on the PLLLOCK pin when usingthe internal PLL mode. The EXTLO pin must be open when using this mode.•NCO – When set, enables NCO.–NCO Gain – Sets NCO gain resulting in a 2x increase in NCO output amplitude. Except for F
s
/2and F
s
/4 mixing NCO frequencies, this selection can result in saturation for full-scale inputs.Consider using QMC gain for lower gains.
10 TSW3003 Demonstration Kit SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
5.4.3 DAC A(B) Gain
5.4.4 NCO
5.4.5 Additional Control/Monitor Registers
Software Operation
•QMC – When set, enables the QMC.–QMCA Gain – Sets QMC gain A to a range = 0 to 2047. See the data sheet for more information.–QMC B Gain – Sets QMC gain B to a range = 0 to 2047. See the data sheet for more information.–QMC Phase – Sets QMC phase to a range = -512 to 511. See the data sheet for more information.Used to adjust for I/Q phase imbalance.•Mode – Used to select the coarse mixer mode. See the DAC5687 data sheet for more information.•PLL Divider – Sets VCO divider to div by 1, 2, 4, or 8.•Interpolation – Sets FIR Interpolation factor: {X2, X4, X4L, X8}. X4 uses lower power than 4xL, butF
dac
= 320 MHz max when NCO or QMC are used.•Phstr Init. Phase – Adjusts the initial phase of the FS/2 and FS/4 CMIP block at PHSTR.•Sync FIFO – Sync source selection mode for the FIFO. When a low to high transition is detected onthe selected sync source, the FIFO input and output pointers are initialized. See the DAC5687 datasheet for source description.
•DAC Coarse Gain – Sets coarse gain of DAC A(B) full-scale current. Range is 0 to 15. See theDAC5687 data sheet for full-scale gain equation.•DAC Fine Gain – Sets fine gain of DAC A(B) full scale current. Range is -128 to127. See theDAC5687 data sheet for full-scale gain equation. Used to adjust for I/Q amplitude imbalance.•DAC DCOffset – Sets DAC A(B) dc-offset register. Range is -4096 to 4095. Used to adjust for carriersuppression.
•Sleep – DAC A(B) sleeps when set, operational when cleared.
•NCO DDS – Sets NCO DDS registers. See the DAC5687 data sheet for formula.•NCO Phase – Sets initial NCO phase registers. See the DAC5687 data sheet for more information.•F
DAC
(MHz), NCO IF (MHz) – Used to calculate the required NCO DDS value.
•Version – Displays the version of the silicon. If a version of 0 is read then the communication is notfunctioning and an error message will be displayed.
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 11Submit Documentation Feedback

www.ti.com
6 Board Setup
6.1 Jumper Settings
6.2 Input/Output Connectors
Board Setup
The TSW3003 Demo Kit has onboard jumpers that allow the user to selectively disengage devices asdesired. The unit is shipped with jumpers in place that activate all of the devices on board. Table 3explains the functionality of the jumpers on the board.
Table 3. Jumper List
Jumper Label Function Condition Default
JP1 VCXOB Choose internal VCXO or external VCXO INB Internal VCXO Pin 1, 2JP2 VCXO Choose internal VCXO or external VCXO INA Internal VCXO Pin 1, 2SJP3 SJP3 Choose 1.8 or 2.1 VDD 1.8 VDD Pin 1, 2JP6 REF CLK Choose internal 10-MHz ref or external ref 10 MHz Pin 2, 3JP8 DEFAULT 3.3VA Choose 3.3V or 1.8V for IOVDD 3.3 VDD Pin 1, 2J31-2 PLL_VDD PLLVDD GND (OFF) or 3.3V (ON) GND Pin 1, 2J31-5 SLEEP SLEEP GND (ACTIVE) or 3.3V (SLEEP) GND Pin 4, 5J31-8 EXTLO Internal (GND) or external (3.3V) voltage reference GND Pin 7, 8J31-11 TX_ENABLE High enable data for DAC 3.3 V Pin 11, 12J31-14 TESTMODE GND GND Pin 22, 23J31-17 No ConnectJ31-20 CDC_PD Low active power down of CDCM7005 3.3 V Pin 20, 21J31-23 PD_OUTBUF Power down output buffer of TRF3761 GND Pin 22, 23J31-26 CHIP_EN Enable TRF3761 chip 3.3 V Pin 26, 27J31-29 RESET Low active reset of DAC5687 3.3 V Pin 29, 30J31-32 PLLLCK_EN Low active PLLLOCK output buffer GND Pin 31, 32J31-35
(1)
No Connect
(1)
VCXO does not have Output Enable control.
The input and output connections are shown in Table 4 .
Table 4. Input/Output Connections
Reference Designator Connector Type Description
J1 Power Connector 6 VDC from wall adapterJ4 34-pin header External VCXO connectionJ7 SMA Optional input clock from CDCM7005J8 SMA Optional input clock from CDCM7005J9 SMA Optional input clock from CDCM7005J27 SMA PLLLLCK output from DAC5687, used to indicate lock or to drive externaldata sourceJ29 34-pin header DA input to the DAC5687J30 34-pin header DB input to the DAC5687J32 SMA RF output from modulatorJ34 USB USB connector for GUI softwareJ35 SMA External Ref clock inputJ37 Banana Plug +6-VDC connector for external DC supplyJ38 Banana Plug GND connection for external DC supply
TSW3003 Demonstration Kit12 SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
6.3 USB Port
6.4 DC Power Requirements
7 Demo Kit Test Configuration
7.1 Test Setup Block Diagram
TSW3003
EVM DUT
J27
Clock
Power
Supply GND
+6 V
16
USB
J32
Pattern
Generator 16
J38 J37
PC Controller
J30
J29
J34
Spectrum
Analyzer
7.2 Test Equipment
Demo Kit Test Configuration
The TSW3003 Demo Kit contains a 4-pin USB port connector (J34) to interface to a standard computerUSB port. Programming of the CDCM7005, DAC5687, and TRF3761 are accomplished through this port.
The Demo Kit requires a single dc-voltage supply that is nominally 6 V. From that supply, the 5 V, 3.3 V,and 1.8 V required for the devices on the board are generated internally through linear voltage regulators.It is possible to use a higher input voltage; however, care should be taken not to over dissipate theonboard voltage regulators.
The test set up for general testing of the TSW3003 Demo Kit is shown in Figure 8 .
Figure 8. Test System Block Diagram
The following is a list of the test equipment required for testing the TSW3003 Demo Kit. Equivalent modelsmay be used for certain applications, but may produce different results due to limitations within theinstrument.
•Dual Power Supply: Any with current readout capability or use the supplied 6VDC 4A wall supply•Spectrum Analyzer: Rhode & Schwartz FSU, Agilent PSA, or equivalentThis particular piece can measure >70-dBc ACPR with the noise cancellation option active. Thisamount of dynamic range is required to accurately measure the ACPR of the Demo Kit. Anotherspectrum analyzer can be substituted if it achieves as good or better dynamic range.•Pattern Generator: Agilent 16720A•Oscilloscope: Tektronix 650 or equivalentUsed to probe clock output signals and for debugging.•Digital Voltmeter: Agilent 34401A or equivalent
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 13Submit Documentation Feedback

www.ti.com
7.3 Calibration
7.4 Test Specifications
Demo Kit Test Configuration
In order to record proper output power the insertion loss of the output cable must calibrated. Measure theinsertion loss of the cable from J32 to the spectrum analyzer; set the analyzer's reference level offset tothat value.
The test specifications are outlined in Table 5 .
Table 5. Demo Kit Typical Specifications
MIN MAX UNITS
CURRENT
+6 V 1.5 A
CW TESTS
Carrier suppression 30 dBcSideband rejection 25 dBc
Spurious Output
2nd harmonic 45 dBcAliased LSB (pos) 40 dBcOutput clock 40 dBcAliased USB 15 dBcAliased USB (neg) 8 dBc
WCDMA ACPR
Channel power -14 dBmACPR -Low 76 dBcACPR -High 76 dBc
TSW3003 Demonstration Kit14 SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
A
Ref -17.5 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 5 sAtt 5 dB
*
1 R M
NOR
*
Center 2.17072 GHz Span 25.5 MHz2.55 MHz/
EXT
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
Tx Channel W-CDMA 3GPP FWD
Bandwidth 3.84 MHz
Power -11.85 dBm
Adjacent Channel
Bandwidth 3.84 MHz
Lower -76.67 dB
Spacing 5 MHz
Upper -76.59 dB
Alternate Channel
Bandwidth 3.84 MHz
Lower -77.96 dB
Spacing 10 MHz
Upper -77.75 dB
POS -17.512 dBm
Demo Kit Test Configuration
Figure 9. Single-Carrier Test Mode 1 WCDMA, Typical PerformanceWith IF=30.72 MHz, LO=2.14 GHz
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 15Submit Documentation Feedback

www.ti.com
A
Ref -20.1 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 5 sAtt 5 dB
*
1 R M
NOR
*
Center 2.17072 GHz Span 35.6 MHz3.56 MHz/
EXT
-110
-100
-90
-80
-70
-60
-50
-40
-30
Standard: W-CDMA 3GPP FWD
Tx Channels
Ch1 -16.46 dBm
(Ref)
Ch2 -88.87 dBm
Ch3 -16.56 dBm
Total -13.50 dBm
Adjacent Channel
Lower -72.90 dB
Upper -72.69 dB
Alternate Channel
Lower -72.51 dB
Upper -72.55 dB
POS -20.129 dBm
Demo Kit Test Configuration
Figure 10. Missing Middle-Carrier Test Mode 1 WCDMA, Typical PerformanceWith IF=30.72 MHz, LO=2.14 GHz
16 TSW3003 Demonstration Kit SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
A
Ref -25.8 dBm
*
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 5 sAtt 5 dB
*
1 R M
NOR
*
Center 2.2936 GHz Span 40.6 MHz4.06 MHz/
EXT
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
Standard: W-CDMA 3GPP FWD
Tx Channels
Ch1 -22.39 dBm
(Ref)
Ch2 -22.48 dBm
Ch3 -22.63 dBm
Ch4 -22.72 dBm
Total -16.53 dBm
Adjacent Channel
Lower -64.03 dB
Upper -64.65 dB
Alternate Channel
Lower -65.48 dB
Upper -64.78 dB
POS -25.811 dBm
7.5 WCDMA Output Power Versus ACPR Performance
Demo Kit Test Configuration
Figure 11. Four-Carrier Test Mode 1 WCDMA, Typical PerformanceWith IF=153.6 MHz, LO=2.14 GHz
The ACPR has some dependency on the output power of the TSW3003. The RF output spectrum showssome IMD effects as the output power of the DAC is increased. The optimum ACPR performance occurswhen there is approximately a -6dB attenuation pad between the DAC output and the TRF3703 input. Asthe power is increased the IMD3 effects start to affect the ACPR. As the power is decreased, the ACPRbecomes linear as a function of the signal power and the noise floor.
The ACPR results have been tabulated in Figure 12 through Figure 15 for 1, 2, 3, and 4 WCDMA carrierswith the TM1 signal.
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 17Submit Documentation Feedback

www.ti.com
1 Carrier ACPR vs Pout, Baseband 2.14 GHz
-20 -15 -10 -5 0
Pout dBm/Channel
dB
1 ACPR
1 Alt ACPR
85
80
75
70
65
60
55
50
11 Carrier ACPR vs Pout, Baseband 2.14 GHz
-30 -25 -20 -15 -10 -5
Pout dBm/Channel
dB
11 ACPR
11 Alt ACPR
80
75
65
55
70
60
Demo Kit Test Configuration
Figure 12. ACPR Versus Output Power for 1Carrier WCDMA
Figure 13. ACPR Versus Output Power for 2 Carriers WCDMA
18 TSW3003 Demonstration Kit SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback

www.ti.com
111 Carrier ACPR vs Pout, Baseband 2.14 GHz
-30 -25 -20 -15 -10 -5
Pout dBm/Channel
dB
111 ACPR
111 Alt ACPR
75
73
71
69
67
65
63
61
59
57
55
1111 Carrier ACPR vs Pout, Baseband 2.14 GHz
-30 -25 -20 -15 -10 -5
Pout dBm/Channel
dB
1111 ACPR
1111 Alt ACPR
75
73
71
69
67
65
63
61
59
57
55
Demo Kit Test Configuration
Figure 14. ACPR Versus Output Power for 3 Carriers WCDMA
Figure 15. ACPR Versus Output Power for 4 Carriers WCDMA
SLWU029D – October 2006 – Revised August 2007 TSW3003 Demonstration Kit 19Submit Documentation Feedback

www.ti.com
A
Ref -16.9 dBm
*
*
CLRWR
RBW 30 kHz
VBW 300 kHz
SWT 3 s
*
Att 5 dB
*
1 R M
NOR
*
Center 2.14 GHz Span 25.5 MHz2.55 MHz/
EXT
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
Tx Channel W-CDMA 3GPP FWD
Bandwidth 3.84 MHz
Power -12.05 dBm
Adjacent Channel
Bandwidth 3.84 MHz
Lower -75.95 dB
Spacing 5 MHz
Upper -75.70 dB
Alternate Channel
Bandwidth 3.84 MHz
Lower -78.95 dB
Spacing 10 MHz
Upper -79.24 dB
Demo Kit Test Configuration
Typical ACPR results are shown in Figure 16 through Figure 19 for the four cases.
Figure 16. Optimum ACPR for 1 Carrier WCDMA, -7-dB Pad
20 TSW3003 Demonstration Kit SLWU029D – October 2006 – Revised August 2007Submit Documentation Feedback