Texas Instruments DCA1000EVM User manual

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DCA1000EVM Data Capture Card
User's Guide
SPRUIJ4A–May 2018–Revised May 2019
DCA1000EVM Data Capture Card
Contents
1 Introduction ................................................................................................................... 3
2 Hardware Specifications .................................................................................................... 4
3 System Setup............................................................................................................... 16
4 DCA1000EVM Ethernet Configuration Data............................................................................ 17
5 DCA1000EVM Command and Data Format............................................................................ 18
6 Use Case: LVDS Over Ethernet Streaming ............................................................................ 20
7 Errors ........................................................................................................................ 21
8 Troubleshooting ............................................................................................................ 22
9 FPGA Programming ....................................................................................................... 22
10 Limitations................................................................................................................... 26
List of Figures
1 DCA1000EVM Functional Block Diagram................................................................................ 4
2 DCA1000EVM – Top View ................................................................................................. 5
3 DCA1000EVM – Bottom View ............................................................................................. 5
4 DCA1000EVM and xWR1xxx EVM Board Alignment................................................................... 6
5 Connect Screws and Spacers ............................................................................................. 6
6 Connect Boards.............................................................................................................. 7
7 Connect Ribbon Cable...................................................................................................... 7
8 Connect Ribbon Cable (Side).............................................................................................. 8
9 Power Connector ............................................................................................................ 8
10 Power Selection Switch..................................................................................................... 8
11 J1 USB Connector........................................................................................................... 9
12 J4 USB Connector ......................................................................................................... 10
13 J6 Ethernet Jack ........................................................................................................... 11
14 J3 High Density Interface Connector .................................................................................... 12
15 Mode Configuration_1..................................................................................................... 13
16 Mode Configuration_2..................................................................................................... 14
17 Push Button................................................................................................................. 14
18 User LEDs................................................................................................................... 15
19 Board Setup................................................................................................................. 16
20 FPGA Config Switch....................................................................................................... 22
21 Device Manager............................................................................................................ 23
22 Hardware Setup ............................................................................................................ 23
23 FTDI USB Cable Detection ............................................................................................... 24
24 FPGA Device Scan ........................................................................................................ 24
25 Select JTAG Option and Bit File ......................................................................................... 25
26 FPGA SPI Flash Programming........................................................................................... 26
List of Tables

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1 Power Selection Switch Information....................................................................................... 9
2 J1 USB Connector Information ............................................................................................ 9
3 J4 USB Connector Information........................................................................................... 10
4 J6 Ethernet Jack Information ............................................................................................. 10
5 J3 High Density Interface Connector Information...................................................................... 11
6 Switch2.5 Functionality Information...................................................................................... 13
7 Switch1 Functionality Information........................................................................................ 13
8 Switch2 Functionality Information........................................................................................ 13
9 Push Button Functionality Information................................................................................... 14
10 LED Functionality Information ............................................................................................ 15
11 Table 11 Default Value Stored in FPGA Registers.................................................................... 17
12 Supported Commands..................................................................................................... 18
13 Reset FPGA Command Request From Host........................................................................... 19
14 Command Response From the DCA1000EVM ........................................................................ 19
15 Data Separated Mode Data, Identifier, Length Information........................................................... 21
16 Data Type and Port for Data Separated Mode ........................................................................ 21
17 Errors ........................................................................................................................ 21
18 FPGA Configuration Mode................................................................................................ 22
19 Theoretical Throughput.................................................................................................... 26
Trademarks
MicroSD is a trademark of SD-3C, LLC.

www.ti.com Introduction
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DCA1000EVM Data Capture Card
1 Introduction
The DCA1000EVM is a capture card for interfacing with Texas Instrument’s 77GHz xWR1xxx EVM that
enables users to stream the ADC data over Ethernet. This design is based on Lattice FPGA LFE5UM-
85F-8BG381I with DDR3L. The signal interface between the capture card and the xWR1xxx EVM uses
the 60-pin Samtec high density connector.
The following use cases can be accessed using the DCA1000EVM with TI's xWR1xxx EVM.
• LVDS over Ethernet streaming:
– Raw mode: In this mode, all LVDS data is captured as it is and streamed over the Ethernet
interface.
– Data separated mode: In this mode, the user can add specific headers to different data types;
FPGA separates out different data types based on the header and streams it over Ethernet
interface.
1.1 Key Features
The key features of the DCA1000EVM are:
• The DCA1000EVM is based on LATTICE's High-Performance FPGA LFE5UM-85F-8BG381I
– Package: 381 pins CABGA (17×17 mm).
– 84K LUT's, 3744 Kbits Block RAM and 4 PLLs
• 2GByte of DDR3L device
• 16MByte SPI Flash for storing FPGA images
• MicroSD™ Card interface (presently not supported)
• JTAG interface through FTDI FT2232HL Chip
• USB interface to provide SPI, UART, and I2C interfaces through the onboard FTDI device. This is used
for mmWave Studio.
• 9 user LEDs, 4 push-button switches, and 1×8 and 1×3 DIP switches for user configurations
• 1Gb/s RGMII Ethernet interface with RJ45 jack
• TI’s xWR1xxx EVM provides the below mentioned interfaces on the 60-pin SAMTEC connector QTH-
030--01-L-D-A. The connector QTH-030-01-L-D-A can be mated with TI's xWR1xxx EVM using board-
to-board cable assembly (Samtec coax micro ribbon cable - Part Number# HQCD-030-02.00-SEU-
TBR-1, is included in the kit).
– SPI interface
– UART interface
– I2C interface
– 4-Lane LVDS interface
– GPIO signals
– DMM interface
• The DCA1000EVM is powered up using 5-V power, either from an external DC adapter, or from TI's
xWR1xxx EVM, by selecting the power selection switch (SW3).
• DC-DC regulators and LDO regulators are used to derive the required power required for FPGA,
DDR3L, and other onboard peripherals.
• RoHS, Pb-free, and REACH-compliant design
• LVDS data rates support a maximum of 600 Mbps. It supports both 4 lanes (xWR1243/1443) and 2
lanes (xWR1642)
• Temperature range – industrial grade
• Maximum current rating – 700-mA maximum

500SSP1S2M2QEA
105017-0001
105017-0001
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1.2 Kit Contents
The following items are included with the DCA1000EVM kit. Unbox the board and identify various
components and connectors as detailed in the user guide.
• DCA1000EVM Kit
• Ethernet cable
• Samtec coax micro ribbon cable
• 8GB microSD Card
• Spacers, screws, and washers
2 Hardware Specifications
2.1 Functional Block Diagram
The functional block diagram of the DCA1000EVM is shown in Figure 1.
Figure 1. DCA1000EVM Functional Block Diagram

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2.2 Board Dimensions
The DCA1000EVM dimensions are 90 mm × 102 mm × 1.6 mm. It is a 10-layer board fabricated with
epoxy fiberglass FR4 grade material (UL94V-0 Certified).
Figure 2. DCA1000EVM – Top View
Figure 3. DCA1000EVM – Bottom View

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2.3 DCA1000EVM and xWR1xxx EVM – Board to Board Connection
To enable easy measurements on the sensing objects on the horizontal plane, the xWR1xxx EVM
(AWR1243BOOST/AWR1443BOOST/AWR1642BOOST) and DCA1000EVM can be mounted vertically by
fixing the L-brackets. The following steps illustrate the assembly of the L-brackets, DCA1000EVM, and
xWR1xxx EVM.
1. Align the DCA1000EVM and xWR1xxx EVM boards, as shown in Figure 4.
Figure 4. DCA1000EVM and xWR1xxx EVM Board Alignment
2. Connect the DCA1000EVM with screws, spacers, and stands, as shown in Figure 5.
Figure 5. Connect Screws and Spacers

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3. Connect the DCA1000EVM with the xWR1xxx EVM, as shown in Figure 6.
Figure 6. Connect Boards
4. Connect the Samtec ribbon cable, as shown in Figure 7 and Figure 8.
Figure 7. Connect Ribbon Cable

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Figure 8. Connect Ribbon Cable (Side)
2.4 Power Connections
The DCA1000EVM is powered by 5-V power, either from a DC jack as shown in Figure 9, or from a 60-pin
high density connector of TI's xWR1xxx EVM mated to J3 of DCA1000EVM, as shown in Figure 14. The
power source is selected through the SPDT power switch (Figure 10) position, as shown in Table 1. When
the power is provided, the 5-V LED (LD10) glows, indicating that the board is powered on.
Figure 9. Power Connector
Figure 10. Power Selection Switch

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Table 1. Power Selection Switch Information
Reference Usage Description
SW3.1 Power selection switch When the switch is closed to position 1, then the external 5-V power is
given through a DC jack.
SW3.3 Power selection switch When the switch is closed to position 3, then the 5-V power is derived from
the xWR1xxx EVM through the 60-pin connectors.
Note: To get 5-V power from the xWR1xxx EVM, the R34 (0 Ω) resistor
should be mounted in the xWR1xxx EVM.
2.5 Connectors
2.5.1 USB Connectors
The DCA1000EVM has two standard micro USB connectors. Connector J1 allows access to the xWR1xxx
EVM through UART, SPI, or I2C through the FTDI chip, using the TI RADAR Studio application, and is as
shown in Figure 11. The mmWave Studio PC application can be used to configure the radar device. For
more details on the mmWave Studio, refer to the following link: http://www.ti.com/tool/MMWAVE-STUDIO.
The second micro USB connector J4 allows programming the FPGA through the FTDI chip through the
JTAG interface, and is shown in Figure 12.
Table 2 provides the J1 connector pin information. Table 3 provides the J4 connector pin information.
To detect the RADAR FTDI and emulate the SPI host bus, connect a micro USB cable to J1 on the
DCA1000EVM.
Table 2. J1 USB Connector Information
Pin No Signal Name Description
1 TP Test Point
2 FTDI_USB1_DM USB Data Signal Negative
3 FTDI_USB1_DP USB Data Signal Positive
4 GND Ground
5 GND Ground
Figure 11. J1 USB Connector
To configure the FPGA through JTAG, connect a micro USB cable to J4 on the DCA1000EVM.

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Table 3. J4 USB Connector Information
Pin No Signal Name Description
1 TP Test Point
2 FTDI_USB2_DM USB Data Signal Negative
3 FTDI_USB2_DP USB Data Signal Positive
4 GND Ground
5 GND Ground
Figure 12. J4 USB Connector
2.5.2 Ethernet Jack
The DCA1000EVM supports a Gigabit Ethernet port to provide the connection to the network. The
Ethernet port is interfaced to the LATTICE FPGA through the Ethernet PHY DP83867IRPAPT, and is
used to stream the captured data over the network to the host PC. Figure 13 shows the Ethernet RJ45
Mag-Jack connector, and Table 4 provides the connector pin details.
Table 4. J6 Ethernet Jack Information
Pin No Signal Name Description
1 GND Ground
2 TP Test point
3 ETH_D3P Gigabit Ethernet differential pair 3 positive
4 ETH_D3N Gigabit Ethernet differential pair 3 negative
5 ETH_D2P Gigabit Ethernet differential pair 2 positive
6 ETH_D2N Gigabit Ethernet differential pair 2 negative
7 ETH_D1P Gigabit Ethernet differential pair 1 positive
8 ETH_D1N Gigabit Ethernet differential pair 1 negative
9 ETH_D0P Gigabit Ethernet differential pair 0 positive
10 ETH_D0N Gigabit Ethernet differential pair 0 negative
11 3V3 Supply voltage for internal anode of activity LED
12 LED_ACTn Activity LED
13 LED_LINKn Link LED
14 3V3 Supply voltage for internal anode of link LED

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Figure 13. J6 Ethernet Jack
2.5.3 60-Pin High Density (HD) Connector
The DCA1000EVM supports a 60-pin HD connector to interface with the xWR1xxx EVM. This connector
provides the high-speed LVDS data, control signals (UART, SPI, I2C, RESET), and DMM interface
signals. The DCA1000EVM captures data from the xWR1xxx EVM over a 4-lane LVDS interface and
playbacks the data from the host PC to the xWR1xxx EVM over a 16-bit DMM/trace interface through the
60-pin connector. Control signals on the 60-pin HD connector are used to access the xWR1xxx EVM
through the FTDI chip. Figure 14 shows the HD connector, and Table 5 provides the connector pin details.
Table 5. J3 High Density Interface Connector Information
Pin No Signal Name Description
1 VCC5V_CONN 5-V supply voltage from xWR1xxx EVM
2 VCC5V_CONN 5-V supply voltage from xWR1xxx EVM
3 VCC5V_CONN 5-V supply voltage from xWR1xxx EVM
4 NC No connect
5 NC No connect
6 NC No connect
7 Conn_SPI_CSn SPI chip select
8 NC No connect
9 Conn_SPI_CLK SPI clock
10 HOST_INT Host interrupt from FTDI
11 Conn_SPI_MOSI SPI master output slave input
12 Conn_SPI_MISO SPI master input slave output
13 PGOOD PGOOD input from xWR1xxx EVM
14 NC No connect
15 DMM_CLK DMM clock
16 DMM_MUX_CTL DMM control
17 DMM_SYNC DMM synchronization
18 GND Ground
19 DP0 DMM Data0
20 LVDS_VALIDP LVDS valid signal positive
21 DP1 DMM Data1
22 LVDS_VALIDM LVDS valid signal negative
23 DP2 DMM Data2
24 GND Ground
25 DP3 DMM Data3
26 LVDS_FRCLKP LVDS frame clock signal positive
27 DP4 DMM Data4
28 LVDS_FRCLKN LVDS frame clock signal negative

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Table 5. J3 High Density Interface Connector Information (continued)
Pin No Signal Name Description
29 DP5 DMM Data5
30 GND Ground
31 DP6 DMM Data6
32 LVDS_3P LVDS data pair 3 positive
33 DP7 DMM Data7
34 LVDS_3M LVDS data pair 3 negative
35 DP8 DMM Data8
36 GND Ground
37 DP9 DMM Data9
38 LVDS_2P LVDS data pair 2 positive
39 DP10 DMM Data10
40 LVDS_2M LVDS data pair 2 negative
41 DP11 DMM Data11
42 GND Ground
43 DP12 DMM Data12
44 LVDS_CLKP LVDS clock pair positive
45 DP13 DMM Data13
46 LVDS_CLKM LVDS clock pair negative
47 DP14 DMM Data14
48 GND Ground
49 DP15 DMM Data15
50 LVDS_1P LVDS data pair 1 positive
51 SDA Serial Data
52 LVDS_1M LVDS data pair 1 negative
53 SCL Serial clock
54 GND Ground
55 RS232RX UART data receive
56 LVDS_0P LVDS data pair 0 positive
57 RS232TX UART data transmit
58 LVDS_0M LVDS data pair 0 negative
59 MCU_RSTn Reset input to xWR1xxx EVM
60 GND Ground
Figure 14. J3 High Density Interface Connector

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2.6 Switches, Push Buttons, and LEDs
2.6.1 Switches
The DCA1000EVM supports a 1×3 DIP switch (as explained in Table 7) and a 1×8 DIP switch (as
explained in Table 8) for mode selection and other functions. In switch SW2, Pin5 indicates that the
DCA1000EVM is configured either by a hardware switch-based configuration, or by a software-based
configuration, as listed in Table 6.
Table 6. Switch2.5 Functionality Information
Reference Usage Description
SW2.5 CONFIG_VIA_HW When positioned at 5 (Pin5), the DCA1000EVM is configured as per the
settings of the hardware DIP switch SW2.
In hardware configuration mode, software configurations are ignored
CONFIG_VIA_SW When positioned at the other side (Pin12), the DCA1000EVM is
configured through the software configuration commands over Ethernet.
In software configuration mode, hardware DIP settings are ignored.
When the DCA1000EVM is configured in hardware switch configuration mode, use the following switch
settings for different modes of data capture.
Table 7. Switch1 Functionality Information
LVDS bit Setting Switch SW1 (3 Position Switch) Description
123
LVDS 12-bit mode ON OFF OFF LVDS 12 bit data is captured from the xWR1xxx EVM.
LVDS 14-bit mode OFF ON OFF LVDS 14 bit data is captured from the xWR1xxx EVM.
LVDS 16-bit mode OFF OFF ON LVDS 16 bit data is captured from the xWR1xxx EVM.
Figure 15. Mode Configuration_1
Table 8. Switch2 Functionality Information
Reference Usage Description
SW2.1 LVDS_CAPTURE When positioned at 1(Pin1), the DCA1000EVM is in capture mode. In this
mode, data is received over LVDS and streamed through Ethernet to the PC.
DMM_PLAYBACK When positioned at the other side (Pin16), the DCA1000EVM is in play back
mode.
SW2.2 SD_STORE When positioned at 2 (Pin2), the DCA1000EVM is in capture mode, and data
is saved into the SD card.
ETH_STREAM When positioned at the other side (Pin15), the DCA1000EVM is in capture
mode, and data is streamed over the network to the host PC.
SW2.3 1243_MODE When positioned at 3 (Pin3), the DCA1000EVM captures 4-lane LVDS data.
AR1642_MODE When positioned at the other side (Pin14), the DCA1000EVM captures 2-
lane LVDS data.
SW2.4 RAW_MODE When positioned at 4 (Pin4), the DCA1000EVM is in raw mode. In this mode,
all LVDS data is captured as it is.
DATA_MODE When positioned at the other side (Pin13), the DCA1000EVM is in data
separated mode. In this mode, the user can add specific headers to different
data types, and FPGA separates out different data types based on the
header.

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Table 8. Switch2 Functionality Information (continued)
Reference Usage Description
SW2.6 USER_SW1
(Using EEPROM configuration) When positioned at 6 (Pin6), the Ethernet configuration data is read from EEPROM, and the same is used for Ethernet communication.
GND
(Using FPGA configuration) When positioned at the other side (Pin11), the Ethernet configuration data hardcoded in FPGA is used for Ethernet communication.
SW2.7 USER_SW2 Future use
GND
SW2.8 USER_SW3 Future use
GND
Figure 16. Mode Configuration_2
2.6.2 Push Buttons
The DCA1000EVM supports four push buttons for FPGA reset, data capture start, and other basic
functions listed in Table 9.
Table 9. Push Button Functionality Information
Reference Usage Description
SW4 PROGRAMN Whenever SPI flash is re-flashed or reprogrammed, press the PROGAMN
(SW4) button to program the FPGA from SPI flash.
Note: A binary file should be present in the SPI flash.
SW5 Capture start When the DCA1000EVM is in hardware configuration mode, press the
capture start (SW5) button to initiate the data transfer. Press the button
(SW5) again to stop the data transfer.
SW6 SPARE_GPIO_SW Future use
SW7 FPGA_RST Press the FPGA_RST button to reset the FPGA.
Figure 17. Push Button
2.6.3 LEDs
The DCA1000EVM supports LEDs for user indications, as listed in Table 10.

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Table 10. LED Functionality Information
Reference Usage Description Color
LD1 DATA_TRANS_PROG_LED1 This LED indicates the progress of data transfer, either
through the network or saving into the SD card. Green
LD2 SD_DETECT_LED5 When the SD card is mounted into the DCA1000EVM, this
LED indicates whether the SD card is detected or not. Green
LD3 SD_FULL_LED0 This LED indicates the full condition of the SD card. Red
LD4 SPARE_LED8 Future use Green
LD5 FPGA_ERR_LED2 When LVDS data is coming at high rate, the internal FPGA
buffer gets full. In that case, this LED glows. Red
LD6 DDR_FULL_LED7 This LED indicates the full condition of the 2GB DDR3
memory. Red
LD7 LVDS_PATH_ERR_LED3 This LED indicates whether the xWR1xxx EVM is sending
LVDS data or not. Red
LD8 HEADER_ERR_LED4 This LED indicates the failure of the header when the
DCA1000EVM is in data separated mode. Red
LD9 EEPROM_RD_FAIL_LED6 This LED indicates an EEPROM read access failure. Red
LD10 5V This LED indicates the presence of the 5-V supply in the
DCA1000EVM. Green
LD11 PROGRAMN This LED indicates assertion of the program to FPGA
when the PROGRAMN button is pressed. Red
LD12 INITN This LED indicates that the FPGA is ready to be
configured. Red
LD13 FPGA_RST This LED indicates the assertion of the FPGA reset. Red
LD14 DONE When FPGA is programmed from SPI flash, this LED
glows. Green
LD15 FTDI_JTAG_ACT This LED indicates activity on the FPGA JTAG
connectivity. Green
Figure 18. User LEDs

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3 System Setup
Figure 19. Board Setup
3.1 Prerequisites
• The DCA1000EVM should be connected to the host PC through an Ethernet cable for the data transfer
process.
• The DCA1000EVM should be connected to a PC through a USB cable (J1-Radar FTDI) for configuring
the xWR1xxx EVM if the mmWave Studio is used to configure the radar device. If an embedded
application is used to configure the xWR1xxx EVM, then this is not required.
• The DCA1000EVM should be connected to TI's xWR1xxx EVM through a 60-pin HD connector by
using a 60-pin Samtec ribbon cable.
• The DCA1000EVM power input should be connected from either a DC jack or TI's xWR1xxx EVM
power output (from a 60-pin HD connector) by selecting the SW3 switch position.
• The xWR1xxx EVM should be connected to a PC through a USB cable (J8) for the RS232 connection
in the Radar Studio interface.
• HOST PC configuration:
– Intel Core i5 2.5 GHz or above
– 8 GB RAM or above
– Windows 10 Pro operating system
– Static IP Address – 192.168.33.30
– 1-Gbps Ethernet port
• Pre-installed mmWave Studio in the mmWave Studio user guide..
• The DCA1000EVM should be connected to a PC through a USB cable (J4-FPGA JTAG) for
programming the FPGA (when the card is in programming mode).

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4 DCA1000EVM Ethernet Configuration Data
The DCA1000EVM stores the default Ethernet configuration data (such as DCA1000EVM IP,
DCA1000EVM MAC, System IP, Configuration port, and Data port) in FPGA internal registers.
The default Ethernet configuration data stored in the FPGA internal registers are listed in Table 11.
Table 11. Table 11 Default Value Stored in FPGA Registers
Parameter Default Value (Decimal)
FPGA IP 192.168.33.180
FPGA MAC 12-34-56-78-90-12
System IP 192.168.33.30
Configuration port 4096
ADC/CP_ADC/ADC_CP/CP_ADC_CQ data 4098
CP data 4099
CQ data 4100
R4F debug data 4101
DSP debug data 4102
The DCA1000EVM has option of loading Ethernet configuration data from EEPROM or the FPGA internal
register, based on SW2.6.
The Ethernet configuration data is loaded from the EEPROM when SW2 positioned at 6 (pin6); else,
FPGA register values are loaded.
Loading the Ethernet configuration data from EEPROM:
• When SW2 is positioned at 6 (pin6), the DCA1000EVM loads the Ethernet configuration data from
EEPROM.
• In general, the EEPROM is blank when the DCA1000EVM comes out of the factory. The EEPROM
remains blank until the updated EEPROM command is given to the DCA1000EVM through the
Ethernet port.
• When the updated EEPROM command is given to the DCA1000EVM, the Ethernet configuration data
are stored into the EEPROM along with the header and footer.
• The DCA1000EVM requires a power cycle/hardware reset to load the updated Ethernet configuration
data from the EEPROM.
• During the power ON/after hardware reset, the DCA1000EVM FPGA loads the Ethernet configuration
data from the EEPROM and checks for the header and footer. If the header and footer are found, the
data loaded from the EEPROM is used for Ethernet communication; else, the FPGA uses the default
values stored in the internal registers.
• The Ethernet configuration data updated in the EEPROM should be used in the Ethernet packets
which are going as commands to the DCA1000EVM, for further communication. Otherwise, the
DCA1000EVM will not respond to the command.
Loading the Ethernet configuration data from the FPGA internal registers:
• When SW2 is positioned at (pin11), the DCA1000EVM loads the default Ethernet configuration data
from the FPGA internal registers, and the same is used for Ethernet communication.
NOTE: For data separated mode, the DCA1000EVM FPGA receives only one data port number
from the updated EEPROM command. This port is considered as an ADC data port, and
other data type’s port number is incremented by one.
NOTE: Whenever Switch 2.6 position is changed from one option to another option, the
DCA1000EVM requires a power cycle and hardware reset.

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5 DCA1000EVM Command and Data Format
The DCA1000EVM follows UDP protocol and supports 14 predefined commands. The configuration and
status of the DCA1000EVM are communicated through the configuration port. The data port is used to
transfer raw mode/data separated mode data.
5.1 DCA1000EVM Command Format
The DCA1000EVM receives a command from the host through the configuration port, and sends back the
response in the same port.
The Command Request protocol consists of the following:
• Header
a. Header
b. Command code
c. Data size
• Data
• Footer
The Command Response protocol consists of the following:
• Header
a. Header
b. Command code
• Status
• Footer
Commands supported in the DCA1000EVM are listed in Table 12.
Table 12. Supported Commands
Command Command Code
RESET_FPGA_CMD_CODE 0x01
RESET_AR_DEV_CMD_CODE 0x02
CONFIG_FPGA_GEN_CMD_CODE 0x03
CONFIG_EEPROM_CMD_CODE 0x04
RECORD_START_CMD_CODE 0x05
RECORD_STOP_CMD_CODE 0x06
PLAYBACK_START_CMD_CODE 0x07
PLAYBACK_STOP_CMD_CODE 0x08
SYSTEM_CONNECT_CMD_CODE 0x09
SYSTEM_ERROR_CMD_CODE 0x0A
CONFIG_PACKET_DATA_CMD_CODE 0x0B
CONFIG_DATA_MODE_AR_DEV_CMD_CODE 0x0C

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Table 12. Supported Commands (continued)
Command Command Code
INIT_FPGA_PLAYBACK_CMD_CODE 0x0D
READ_FPGA_VERSION_CMD_CODE 0x0E
Table 13 and Table 14 show examples using RESET_FPGA_CMD_CODE.
Table 13. Reset FPGA Command Request From Host
Name Data Type Number of
Bytes Default Value Min Value Max Value Description
Header UINT16 2 0xA55A - - 0xA55A always. Start bits of
packet.
Command code UINT16 2 0x01 - - Command code
Size UINT16 2 0 - - Data size
Footer UINT16 2 0xEEAA - - 0xEEAA always. Stop bits of
packet.
Table 14. Command Response From the DCA1000EVM
Name Data Type Number of
Bytes Default Value Min Value Max Value Description
Header UINT16 2 0xA55A - - 0xA55A always. Start bits of
packet.
Command code UINT16 2 0x01 - - Command code
Status UINT16 2 0 0 1 0 – Success
1 – Failure
Footer UINT16 2 0xEEAA - - 0xEEAA always. Stop bits of
packet.
5.2 DCA1000EVM Data Format
The DCA1000EVM sends raw mode/data separated mode data to the host through the data port.
• Raw mode data format: the DCA1000EVM sends raw mode data in the following format.
• Data separated mode data format: the DCA1000EVM sends data separated mode data in the following
format.

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DCA1000EVM Data Capture Card
5.3 Stored File Format
Raw mode data format: in raw mode, the file is stored in the following format:
• Without sequence number:
• With sequence number:
Data separated mode data format: in data separated mode, the file is stored in the following format:
• Without sequence number:
• With sequence number:
6 Use Case: LVDS Over Ethernet Streaming
LVDS over Ethernet streaming can be used in two modes of operations: raw mode and data separated
mode. Both can be accessed either through the hardware switch configuration mode or software GUI
configuration mode by selecting the switch (SW2.5).
6.1 Raw Mode
In Raw mode, the FPGA records all the data appearing on the LVDS lines as is. The data sent over the
LVDS lanes is controlled by either the configuration from the mmwave studio, or the user application
running on the radar device.
6.2 Data Separated Mode
Data separated mode features supports for receiving different data types with unique identifiers, along with
length field information from the xWR1xxx EVM over the LVDS interface, and streamed over the Ethernet
interface in different ports. This mode of capture supports specific identifiers, as listed in Table 15. Each
data type has a 64-bit identifier and 64-bit length field. In the length field, the actual length information is
only 24 bits (the first 12 bits are taken from the first sample and the next 12 bits from the second sample).
The remaining 40 bits are reserved. The user application on the radar device must ensure that these
headers are added on the LVDS data in the exact format the FPGA expects.