Texas Instruments CI2EVM BoC User manual

Users Guide
August 2011
Revision 0.4 – preliminary Page 1 of 31
Texas Instruments Dual EVM BoC Card
- Quick Start Guide
High Density Multiprocessor DSP’s
Abstract
This document is provided as a quick start guide for using the Texas Instruments BoC
(Break out Card). The breakout card is intended to provide communication support between
Texas Instruments EVM’s which contain an AMC B+ interface. The EVM BoC is intended
to support EVM to EVM communication for SRIO, PCIe, SGMII, and AIF.
Table of Contents
Abstract...........................................................................................................................................................................1
Table of Contents ...........................................................................................................................................................1
Table of Figures..............................................................................................................................................................2
Table of Tables...............................................................................................................................................................2
I. OVERVIEW...........................................................................................................................................................3
I. Introduction......................................................................................................................................................3
II. Hardware Description......................................................................................................................................3
II. Hardware Configuration.......................................................................................................................................6
I. Initial Installation Procedure...........................................................................................................................6
II. Default Jumper and Pin Settings......................................................................................................................6
III. BoC Logic Power Source Selection [20]..........................................................................................................6
IV. EVM Power Source [16, 17, 18]......................................................................................................................7
V. Emulation Interface [1]....................................................................................................................................8
VI. SGMII Interface ...............................................................................................................................................8
VII. PCIE Interface .................................................................................................................................................8
VIII. SRIO (Serial RapidIO) Interface......................................................................................................................9
IX. AIF (Antenna Interface) Interface....................................................................................................................9
X. I2C interface [5, 9, 11, 23]...............................................................................................................................9
XI. Common REFCLK Source .............................................................................................................................10
a. REFCLK Oscillator Enable Header [19].......................................................................................................10
b. REFCLK Signal Levels...................................................................................................................................10
XII. Timer0 Output Headers [12, 22]....................................................................................................................12
XIII. Timer0 Input Header [10, 24]........................................................................................................................12
XIV. Common RP1CLK Source..............................................................................................................................12
a. RP1CLK Oscillator Enable Header [8].........................................................................................................12
b. RP1CLK Signal Levels...................................................................................................................................13
c. Alternate RP1CLK Inputs [15].......................................................................................................................14
XV. Common TCLK_B Source..............................................................................................................................14
a. TCLK_B Oscillator Enable Header [14] .......................................................................................................14
b. TCLK_B Signal Outputs [2, 13].....................................................................................................................15
c. TCLK_A Signal Outputs [2, 13].....................................................................................................................16
XVI. Common PCIeREFCLK Source [25] .............................................................................................................17

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Board A
SGMII [1]
TDO Output from Brd A to Brd B
Board A
JTAG Interface
Board A
Clocks
Board A
SGMII [0] Board A
RP1CLK
Board A
AIF[0:5]
Board A
AIF CLK & FS
Board A
Expansion I2C
Board A
SRIO[1:4]
Board A
PCIe[4:7]
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
FROM EVM A
TO EVM A
TO EVM A
TO EVM A
TO EVM A
TO EVM A
CONNECTOR REFLECTS BACKPLANE PIN OUTS
TDI
TDO_2_TDI
TRST#
TMS
TCK
A_AMC0_SGMII1_TX_DP
A_AMC0_SGMII1_TX_DN
A_AMC0_SGMII1_RX_DP
A_AMC0_SGMII1_RX_DN
A_DSP_RP1CLKN
A_DSP_RP1CLKP
A_AMCC_P7_PCIe_RX2P
A_AMCC_P7_PCIe_RX2N
A_AMCC_P6_PCIe_RX1P
A_AMCC_P6_PCIe_RX1N
A_AMCC_P7_PCIe_TX2P
A_AMCC_P7_PCIe_TX2N
A_AMCC_P6_PCIe_TX1P
A_AMCC_P6_PCIe_TX1N
A_AMCC_P13_AIF1_RXN
A_AMCC_P13_AIF1_RXP
A_AMCC_P13_AIF1_TXP
A_AMCC_P13_AIF1_TXN
A_AMCC_P14_AIF2_RXP
A_AMCC_P14_AIF2_RXN
A_AMCC_P14_AIF2_TXP
A_AMCC_P14_AIF2_TXN
A_AMCC_P15_AIF3_RXP
A_AMCC_P15_AIF3_RXN
A_AMCC_P15_AIF3_TXP
A_AMCC_P15_AIF3_TXN
A_AMCC_P12_AIF0_RXN
A_AMCC_P12_AIF0_RXP
A_AMCC_P12_AIF0_TXP
A_AMCC_P12_AIF0_TXN
A_AMCC_P17_AIF4_RXP
A_AMCC_P17_AIF4_RXN
A_AMCC_P17_AIF4_TXP
A_AMCC_P17_AIF4_TXN
A_AMCC_P18_AIF5_RXP
A_AMCC_P18_AIF5_RXN
A_AMCC_P18_AIF5_TXP
A_AMCC_P18_AIF5_TXN
A_AMC0_SGMII0_TX_DP
A_AMC0_SGMII0_TX_DN
A_AMCC_P11_SRIO4_RXN
A_AMCC_P11_SRIO4_RXP
A_AMCC_P9_SRIO2_TXN
A_AMCC_P9_SRIO2_TXP
A_AMCC_P10_SRIO3_RXP
A_AMCC_P10_SRIO3_RXN
A_AMCC_P8_SRIO1_TXN
A_AMCC_P8_SRIO1_TXP
A_AMCC_P9_SRIO2_RXP
A_AMCC_P9_SRIO2_RXN
A_AMCC_P11_SRIO4_TXP
A_AMCC_P11_SRIO4_TXN
A_AMCC_P8_SRIO1_RXP
A_AMCC_P8_SRIO1_RXN
A_AMCC_P10_SRIO3_TXP
A_AMCC_P10_SRIO3_TXN
A_PCIE_REF_CLK_P
A_AMC0_SGMII0_RX_DP
A_AMC0_SGMII0_RX_DN
A_PCIE_REF_CLK_N
A_AMCC_P5_PCIe_RX2P
A_AMCC_P5_PCIe_RX2N
A_AMCC_P4_PCIe_RX1P
A_AMCC_P4_PCIe_RX1N
A_AMCC_P5_PCIe_TX2P
A_AMCC_P5_PCIe_TX2N
A_AMCC_P4_PCIe_TX1P
A_AMCC_P4_PCIe_TX1N
A_TCLKA_P
A_TCLKA_N
A_TCLKB_P
A_TCLKB_N
A_REFCLK_P
A_REFCLK_N
A_TIMEROUT_0
A_TIMERIN_0
A_RP1FBP
A_RP1FBN
A_DSP_SDA_AMC
A_DSP_SCL_AMC
A_PHYSYNC
A_RADSYNC
A_VCC12
INB_AMC0_SGMII1_TX_DP4 INB_AMC0_SGMII1_TX_DN4
OUT
A_AMC0_SGMII1_TX_DP4 OUT
A_AMC0_SGMII1_TX_DN4
IN TDI 7
OUT TDO_2_TDI 4
IN TRST# 4,7
IN TMS 4,7
IN A_TCK 7
IN A_DSP_RP1CLKN 5
IN A_DSP_RP1CLKP 5
OUT
A_AMCC_P6_PCIe_TX1P4 OUT
A_AMCC_P6_PCIe_TX1N4
INB_AMCC_P6_PCIe_TX1P4 INB_AMCC_P6_PCIe_TX1N4
INB_AMCC_P7_PCIe_TX2P4 INB_AMCC_P7_PCIe_TX2N4
OUT
A_AMCC_P7_PCIe_TX2P4 OUT
A_AMCC_P7_PCIe_TX2N4
INB_AMC0_SGMII0_TX_DP4 INB_AMC0_SGMII0_TX_DN4
OUT
A_AMC0_SGMII0_TX_DP4 OUT
A_AMC0_SGMII0_TX_DN4
OUT
A_AMCC_P4_PCIe_TX1P4 OUT
A_AMCC_P4_PCIe_TX1N4
INB_AMCC_P4_PCIe_TX1P4 INB_AMCC_P4_PCIe_TX1N4
INB_AMCC_P5_PCIe_TX2P4 INB_AMCC_P5_PCIe_TX2N4
OUT
A_AMCC_P5_PCIe_TX2P4 OUT
A_AMCC_P5_PCIe_TX2N4
INA_TCLKA_P5 INA_TCLKA_N5
INA_TCLKB_P5 INA_TCLKB_N5
INA_PCIE_REF_CLK_P5 INA_PCIE_REF_CLK_N5
IN A_RP1FBN 6
IN A_RP1FBP 6
IN A_RADSYNC 6
IN A_PHYSYNC 6
IN B_AMCC_P18_AIF5_TXN 4
IN B_AMCC_P18_AIF5_TXP 4
OUT A_AMCC_P17_AIF4_TXP 4
OUT A_AMCC_P17_AIF4_TXN 4
IN B_AMCC_P17_AIF4_TXN 4
IN B_AMCC_P17_AIF4_TXP 4
OUT A_AMCC_P18_AIF5_TXP 4
OUT A_AMCC_P18_AIF5_TXN 4
OUT A_AMCC_P15_AIF3_TXP 4
OUT A_AMCC_P15_AIF3_TXN 4
OUT A_AMCC_P14_AIF2_TXP 4
OUT A_AMCC_P14_AIF2_TXN 4
IN B_AMCC_P15_AIF3_TXN 4
IN B_AMCC_P15_AIF3_TXP 4
OUT A_AMCC_P13_AIF1_TXP 4
OUT A_AMCC_P13_AIF1_TXN 4
IN B_AMCC_P14_AIF2_TXN 4
IN B_AMCC_P14_AIF2_TXP 4
OUT A_AMCC_P12_AIF0_TXP 4
OUT A_AMCC_P12_AIF0_TXN 4
IN B_AMCC_P13_AIF1_TXN 4
IN B_AMCC_P13_AIF1_TXP 4
IN B_AMCC_P12_AIF0_TXN 4
IN B_AMCC_P12_AIF0_TXP 4
OUT A_AMCC_P11_SRIO4_TXP 4
OUT A_AMCC_P11_SRIO4_TXN 4
IN B_AMCC_P11_SRIO4_TXP 4
IN B_AMCC_P11_SRIO4_TXN 4
OUT A_AMCC_P10_SRIO3_TXP 4
OUT A_AMCC_P10_SRIO3_TXN 4
IN B_AMCC_P10_SRIO3_TXP 4
IN B_AMCC_P10_SRIO3_TXN 4
OUT A_AMCC_P9_SRIO2_TXP 4
OUT A_AMCC_P9_SRIO2_TXN 4
IN B_AMCC_P9_SRIO2_TXP 4
IN B_AMCC_P9_SRIO2_TXN 4
OUT A_AMCC_P8_SRIO1_TXP 4
OUT A_AMCC_P8_SRIO1_TXN 4
IN B_AMCC_P8_SRIO1_TXP 4
IN B_AMCC_P8_SRIO1_TXN 4
BI A_AMC_EXP_SDA 6
OUT A_TIMERIN_0 6
IN A_AMC_EXP_SCL 6
IN A_TIMEROUT_0 6
IN A_REFCLK_N 7
IN A_REFCLK_P 7
Title
Size Document Number Rev
Date: Sheet of
<Doc> E
LC_2-EVM_BoC-0002 - Board B Interface
B
310Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> E
LC_2-EVM_BoC-0002 - Board B Interface
B
310Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> E
LC_2-EVM_BoC-0002 - Board B Interface
B
310Friday, September 09, 2011
R3 DNI
R4 DNI
R5 0
R6 0
A1
AMC_BACKPLANE_CONNECTOR
<Characteristic>
GND_1
1
GND_2
7
GND_3
10
PWR_12V_1
2
PS1
3
MP
4
GA0
5
RSRVD6
6
RSRVD8
8
PWR_12V_2
9
Rx0+
11
Rx0-
12
GND_4
13
Tx0+
14
Tx0-
15
GND_5
16
GA1
17
PWR_12V_3
18
GND_6
19
Rx1+
20
Rx1-
21
GND_7
22
Tx1+
23
Tx1-
24
GND_8
25
GA2
26
PWR_12V_4
27
GND_9
28
Rx2+
29
Rx2-
30
GND_10
31
Tx2+
32
Tx2-
33
GND_11
34
Rx3+
35
Rx3-
36
GND_12
37
Tx3+
38
Tx3-
39
GND_13
40
ENABLE
41
PWR_12V_5
42
GND_14
43
Rx4+
44
Rx4-
45
GND_15
46
Tx4+
47
Tx4-
48
GND_16
49
Rx5+
50
Rx5-
51
GND_17
52
Tx5+
53
Tx5-
54
GND_18
55
SCL_L
56
GND_19
58
Rx6+
59
Rx6-
60
GND_20
61
Tx6+
62
Tx6-
63
GND_21
64
Rx7+
65
Rx7-
66
GND_22
67
Tx7+
68
Tx7-
69
GND_23
70
SDA_L
71
PWR_12V_6
57
PWR_12V_7
72
GND_24
73
TCLKA+
74
TCLKA-
75
GND_25
76
TCLKB+
77
TCLKB-
78
GND_26
79
FCLKA+
80
FCLKA-
81
GND_27
82
PS0
83
PWR_12V_8
84
GND_28
85 GND_29 86
Tx8- 87
Tx8+ 88
Rx8+ 91
Rx8- 90
GND_30 89
Tx9+ 94
Tx9- 93
GND_31 92
Rx9+ 97
Rx9- 96
GND_32 95
Tx10+ 100
Tx10- 99
GND_33 98
Rx10+ 103
Rx10- 102
GND_34 101
Tx11+ 106
Tx11- 105
GND_35 104
Rx11+ 109
Rx11- 108
GND_36 107
Tx12+ 112
Tx12- 111
GND_37 110
Rx12+ 115
Rx12- 114
GND_38 113
Tx13+ 118
Tx13- 117
GND_39 116
Rx13+ 121
Rx13- 120
GND_40 119
Tx14+ 124
Tx14- 123
GND_41 122
Rx14+ 127
Rx14- 126
GND_42 125
GND_43 128
Tx15+ 130
Tx15- 129
GND_44 131
Rx15- 132
Rx15+ 133
GND_45 134
TCLKC+ 136
TCLKC- 135
TCLKD+ 139
TCLKD- 138
GND_46 137
Tx17+ 142
Tx17- 141
GND_47 140
Rx17+ 145
Rx17- 144
GND_48 143
Rx18+ 151
Rx18- 150
GND_50 149
Tx18+ 148
Tx18- 147
GND_49 146
Rx19+ 157
Rx19- 156
GND_52 155
Tx19+ 154
Tx19- 153
GND_51 152
Rx20+ 163
Rx20- 162
GND_54 161
Tx20+ 160
Tx20- 159
GND_53 158
GND_55 164
TCK 165
TMS 166
TRST 167
TDO 168
TDI 169
GND_56 170
R1 0
R2 0

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Board B
SGMII [1]
TDO Output from Brd A, TDI Input to Brd B
Board B
JTAG Interface
Board B
Clocks
Board B
SGMII [0]
Board B
PCIe[4:7]
Board B
RP1CLK
Board B
AIF[0:5]
Board B
AIF CLK & FS
Board B
Expansion I2C
Board B
SRIO[1:4]
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
FROM EVM B
TO EVM B
TO EVM B
TO EVM B
TO EVM B
TDO_2_TDI
TDO
TRST#
TMS
TCK
B_AMC0_SGMII1_TX_DP
B_AMC0_SGMII1_TX_DN
B_AMC0_SGMII1_RX_DP
B_AMC0_SGMII1_RX_DN
B_AMC0_SGMII0_RX_DP
B_AMC0_SGMII0_RX_DN
B_AMCC_P7_PCIe_RX2P
B_AMCC_P7_PCIe_RX2N
B_AMCC_P6_PCIe_RX1P
B_AMCC_P6_PCIe_RX1N
B_AMCC_P7_PCIe_TX2P
B_AMCC_P7_PCIe_TX2N
B_AMCC_P6_PCIe_TX1P
B_AMCC_P6_PCIe_TX1N
B_DSP_RP1CLKN
B_DSP_RP1CLKP
B_AMCC_P13_AIF1_RXN
B_AMCC_P13_AIF1_RXP
B_AMCC_P13_AIF1_TXP
B_AMCC_P13_AIF1_TXN
B_AMCC_P14_AIF2_RXP
B_AMCC_P14_AIF2_RXN
B_AMCC_P14_AIF2_TXP
B_AMCC_P14_AIF2_TXN
B_AMCC_P15_AIF3_RXP
B_AMCC_P15_AIF3_RXN
B_AMCC_P15_AIF3_TXP
B_AMCC_P15_AIF3_TXN
B_AMCC_P12_AIF0_RXN
B_AMCC_P12_AIF0_RXP
B_AMCC_P12_AIF0_TXP
B_AMCC_P12_AIF0_TXN
B_AMCC_P17_AIF4_RXP
B_AMCC_P17_AIF4_RXN
B_AMCC_P17_AIF4_TXP
B_AMCC_P17_AIF4_TXN
B_AMCC_P18_AIF5_RXP
B_AMCC_P18_AIF5_RXN
B_AMCC_P18_AIF5_TXP
B_AMCC_P18_AIF5_TXN
B_AMC0_SGMII0_TX_DP
B_AMC0_SGMII0_TX_DN
B_AMCC_P11_SRIO4_RXN
B_AMCC_P11_SRIO4_RXP
B_AMCC_P9_SRIO2_TXN
B_AMCC_P9_SRIO2_TXP
B_AMCC_P10_SRIO3_RXP
B_AMCC_P10_SRIO3_RXN
B_AMCC_P8_SRIO1_TXN
B_AMCC_P8_SRIO1_TXP
B_AMCC_P9_SRIO2_RXP
B_AMCC_P9_SRIO2_RXN
B_AMCC_P11_SRIO4_TXP
B_AMCC_P11_SRIO4_TXN
B_AMCC_P8_SRIO1_RXP
B_AMCC_P8_SRIO1_RXN
B_AMCC_P10_SRIO3_TXP
B_AMCC_P10_SRIO3_TXN
B_PCIE_REF_CLK_P
B_PCIE_REF_CLK_N
B_AMCC_P5_PCIe_RX2P
B_AMCC_P5_PCIe_RX2N
B_AMCC_P4_PCIe_RX1P
B_AMCC_P4_PCIe_RX1N
B_AMCC_P5_PCIe_TX2P
B_AMCC_P5_PCIe_TX2N
B_AMCC_P4_PCIe_TX1P
B_AMCC_P4_PCIe_TX1N
B_TCLKA_P
B_TCLKA_N
B_TCLKB_P
B_TCLKB_N
B_REFCLK_P
B_REFCLK_N
B_TIMEROUT_0
B_TIMERIN_0
B_RP1FBP
B_RP1FBN
B_EXP_SDA
B_EXP_SCL
B_PHYSYNC
B_RADSYNC
B_VCC12
INA_AMC0_SGMII1_TX_DP3 INA_AMC0_SGMII1_TX_DN3
OUT
B_AMC0_SGMII1_TX_DP3
IN TDO_2_TDI 3
OUT
B_AMC0_SGMII1_TX_DN3
OUT TDO 7
IN TRST# 3,7
IN TMS 3,7
IN B_TCK 7
OUT
B_AMCC_P6_PCIe_TX1P3 OUT
B_AMCC_P6_PCIe_TX1N3
OUT
B_AMCC_P7_PCIe_TX2P3 OUT
B_AMCC_P7_PCIe_TX2N3
INA_AMCC_P7_PCIe_TX2P3 INA_AMCC_P7_PCIe_TX2N3
INA_AMCC_P6_PCIe_TX1P3 INA_AMCC_P6_PCIe_TX1N3
IN B_DSP_RP1CLKN 5
IN B_DSP_RP1CLKP 5
BI B_AMC_EXP_SDA 6
IN B_AMC_EXP_SCL 6
OUT B_TIMERIN_0 6
IN B_TIMEROUT_0 6
IN B_REFCLK_N 7
IN B_REFCLK_P 7
INA_AMC0_SGMII0_TX_DP3 INA_AMC0_SGMII0_TX_DN3
OUT
B_AMC0_SGMII0_TX_DP3 OUT
B_AMC0_SGMII0_TX_DN3
OUT
B_AMCC_P4_PCIe_TX1P3 OUT
B_AMCC_P4_PCIe_TX1N3
OUT
B_AMCC_P5_PCIe_TX2P3 OUT
B_AMCC_P5_PCIe_TX2N3
INA_AMCC_P5_PCIe_TX2P3 INA_AMCC_P5_PCIe_TX2N3
INA_AMCC_P4_PCIe_TX1P3 INA_AMCC_P4_PCIe_TX1N3
INB_PCIE_REF_CLK_P5 INB_PCIE_REF_CLK_N5
INB_TCLKA_P5 INB_TCLKA_N5
INB_TCLKB_P5 INB_TCLKB_N5
IN B_RP1FBN 6
IN B_RP1FBP 6
IN B_RADSYNC 6
IN B_PHYSYNC 6
IN A_AMCC_P18_AIF5_TXN 3
IN A_AMCC_P18_AIF5_TXP 3
IN A_AMCC_P17_AIF4_TXP 3
IN A_AMCC_P17_AIF4_TXN 3
OUT B_AMCC_P17_AIF4_TXP 3
OUT B_AMCC_P17_AIF4_TXN 3
OUT B_AMCC_P18_AIF5_TXP 3
OUT B_AMCC_P18_AIF5_TXN 3
IN A_AMCC_P14_AIF2_TXP 3
IN A_AMCC_P14_AIF2_TXN 3
OUT B_AMCC_P14_AIF2_TXP 3
OUT B_AMCC_P14_AIF2_TXN 3
IN A_AMCC_P15_AIF3_TXN 3
IN A_AMCC_P15_AIF3_TXP 3
OUT B_AMCC_P15_AIF3_TXP 3
OUT B_AMCC_P15_AIF3_TXN 3
IN A_AMCC_P12_AIF0_TXP 3
IN A_AMCC_P12_AIF0_TXN 3
OUT B_AMCC_P12_AIF0_TXP 3
OUT B_AMCC_P12_AIF0_TXN 3
IN A_AMCC_P13_AIF1_TXN 3
IN A_AMCC_P13_AIF1_TXP 3
OUT B_AMCC_P13_AIF1_TXP 3
OUT B_AMCC_P13_AIF1_TXN 3
OUT B_AMCC_P11_SRIO4_TXP 3
OUT B_AMCC_P11_SRIO4_TXN 3
IN A_AMCC_P11_SRIO4_TXP 3
IN A_AMCC_P11_SRIO4_TXN 3
OUT B_AMCC_P10_SRIO3_TXP 3
OUT B_AMCC_P10_SRIO3_TXN 3
IN A_AMCC_P10_SRIO3_TXP 3
IN A_AMCC_P10_SRIO3_TXN 3
OUT B_AMCC_P9_SRIO2_TXP 3
OUT B_AMCC_P9_SRIO2_TXN 3
IN A_AMCC_P9_SRIO2_TXP 3
IN A_AMCC_P9_SRIO2_TXN 3
OUT B_AMCC_P8_SRIO1_TXP 3
OUT B_AMCC_P8_SRIO1_TXN 3
IN A_AMCC_P8_SRIO1_TXP 3
IN A_AMCC_P8_SRIO1_TXN 3
Title
Size Document Number Rev
Date: Sheet of
<Doc> E
LC_2-EVM_BoC-0002 - Board B Interface
B
410Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> E
LC_2-EVM_BoC-0002 - Board B Interface
B
410Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> E
LC_2-EVM_BoC-0002 - Board B Interface
B
410Friday, September 09, 2011
R11 0
R12 0
R7 0R8 DNI
R9 0
B1
AMC_BACKPLANE_CONNECTOR
<Characteristic>
GND_1
1
GND_2
7
GND_3
10
PWR_12V_1
2
PS1
3
MP
4
GA0
5
RSRVD6
6
RSRVD8
8
PWR_12V_2
9
Rx0+
11
Rx0-
12
GND_4
13
Tx0+
14
Tx0-
15
GND_5
16
GA1
17
PWR_12V_3
18
GND_6
19
Rx1+
20
Rx1-
21
GND_7
22
Tx1+
23
Tx1-
24
GND_8
25
GA2
26
PWR_12V_4
27
GND_9
28
Rx2+
29
Rx2-
30
GND_10
31
Tx2+
32
Tx2-
33
GND_11
34
Rx3+
35
Rx3-
36
GND_12
37
Tx3+
38
Tx3-
39
GND_13
40
ENABLE
41
PWR_12V_5
42
GND_14
43
Rx4+
44
Rx4-
45
GND_15
46
Tx4+
47
Tx4-
48
GND_16
49
Rx5+
50
Rx5-
51
GND_17
52
Tx5+
53
Tx5-
54
GND_18
55
SCL_L
56
GND_19
58
Rx6+
59
Rx6-
60
GND_20
61
Tx6+
62
Tx6-
63
GND_21
64
Rx7+
65
Rx7-
66
GND_22
67
Tx7+
68
Tx7-
69
GND_23
70
SDA_L
71
PWR_12V_6
57
PWR_12V_7
72
GND_24
73
TCLKA+
74
TCLKA-
75
GND_25
76
TCLKB+
77
TCLKB-
78
GND_26
79
FCLKA+
80
FCLKA-
81
GND_27
82
PS0
83
PWR_12V_8
84
GND_28
85 GND_29 86
Tx8- 87
Tx8+ 88
Rx8+ 91
Rx8- 90
GND_30 89
Tx9+ 94
Tx9- 93
GND_31 92
Rx9+ 97
Rx9- 96
GND_32 95
Tx10+ 100
Tx10- 99
GND_33 98
Rx10+ 103
Rx10- 102
GND_34 101
Tx11+ 106
Tx11- 105
GND_35 104
Rx11+ 109
Rx11- 108
GND_36 107
Tx12+ 112
Tx12- 111
GND_37 110
Rx12+ 115
Rx12- 114
GND_38 113
Tx13+ 118
Tx13- 117
GND_39 116
Rx13+ 121
Rx13- 120
GND_40 119
Tx14+ 124
Tx14- 123
GND_41 122
Rx14+ 127
Rx14- 126
GND_42 125
GND_43 128
Tx15+ 130
Tx15- 129
GND_44 131
Rx15- 132
Rx15+ 133
GND_45 134
TCLKC+ 136
TCLKC- 135
TCLKD+ 139
TCLKD- 138
GND_46 137
Tx17+ 142
Tx17- 141
GND_47 140
Rx17+ 145
Rx17- 144
GND_48 143
Rx18+ 151
Rx18- 150
GND_50 149
Tx18+ 148
Tx18- 147
GND_49 146
Rx19+ 157
Rx19- 156
GND_52 155
Tx19+ 154
Tx19- 153
GND_51 152
Rx20+ 163
Rx20- 162
GND_54 161
Tx20+ 160
Tx20- 159
GND_53 158
GND_55 164
TCK 165
TMS 166
TRST 167
TDO 168
TDI 169
GND_56 170
R10 DNI

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Board B
Clocks
Board A
Clocks
CLOCK INTERFACE
RP1CLK SMT SMA
--Leave room for wrench--
-must be skew matched between SMA's and U10 input
-NO STUBS
Common PCIe REFCLK
SMT SMA
-Leave room for wrench
-No stubs and all "T's"
must be balanced
Zero stub between CON5/CON4
SMA and U8/U7 Crystal input,
Nets must be identical length
-U7 configured for 100MHz output
U8 is a 25MHz xtal
NOTE: PLACE OSCILLATOR WITH NO STUBS
-U2 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72
-By default leave Disabled
-Oscillator only installed on limited board
-RPICLKP/N nets to be matched length from "T"
-R15:18, 20:23, & 25:28 must be placed close to output
JP1 Default Settings
-Install shunt between 1-2
-Oscillator output is Hi-Z
JP2 Default Settings
-Install shunt
-Oscillator output is Hi-Z
JP3 Default Settings
-Install shunt between 1-2
-Output is Hi-Z
R35 MUST be
placed close
to input pins
of U6
U1 Output is LVPECL
Resistors R20:R23
have been configured
for CML output (mod for LVDS swing)
R24 & R29 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple
R30 must be across pins of U1
FULL SILK SCREENING REQUIRED
R36 & R41 are 0 ohm 0402
resistors, May need to be
changed to 0.01uF
Capacitors to AC couple
U6 Output is LVPECL
Resistors R42:R45
have been configured
for CML output
Zero stub between CON1/CON2
SMA and U2/U1 OScillator input,
Nets must be identical length
NOTE: PLACE OSCILLATOR WITH NO STUBS
-U5 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72
-By default leave Disabled
-RPICLKP/N nets to be matched length from "T"
-R37:40, & 42:49 must be placed close to output
Pay attention to mounting requirements for all clock sources
BRD3V3
BRD3V3
BRD3V3
BRD3V3 BRD3V3
BRD3V3 BRD3V3
BRD3V3
OUTB_TCLKA_P4 OUT
B_TCLKA_N4
OUT A_PCIE_REF_CLK_P 3
OUT A_PCIE_REF_CLK_N 3
OUT A_TCLKA_P 3
OUT A_TCLKA_N 3
OUT
B_TCLKB_P4 OUT
B_TCLKB_N4
OUT
B_PCIE_REF_CLK_P4 OUT
B_PCIE_REF_CLK_N4
OUT
B_DSP_RP1CLKP4 OUT
B_DSP_RP1CLKN4
OUT A_DSP_RP1CLKP 3
OUT A_DSP_RP1CLKN 3
OUT A_TCLKB_N 3
OUT A_TCLKB_P 3
Title
Size Document Number Rev
Date: Sheet of
<Doc> F
LC_2-EVM_BoC-0002 - Control Interface 1
B
510Tuesday, September 13, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> F
LC_2-EVM_BoC-0002 - Control Interface 1
B
510Tuesday, September 13, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> F
LC_2-EVM_BoC-0002 - Control Interface 1
B
510Tuesday, September 13, 2011
C1
0.01µF
R41 0
R26
150
R19
150
U1
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacref
8
OUTP0 9
OUTN0 10
OUTP1 11
OUTN1 12
NC3 13 NC4 14 NC5 15
Gnd1 16
GP 17
R47
150
R46
150
C10
0.1µF
R36 0
R27
150
C11
DNI
R14 27
JP3
HDR_1x2
1
2
R28
150
R42 75
R34 10K
R53 0
CON3
SMA_SMT
G1
2
G2
3
G3 4
G4 5
11
R44 75
JP2
HDR_1x2
1
2
CON4
SMA_SMT
G1
2
G2
3
G3 4
G4 5
11
R43 75
JP1
HDR_1x2
1
2
U2
FXO-LC73
E/D
1
NC
2
GND
3+OUT 4
-OUT 5
Vdd 6
C3 10µF
C7
0.01µF
U6
CDCLVP1102
Gnd0 1
NC0 2
NC1 3
NC2 4
Vcc 5
INP 6
INN 7
Vacref 8
OUTP0
9
OUTN0
10
OUTP1
11
OUTN1
12
NC3
13
NC4
14
NC5
15
Gnd1
16
GP
17
U3 Ferrite
1
122
R21 75
R18
DNI
R13 10K
R40
DNI
R23 75
R16
DNI
R54 475 1%
R33 27
R32 10K
R52
20
R39
DNI
CON2
SMA_SMT
G1 2 G2 3
G3
4
G4
51 1
R38
DNI
R37
DNI
R30 100
U5
FXO-LC73
E/D 1
NC 2
GND 3 +OUT
4-OUT
5Vdd
6
C6 0.01µF
J2
CON4B
1
2
3
4
R24 0
R31 150
R29 0
R45 75
CON1
SMA_SMT
G1 2 G2 3
G3
4
G4
5
1
1
C8
0.01µF
C2 0.1µF
R35 100
R20 75
C5 0.01µF
U4
Ferrite
1
122
J1
CON4B
1
2
3
4
R22 75
R15
DNI
C4 0.1µF
U7
NB3N5573
S0
1
S1
2
NC0
3
X1
4
X2
5
OE
6
GND0
7
NC1
8iREF 9
CLK1# 10
CLK1 11
Vdd0 12
GND1 13
CLK0# 14
CLK0 15
Vdd1 16
C910µF
R17
DNI
R51
10K
R49
150
R25
150
R50 10K
R48
150
U8
Crystal
1
122

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Board A i2c
Expansion
Board A
AIF CLK & FS
Zero stub length to resistors,
Nets must be identical length
RP1FB / SMT SMA
--Leave room for wrench--
Zero stub length to resistors,
Nets must be identical length
J11 [ON = 0] DEFAULT
1 - A0 OFF
2 - A1 ON
3 - A2 ON
J10 [ON = 0] DEFAULT
1 - A0 ON
2 - A1 ON
3 - A2 ON
Board B i2c
Expansion
Board B
AIF CLK & FS
FACTORY J9 SETTINGS
01 - 12 Board B RADSYNC - ON
02 - 11 Board B PHYSYNC - ON
03 - 01 Board A RADSYNC - OFF
04 - 09 Board A PHYSYNC - OFF
05 - 08 TimerOut 0 Board B - ON
06 - 07 TimerOut 0 Board A - OFF
R73 &R32 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple CON5/CON6 net connections to R63/64
and R65/66 must be matched in length
-lengths from resistor junctions to AMC
headers must be identical
Placement of JP6/JP8 should be identical to JP7/JP9.
-Placement of R67 should be identical in distance to
R68 from Headers and switch
BRD3V3
BRD3V3
BRD3V3
BRD3V3
BRD3V3
BI A_AMC_EXP_SDA 3
IN A_AMC_EXP_SCL 3
OUT A_RP1FBP 3
OUT A_RP1FBN 3
BI
B_AMC_EXP_SDA4 IN
B_AMC_EXP_SCL4
OUT
B_RP1FBN4 OUT
B_RP1FBP4
OUT
B_TIMEROUT_04
INB_TIMERIN_04 OUT A_TIMERIN_0 3
IN A_TIMEROUT_0 3
OUT
B_RADSYNC4 OUT
B_PHYSYNC4 OUT A_PHYSYNC 3
OUT A_RADSYNC 3
Title
Size Document Number Rev
Date: Sheet of
<Doc> A
LC_2-EVM_BoC-0002 - Control Interface 2
B
610Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> A
LC_2-EVM_BoC-0002 - Control Interface 2
B
610Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> A
LC_2-EVM_BoC-0002 - Control Interface 2
B
610Friday, September 09, 2011
JP4
HDR_1x2
1
2
R66 10
U10
EEPROM
A0
1
A1
2
A2
3
Vss
4SDA 5
SCL 6
WP 7
Vcc 8
R63 10
R62 10K
R67 0
ON
J3
219-3MST
1
2
34
5
6
ON
J5
SDA06H1SBD
1 2 3 4 5 6 7
8 9 10 12 11
CON6
SMA_SMT
G1 2 G2 3
G3
4
G4
5
1
1
R68 0
JP8
HDR_1x1
1
JP7
HDR_1x1
1
R65 10
ON
J4
219-3MST
1
2
3 4
5
6
JP6
HDR_1x1
1
R61 10K
CON5
SMA_SMT
G1 2 G2 3
G3
4
G4
51 1
R58 10K
JP5
HDR_1x2
1
2
R64 10
R59 10K
R56 1K R55 1K
JP9
HDR_1x1
1
R60 10K
R57 10K
U9
EEPROM
A0 1
A1 2
A2 3
Vss 4 SDA
5SCL
6WP
7Vcc
8

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Board A & B
Daisy Chain
JTAG
Interface
TCKRTn total length to match TCK
routing on EVM's (No stubs allowed,
resistor connection should be as
close to header pin as possible.
EMULATION INTERFACE
TVD Target Power
Supply for IO's
POWER SUPPLY
NOTE: Interface is 3.3V and
requires 3.3V level translation
prior to interface with DSP. This
is done to comply with the current
AMC specification
0.100" Header
1 shunt needed
REG1117-3.3 (0.8A)
J6 Default 1:2
0.100" Header
1 shunt needed
J5 Default is Not Installed
0 = Power Down (Hi-Z)
1 = Normal (Active Output)
TDI from Emulator to DSP
TDO from DSP to Emulator
U12 Output is LVPECL Resistors R71:R75 & R77:R83
have been configured for CML output.
-Resistors will need to be changed to accommodate
a different swing.
-All resistors to go close to U12
U13, C18:C19 MUST be
placed close to U3
R85:R86 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple
NO STUBS
R84 must be across pins of U12
BJ_MH3
-Mounting hole to support
Pamona 2142-0 (Black
Banana Jack, Through hole)
BJ_MH1 & BJ_MH2
-Mounting hole to
support Pamona
2142-2 (Red Banana
Jack, Through hole)
NOTE: Mounting holes are plated through,
after plating, holes must support 6/32
mounting hardware and standoffs
GND GND
BRD3V3
BRD3V3
BRD3V3
A_VCC12
B_VCC12
BRD3V3
BRD3V3
BRD3V3
OUT A_REFCLK_P 3
OUT A_REFCLK_N 3
OUT B_REFCLK_P 4
OUT B_REFCLK_N 4
OUT A_TCK 3
OUT B_TCK 4
OUT TRST# 3,4
OUT TMS 3,4
IN TDO 4
OUT TDI 3
Title
Size Document Number Rev
Date: Sheet of
<Doc> D
LC_2-EVM_BoC-0002 - Control Interface 3 - JTAG
B
710Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> D
LC_2-EVM_BoC-0002 - Control Interface 3 - JTAG
B
710Friday, September 09, 2011
Title
Size Document Number Rev
Date: Sheet of
<Doc> D
LC_2-EVM_BoC-0002 - Control Interface 3 - JTAG
B
710Friday, September 09, 2011
R82
150
BJ_MH1
Banana-2142-
1
1
F1
Fuse 0154001.0
1
122
MH3
Mounting_Hole
11
R79 75
R83
150 R74
DNI
BJ_MH2
Banana-2142-
11
C18 0.1µF
C141µF
F2
Fuse 0154001.0
1
122
R71
DNI
C19 0.01µF
R70
150
C1710µF
R85 0
BJ_MH3
Banana-2142-
11
C1610µF
J6
CON3BR
12
3
JP10
HDR_1x2
1
2
U11
REG1117
Gnd
1
Out2
2
In
3Out1 4
U12
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacref
8
OUTP0 9
OUTN0 10
OUTP1 11
OUTN1 12
NC3 13 NC4 14 NC5 15
Gnd1 16
GP 17
MH4
Mounting_Hole
11
J7
hurricane_header
ID0
B1
GND*
A1
TMS
B2
GND
A2
EMU17
B3
GND
A3
TDI
B4
GND
A4
EMU14
B5
GND
A5
EMU12
B6
GND
A6
TDO
B7
GND
A7
TVD
B8
Type 0
A8
EMU9
B9
GND
A9
EMU7
B10
GND
A10
EMU5
B11
GND
A11
TCLK
B12
GND
A12
EMU2
B13
GND
A13
EMU0
B14
GND
A14
ID1
B15
OUT
A15
NC D1
ID2 C1
GND D2
EMU18 C2
GND D3
TRST C3
GND D4
EMU16 C4
GND D5
EMU15 C5
GND D6
EMU13 C6
GND D7
EMU11 C7
Type 1 D8
TCLKRTN C8
GND D9
EMU10 C9
GND D10
EMU8 C10
GND D11
EMU6 C11
GND D12
EMU4 C12
GND D13
EMU3 C13
GND D14
EMU1 C14
GND D15
ID3 C15
U15
CDCLVC1102_0
CLKIN
1
1G
2
Y0
3
GND
4NC0 5
Vdd 6
NC1 7
Y1 8
R76
10K
R69 27
R72
DNI
C151µF C1310µF
MH5
Mounting_Hole
11
U13
Ferrite
1
122
R86 0
R75 75
R80
150
R84 100
U14
FXO-LC73
E/D
1
NC
2
GND
3+OUT 4
-OUT 5
Vdd 6
MH6
Mounting_Hole
11
C20 0.1µF
R89 10
R77 75
R90
100
MH1
Mounting_Hole
11
C12
0.01µF
R81
150
R87
10K
R73
DNI
MH2
Mounting_Hole
11
R78 75
R88
150

EVM Dual BoC
BoC - Quick Start Guide Revision 0.4 – preliminary
Page 2 of 31
a. PCIeREFCLK Crystal-to-HCSL Output Enable Header [25].......................................................................17
b. PCIeREFCLK Logic ......................................................................................................................................18
c. Alternate PCIeREFCLK Inputs [4]................................................................................................................18
XVII. RP1FB Source [7]..........................................................................................................................................18
XVIII. RADSYNC & PHYSYNC Triggering [6]........................................................................................................18
XIX. Warnings and Cautions..................................................................................................................................20
XX. Pin Assignment [Board A].............................................................................................................................20
XXI. Pin Assignment [Board B].............................................................................................................................22
XXII. Header Intra-Connections .............................................................................................................................24
Table of Figures
Figure 1 - BoC Top View...............................................................................................................................................3
Figure 2: Front View, Assembled BoC..........................................................................................................................4
Figure 3 - Block Diagram..............................................................................................................................................5
Figure 4 - BoC Logic Power Source Selection..............................................................................................................6
Figure 5: BoC Power Supply.........................................................................................................................................7
Figure 6 - I2C Programming Header............................................................................................................................9
Figure 7: REFCLK Logic............................................................................................................................................11
Figure 8: REFCLK Biasing Components ....................................................................................................................11
Figure 9: RP1CLK Logic............................................................................................................................................. 13
Figure 10: RP1CLK Biasing Components...................................................................................................................14
Figure 11: TCLK_B Interface......................................................................................................................................15
Figure 12: TCLK_B Logic...........................................................................................................................................16
Figure 13: TCLK_B Biasing Components...................................................................................................................16
Figure 14: TCLK_B Interface......................................................................................................................................17
Figure 15: RP1CLK Logic...........................................................................................................................................18
Figure 16: RADSYNC & PHYSYNC Control ..............................................................................................................19
Figure 17: Cross Triggering Switch............................................................................................................................19
Table of Tables
Table 1: Factory Configuration.....................................................................................................................................6
Table 2: JP5 & JP4 (Board A & B) I2C Switch Configuration...................................................................................10
Table 3: JP10 REFCLK Enable Header......................................................................................................................10
Table 4: JP1 RP1CLK Enable Header........................................................................................................................13
Table 5: JP2 TCLK_B Enable Header ........................................................................................................................15
Table 6: JP3 PCIEREFCLK Enable Header...............................................................................................................17
Table 7: RADSYNC / PHYSYNC Trigger Configuration.............................................................................................20
Table 8: AMC B+ Header Pin Assignment – Board A ................................................................................................20
Table 9: AMC B+ Header Pin Assignment – Board B ................................................................................................22
Table 10: SerDes Board2Board Connections..............................................................................................................24

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 3 of 31
I. OVERVIEW
I. Introduction
The CI2EVM_BoC dual evm interface card is a high performance inter-communication card
designed to provide DSP to DSP communication during software testing and analysis.
II. Hardware Description
The following illustrates the major components and areas of the CI2EVM_BoC breakout card.
Figure 1 - BoC Top View
1) Emulation Interface – J7
2) Board B TCKA/B Header – J1
3) Board B AMC B+ EVM Interface Connector
4) Auxilluary PCIe Clock Input SMA Connectors - CON3/CON4
5) Board A EEPROM Address Configuration Switch - J4
6) Timer Sync Configuration Switch - J5
7) Auxilluary RP1FB Clock Input SMA Connectors - CON5/CON6
8) RP1CLK Source Input Clock Oscillator Enable Control – JP1
9) Board B I2C EEPROM Programming Header – JP4
10) Board B Timer0 Input Interface Header – JP6
11) Board A I2C EEPROM Programming Header – JP5
12) Board A Timer0 Output Interface Header – JP9
13) Board A TCKA/B Header – J2
1
2
3
4
5
6
7
8
9
22
11
12
13
14
15
16
17
18
19
20
21
23
10
24
25

EVM Dual BoC
BoC - Quick Start Guide Revision 0.4 – preliminary
Page 4 of 31
14) A_TCLKB & B_TCKB Source Input Clock Oscillator Enable Control – JP2
15) Auxilluary RP1CLK Clock Input SMA Connectors – CON1/CON2
16) Common Ground Banana Jack – BJ-MH3
17) Board B Power Banana Jack – BJ-MH2
18) Board A Power Banana Jack – BJ-MH1
19) Board A & B REFCLK Source Input Clock Oscillator Enable Control – JP10
20) Primary BoC Power Selection Switch – J6
21) Board A AMC B+ EVM Interface Connector
22) Board B Timer0 Output Interface Header – JP8
23) Board B EEPROM Address Configuration Switch – J3
24) Board A Timer0 Input Interface Header – JP7
25) Board A & B PCIECLK Source Input Clock Oscillator Enable Control - JP3
The following illustration is of the assembled BoC card for reference purposes:
Figure 2: Front View, Assembled BoC

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 5 of 31
The following is a high level block diagram denoting the connectivity and functionality of the dual EVM
BoC card.
SGMII TX Lane 1:0
SGMII RX Lane 1:0
PCIe TX Lane 3:0
PCIe RX Lane 3:0
TCLK A P/N
TCLK B P/N
PCIe REFCLK P/N
I2C SDA/SCL
AIF TX Lane 5:0
AIF RX Lane 5:0
TDI
TDO
TRST#
TMS
TCLK
SRIO TX Lane 4:1
SRIO RX Lane 4:1
TIMERIN_0
TIMEROUT_0
PHYSYNC
RADSYNC
REFCLKP/N
RP1FBP/N
RPICLK P/N
SGMII RX Lane 1:0
SGMII TX Lane 1:0
PCIe RX Lane 3:0
PCIe TX Lane 3:0
TCLK A P/N
TCLK B P/N
PCIe REFCLK P/N
I2C SDA/SCL
AIF RX Lane 5:0
AIF TX Lane 5:0
TDO
TDI
TRST#
TMS
TCLK
SRIO RX Lane 4:1
SRIO TX Lane 4:1
TIMERIN_0
TIMEROUT_0
PHYSYNC
RADSYNC
REFCLKP/N
RP1FBP/N
RPICLK P/N
AMC HEADER
BOARD B
+ RP1CLK -
+ RP1FB - + PCICLK -
12Vin à 3.3V Out
12V DC
TDO TDI TRST# TMS TCLK TVD
CDCLVP
OSC
CDCLVP
OSC
NB3N55
73
eeprom
eeprom
OSC
CDCLVP
OSC
12V DC
Figure 3 - Block Diagram

EVM Dual BoC
BoC - Quick Start Guide Revision 0.4 – preliminary
Page 6 of 31
II. Hardware Configuration
I. Initial Installation Procedure
The following instructions define the basic minimum installation requirements for your
BoC (Break out Card).
II. Default Jumper and Pin Settings
The following table defines the factory default configuration settings your BoC has been
shipped with.
Table 1: Factory Configuration
Reference
Item
Description
Factory Setting
J1
2
1X4 Header
N/A
J2
13
1X4 Header
N/A
J3
23
Switch
0x111
J4
5
Switch
0x011
J5
6
Switch
0x111110
J6
20
1X3 Header
Shunt Installed [1-2]
JP1
8
1X2 Header
Shunt Installed
JP2
14
1X2 Header
Shunt Installed
JP3
25
1X2 Header
Shunt Installed
JP4
9
1X2 Header
N/A
JP5
11
1X2 Header
N/A
JP6
10
1X1 Header
N/A
JP7
24
1X1 Header
N/A
JP8
22
1X1 Header
N/A
JP9
12
1X1 Header
N/A
JP10
19
1X2 Header
Shunt Installed
III. BoC Logic Power Source Selection [20]
The BoC on board logic is capable of sourcing power from either of the EVM’s (provided
the EVM’s are independently powered. Header J6 allows the user to select the 12V input
power to the BoC on board logic. The following figure illustrates the possible
configurations.
1
2
3
[1-2] Board A Supplies Power
[2-3] Board B Supplies Power
J6
Figure 4 - BoC Logic Power Source Selection

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 7 of 31
The following figure illustrates the basic power supply logic implemented on your BoC.
Figure 5: BoC Power Supply
IV. EVM Power Source [16, 17, 18]
Traditionally the EVM’s installed into the Boc will have there own power supplies. There
may be on occasion where a user needs to power both boards from the same power
source. The BoC contains three mounting holes (for banana jacks) that when installed
can be used to power the EVM’s installed.
EVM’s vary in total board power requirements. The power rating based on the current
designed layout of your BoC card will accommodate up to 8 amperes per board.
The recommended banana jacks to be installed are manufactured by Pomona®, part
numbers:
•1581-2 (Red, 2 required) [17 & 18]
•1581-0 (Black, 1 required) [16]
The mounting pads on the BoC are electrically conductive. Due to the height limitations
and the need to clear any supporting surface, the bottom insulated ring must be placed on
the top side of the PCB and the star washer and nut assembled from the bottom.
POWER SUPPLY
F1
Fuse 0154001.0
1
122
F2
Fuse 0154001.0 1
122
A_VCC12
B_VCC12
J6
CON3BR
12
3
0.100" Header
1 shunt needed
REG1117-3.3 (0.8A)
BRD3V3
J6 Default 1:2
C141µF
C1610µF
C151µF
BJ_MH1
Banana-2142-
1
1
BJ_MH2
Banana-2142-
11
BJ_MH3
Banana-2142-
11
C1310µF
U11
REG1117
Gnd
1
Out2
2
In
3Out1 4
BRD3V3
CAUTION: If you elect to power your EVM’s through the BoC card, you
MUST not use power supplies connected to your EVM’s input power.
WARNING: If you elect to power your EVM’s in this method, your EVM
power requirements must not exceed the maximum power allowed by the
design.

EVM Dual BoC
BoC - Quick Start Guide Revision 0.4 – preliminary
Page 8 of 31
V. Emulation Interface [1]
Your BoC contains a traditional Texas Instruments 60-pin emulation header (item 1). It
should be noted that emulation voltages across the AMCC backplane are intended for
3.3Vdc. Your BoC has been designed so that the emulation interface is also 3.3V, before
using this interface it will be necessary to confirm that your EVM’s can accommodate a
3.3V logic level without damage occurring.
The emulation interface of you BoC is daisy-chained. This means that the test data in and
test data out pins are configured such that both boards are in the scan chan at all times. If
you require separate control, use separate emulators directly connected to each
respective EVM.
VI. SGMII Interface
Your BoC in designed to support two (2) lanes of SGMII. The SGMII interface is
connected between each board (A & B) in a manner that provides intercommunication.
Board A transmit (TX) lanes 1:0 are routed to the receive (RX) lanes 1:0 of Board B, and
Board A receive (RX) lanes 1:0 are routed to the transmit (TX) lanes 1:0 of Board B.
There are no AC coupling capacitors on your BoC, it is assume that your EVM hardware
has been properly designed and contains the appropriate AC coupling capacitors on the
respective AC nets.
VII. PCIE Interface
Your BoC in designed to support four (4) lanes of PCIe. The PCIe interface is connected
between each board (A & B) in a manner that provides intercommunication. Board A
transmit (TX) lanes 7:4 are routed to the receive (RX) lanes 7:4 of Board B, and Board A
receive (RX) lanes 7:4 are routed to the transmit (TX) lanes 7:4 of Board B. There are no
AC coupling capacitors on your BoC, it is assume that your EVM hardware has been
properly designed and contains the appropriate AC coupling capacitors on the respective
AC nets.
In some cases a common or alternate PCIe clock may be required, where needed the
BoC has the ability to provide a common PCIe REFCLK, refer to section XVI for details
and configuration options.
WARNING: The Emulation Interface is intended to operate at 3.3V, Confirm
that your EVM level shifts this into to correct DSP range before using this
interface
CAUTION: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.
CAUTION: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 9 of 31
VIII. SRIO (Serial RapidIO) Interface
Your BoC in designed to support four (4) lanes of SRIO. The SRIO interface is connected
between each board (A & B) in a manner that provides intercommunication. Board A
transmit (TX) lanes 11:8 are routed to the receive (RX) lanes 11:8 of Board B, and Board
A receive (RX) lanes 11:8 are routed to the transmit (TX) lanes 11:8 of Board B. There
are no AC coupling capacitors on your BoC, it is assume that your EVM hardware has
been properly designed and contains the appropriate AC coupling capacitors on the
respective AC nets.
IX. AIF (Antenna Interface) Interface
Your BoC in designed to support six (6) lanes of AIF. The AIF interface is connected
between each board (A & B) in a manner that provides intercommunication. Board A
transmit (TX) lanes 18:17 & 15:12 are routed to the receive (RX) lanes 18:17 & 15:12 of
Board B, and Board A receive (RX) lanes 18:17 & 15:12 are routed to the transmit (TX)
lanes 18:17 & 15:12 of Board B. There are no AC coupling capacitors on your BoC, it is
assume that your EVM hardware has been properly designed and contains the
appropriate AC coupling capacitors on the respective AC nets.
X. I2C interface [5, 9, 11, 23]
Your BoC card is designed with EEPROMs sitting on the I2C bus for each EVM. Each
EEPROM is isolated from the other and resides on the AMCC backplane bus to the
respective EVM. From the factory, this interface to each respective EVM is electrically
ready for use but not directly connected to the EVM’s. Prior to use, the series termination
resistors (0ohm) are required to be installed. These resistors are designed in as SMT
components, 0402 in size. The following figure illustrates the pin out for both EEPROM
interface headers. These headers (JP4 & JP5) can be used to program the individual on
board EEPROMs. Your EEPROMS are blank from Texas Instruments. JP5 is the
interface and programming header for Board A, and JP4 is the interface and
programming header for Board B.
1
2
[Pin 1] SCL
[Pin 2] SDA
Figure 6 - I2C Programming Header
Each EEPROM contains a dedicated switch used to define the address. This feature was
added to allow the end user the ability to change the EEPROM address in the event there
was address contention do to something else sitting on the same bus. An on indication is
denoted as “0”. JP4 is default configured as 0x011, JP5 is default configured as 0x000.
The following table is provided to illustrate the switch to eeprom address correlation.
CAUTION: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.
CAUTION: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.

EVM Dual BoC
BoC - Quick Start Guide Revision 0.4 – preliminary
Page 10 of 31
Table 2: JP5 & JP4 (Board A & B) I2C Switch Configuration
JP4
JP5
EEPROM Address
ON
OFF
ON
OFF
Switch
A0
X
X
1-6
A1
X
X
2-5
A2
X
X
3-4
XI. Common REFCLK Source
Your BoC has the capability of supplying a common REFCLK both EVM’s. This common
REFCLK is generated on the BoC and sourced from a dedicated differential oscillator
through a high performance 1:2 low clock jitter buffer (U12). On your BoC is JP10, this
header and shunt are used to enable or disable the differential oscillator on the BoC. By
default the shunt is applied on this header, placing the oscillator input to the clock mux in
a Hi-Z state.
Not all EVM’s directly support this feature, future EVM’s will incorporate this feature and
have it connected to a EVM clock source (typically att the secondary clock source input)
through the AMC connectors and respective nets. The clock routing is skew matched
between AMC headers to within 5ps.
a. REFCLK Oscillator Enable Header [19]
The following table defines the possible configurations for JP10. JP10 is used to enable
or disable the 30.72MHz differential clock source (U14) input to the CDCLVP1102 which
is intended to provide a common clock source to both EVM’s for the REFCLK. By default
the shunt is installed and the REFCLK source is disabled.
Table 3: JP10 REFCLK Enable Header
JP10
ON
Disabled
OFF
Enabled
OFF
ON
1
X
2
X
b. REFCLK Signal Levels
The output of the low jitter 1:2 clock buffer is LVPECL (low voltage PECL). As such this
logic level may not be adequate for your DSP. Consult your DSP data manual and the
data manual for the CDCLVP1102 before using this hardware. Prior to proceeding it will
also be necessary to confirm that the EVM clock source input (that the REFCLK is
connecting to) is AC coupled and/or biased. Your BoC REFCLKp/n outputs are not AC
WARNING: The I2C Interface is intended to operate at 3.3V, Confirm that
your EVM level shifts this into to correct DSP range before using this interface
or connecting your EVM’s.
CAUTION: Confirm that your EVM supports this interface and that the
number of interfaces as well as the pinout locations is supported correctly.

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 11 of 31
coupled, however they are biased. The current biasing scheme implemented is designed
to provide the appropriate swing for most TI DSP’s available today.
The following two figures illustrate the configuration for the REFCLK generation and
biasing components. If a change in the output swing is needed, remove and replace the
appropriate components carefully.
Figure 7: REFCLK Logic
Figure 8: REFCLK Biasing Components
C18 0.1µF
C19 0.01µF
U13, C18:C19 MUST be
placed close to U3
R85:R86 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple
R85 0
R86 0
R84 must be across pins of U12
R80
150 R81
150 R82
150 R83
150
OUT A_REFCLK_P 3
OUT B_REFCLK_P 4
OUT A_REFCLK_N 3
OUT B_REFCLK_N 4
NO STUBS
BRD3V3
JP10
HDR_1x2
1
2
R76
10K
0.100" Header
1 shunt needed
J5 Default is Not Installed
0 = Power Down (Hi-Z)
1 = Normal (Active Output)
R75 75
R69 27
R77 75
R78 75
BRD3V3
C12
0.01µF
R79 75
R70
150
R71
DNI R72
DNI R73
DNI R74
DNI
U14
FXO-LC73
E/D
1
NC
2
GND
3+OUT 4
-OUT 5
Vdd 6
U12
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5
INP
6
INN
7
Vacref
8
OUTP0 9
OUTN0 10
OUTP1 11
OUTN1 12
NC3 13
NC4 14
NC5 15
Gnd1 16
GP 17
R84 100
U12 Output is LVPECL Resistors R71:R75 & R77:R83
have been configured for CML output.
-Resistors will need to be changed to accommodate a different swing.
-All resistors to go close to U12
U13
Ferrite
1
122
C20 0.1µF
C1710µF
R80
150 R81
150 R82
150 R83
150
OUT A_REFCLK_P 3
OUT B_REFCLK_P 4
OUT A_REFCLK_N 3
OUT B_REFCLK_N 4
NO STUBS
R75 75
R77 75
R78 75
BRD3V3
R79 75
R71
DNI R72
DNI R73
DNI R74
DNI
U12
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5INP 6INN
7Vacref
8
OUTP0
9OUTN0
10 OUTP1
11 OUTN1
12
NC3
13 NC4
14 NC5
15 Gnd1
16
GP
17
R84 100 C20 0.1µF

EVM Dual BoC
BoC - Quick Start Guide Revision 0.4 – preliminary
Page 12 of 31
XII. Timer0 Output Headers [12, 22]
The BoC incorporates a separate single header connected (through the AMC B+
connector) to each EVM’s DSP’s Timer0 output pin [DSP Timer0_output
 BoC
Timer0_output]. Header JP8 [22] is connected to Board B and header JP9 [12] is
connected to Board A. This timer pin can be used to initiate a trigger event which is
configurable using J5. Refer to section XVIII for additional configuration details.
Your BoC is also provided with a custom 12”-14” (30.48cm – 35.46cm) jumper wire that
can be used to connect between older EVM’s auxillary header containing the TimerOut0
pin to the either JP8 or JP9. This jumper is specifically designed with a 0.018” (0.457mm)
male pin (on one side) that if used can be inserted into the appropriate location on the
EVM auxillary header of you EVM, the opposite end contains a female header that is
designed to attach to either JP8 or JP9. Refer to section XVIII for detailed information on
configurations options.
XIII. Timer0 Input Header [10, 24]
The BoC incorporates a separate single header connected (through the AMC B+
connector) to each EVM’s DSP’s Timer0 input pin [DSP Timer0_input
 BoC Timer0_input].
Header JP6 [10] is connected to Board B and header JP7 [24] is connected to Board A.
This timer input pin to each respective DSP is provided for convience in the event future
connection is required.
XIV. Common RP1CLK Source
Your BoC has the capability of supplying a common RP1CLK both EVM’s. This common
RP1CLK is generated on the BoC and sourced from a dedicated differential oscillator
through a high performance 1:2 low clock jitter buffer (U1). On your BoC is JP1, this
header and shunt are used to enable or disable the differential oscillator on the BoC. By
default the shunt is applied on this header, placing the oscillator input to the clock mux in
a Hi-Z state.
Not all EVM’s directly support this feature, future EVM’s will incorporate this feature to
allow for design debug, expandability and test. The clock routing is skew matched
between AMC headers to within 5ps.
a. RP1CLK Oscillator Enable Header [8]
The following table defines the possible configurations for JP1. JP1 is used to enable or
disable the 30.72MHz differential clock source (U2) input to the CDCLVP1102 which is
intended to provide a common clock source to both EVM’s for the RP1CLK. By default the
shunt is installed and the RP1CLK source is disabled.
CAUTION: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.
CAUTION: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 13 of 31
Table 4: JP1 RP1CLK Enable Header
JP1
ON
Disabled
OFF
Enabled
OFF
ON
1
X
2
X
b. RP1CLK Signal Levels
The output of the low jitter 1:2 clock buffer is LVPECL (low voltage PECL). As such this
logic level may not be adequate for your DSP. Consult your DSP data manual and the
data manual for the CDCLVP1102 before using this hardware. Prior to proceeding it will
also be necessary to confirm that the EVM clock source input (that the REFCLK is
connecting to) is AC coupled and/or biased. Your BoC RP1CLKp/n outputs are not AC
coupled, however they are biased. The current biasing scheme implemented is designed
to provide the appropriate swing for most TI DSP’s available today.
The following two figures illustrate the configuration for the REFCLK generation and
biasing components. If a change in the output swing is needed, remove and replace the
appropriate components carefully.
Figure 9: RP1CLK Logic
R13 10K U1
CDCLVP1102
Gnd0
1
NC0
2
NC1
3
NC2
4
Vcc
5INP 6INN 7Vacref 8
OUTP0
9OUTN0
10 OUTP1
11 OUTN1
12
NC3
13 NC4
14 NC5 15 Gnd1 16
GP
17
JP1Default Settings
-Installshunt between 1-2
-Oscillator output is Hi-Z
Zero stub between CON1/CON2
SMA and U2/U1 OScillator input,
Nets must be identical length
CON1
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
CON2
SMA_SMT
G1
2G2 3
G3
4G4 5
1
1
U1 Output is LVPECL
Resistors R20:R23
have been configured
for CML output (mod for LVDS swing) RP1CLK SMT SMA
--Leave room for wrench--
-must be skew matched between SMA's
and U10 input
-NO STUBS
OUT A_DSP_RP1CLKP 3
OUT A_DSP_RP1CLKN 3
C2 0.1µF
R20 75
R21 75
R22 75
R23 75
C1
0.01µF
OUT B_DSP_RP1CLKP 3
OUT B_DSP_RP1CLKN 3
BRD3V3
R14
27
U3 Ferrite
1
122
C4 0.1µF
C5 0.01µF
R19
150
BRD3V3
C3 10µF U2
FXO-LC73
E/D
1
NC
2
GND
3+OUT 4
-OUT 5
Vdd 6
R18
DNI
R15
DNI R16 DNI R17 DNI
R28
150
R27
150
R26
150
R25
150
NOTE: PLACE OSCILLATOR WITH NO STUBS
-U2 is a 30.72MHz Oscillator p/n FXO-LC735R-30.72
-By default leave Disabled
-Oscillatoronly installed on limited board
-RPICLKP/Nnets to be matched length from"T"
-R15:18, 20:23, & 25:28 must be placed close to output
R24 & R29 are 0 ohm 0402 resistors,
May need to be changed to 0.01uF
Capacitors to AC couple
R24 0
R30 100
R29 0
BRD3V3
JP1
HDR_1x2
1
2

EVM Dual BoC
BoC - Quick Start Guide Revision 0.4 – preliminary
Page 14 of 31
Figure 10: RP1CLK Biasing Components
c. Alternate RP1CLK Inputs [15]
Your BoC has been designed with auxillary SMA input connectors (CON1 & CON2) in the
event a different RP1CLK frequency is desired. Should you elect to utilize this input it will
be necessary to confirm that it meets the input requirements of the CDCLVP1102 and
that the corresponding outputs are properly biased, and that the oscillator is disabled
(install JP1 shunt). CON1 is the negative polarity differential input; CON2 is the positive
polarity differential input to the CDCLVP1102.
XV. Common TCLK_B Source
Your BoC has the capability of supplying a common TCLK_B to both EVM’s. This
common TCLK_B is generated on the BoC and sourced from a dedicated differential
oscillator through a high performance 1:2 low clock jitter buffer (U6). On your BoC is JP2;
this header and shunt are used to enable or disable the differential oscillator on the BoC.
By default the shunt is applied on this header, placing the oscillator input to the clock mux
in a Hi-Z state.
Not all EVM’s directly support this feature, future EVM’s will incorporate this feature to
allow for advanced clocking and test. The clock routing is skew matched between AMC
headers to within 5ps.
a. TCLK_B Oscillator Enable Header [14]
The AMC standard allows for external clock sources across the backplane bus, TCLK_x
are several of the clocks allowed. The following table defines the possible configurations
for JP2. JP2 is used to enable or disable the 30.72MHz differential clock source (U6)
input to the CDCLVP1102 which is intended to provide a common clock source of
U1
CDCLVP1102
0
VccINP
6INN 7Vacref 8
OUTP0
9OUTN0
10 OUTP1
11 OUTN1
12
NC3
13 NC4
14 NC5
15 Gnd1
P
Zero stub between CON1/CON2
SMA and U2/U1 OScillator input,
Nets must be identical length
CON1
SMA_SMT
G1
2
G2
3
G3
4
G4
5
1
1
CON2
SMA_SMT
G1
2G2
3
G3
4G4 5
1
1
CL
red
od for LVDS swing)
RP1CLK SMT SMA
--Leave room for wrench--
-must be skew matched between SMA's
and U10 input
-NO STUBS
OUT A_DSP_RP1CLKP 3
OUT A_DSP_RP1CLKN 3
C2 0.1µF
R20 75
R21 75
R22 75
R23 75 OUT B_DSP_RP1CLKP 3
OUT B_DSP_RP1CLKN 3
R18
DNI
R15
DNI R16 DNI R17 DNI
R28
150
R27
150
R26
150
R25
150
R30 100
BRD3V3
CAUTION: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.

EVM Dual BoC
Revision 0.4 – preliminary BoC - Quick Start Guide
Page 15 of 31
30.72MHz to both EVM’s for TCLK_B. By default the shunt is installed and the REFCLK
source is disabled.
Table 5: JP2 TCLK_B Enable Header
JP2
ON
Disabled
OFF
Enabled
OFF
ON
1
X
2
X
b. TCLK_B Signal Outputs [2, 13]
There are two headers provided on your BoC; J1 & J2. Board A makes use of the 1 x 4
header whereas Board A interfaces with J2. In some current production TI EVM’s these
pins are connected to the AMC headers, others not – confirm proper connection before
powering up or using this feature. Due to layout constrainst J1 and J2 pinouts are not
identical – please refer to the following figure and the silk screen on your BoC for proper
pin locations.
J2
1
TCLKA_P
TCLKA_N
TCLKB_P
TCLKB_N
4
2
3
J1
1
TCLKA_P
TCLKA_N
TCLKB_N
TCLKB_P
4
2
3
Figure 11: TCLK_B Interface
The oscillator source (U5) is routed into the low jitter 1:2 clock buffer (U6), the output is a
biased LVPECL (low voltage PECL). Some EVM input logic levels may have to be
adjusted to properly interface with your DSP, consult your DSP data manual and the data
manual for the CDCLVP1102 before using this hardware or making any modifications.
Prior to proceeding it will also be necessary to confirm that the TCLK_B pins are not
assigned other functions and that no contention will occur. Your BoC REFCLKp/n outputs
are not AC coupled, however they are biased. The current biasing scheme implemented
is designed to provide the appropriate swing for most TI DSP’s available today.
CAUTION: Different versions of EVM’s have different pinout configurations,
confirm that your EVM supports this interface and feature.