Texas Instruments TIDA-050034 Guide

i.MX7D Processor
VDD_ARM
i.MX7 Based System
VDDA_1P8_IN, VDD_XTAL_1P8,
VDD_LPSR_IN,
VDD_TEMPSENSOR_1P8,
VDD_ADCx_1P8, FUSE_FSOURCE,
NVCC_SPI, NVCC_SD1-3
NVCC_DRAM, NVCC_DRAM_CKE
DRAM_VREF
DRAM Memory Module
VDD, VDDQ, VDDCA,
VDD1, VDD2
VREF
VSYS
TPS6521815
PMIC
DCDC1
DCDC2 1.8 A
1.8 A
LDO1
IN_BIAS
400 mA
LS2
PFI
SCL
SDA
PWR_EN
PGOOD
IN_DCDCx
IN_LDO
4
DCDC4
1.35 V
1.6 A
(5 V)
nINT
Regulators
IN_LS2
AC_DET Digital
1 V / 1.1V
1.5 V
3.3 V
VDD_SOC
PFO
POR_B
PWR_ON_REQ
GPIO
GPIO
I2Cx_SCL
I2Cx_SDA
NVCC_I2C, NVCC_xxxx (3.3V IOs),
VDD_USB_OTGx_3P3_IN
0
2
1
1
2
VDD_SNVS_IN
DCDC3
1.8 V
1.8 A
LS3
IN_LS3
Load Switches
TPS51200
DDR Terminator
2
mPCIe
1
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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
Design Guide: TIDA-050034
Integrated Power Supply Reference Design for NXP i.MX
7D Processor
Description
TIDA-050034 is a fully functional development board
integrating a TI PMIC, TPS6521815, with NXP™ i.MX
7Dual application processor. The hardware design
consists of DDR3L SDRAM (2x512MB), 64MB Serial
NOR Flash, 8GB eMMC 5.0 iNAND, SD Card interface
v3.0, 50-pin LCD Connector for external TFT display
interface, 1000Base-T Ethernet, USB2.0 Type A and
micro-AB, MIPI CSI for external camera interface, and
mini-PCIe interface. This design is intended for any
project using the i.MX 7Solo or i.MX 7Dual processor
and requires evaluation of alternate power solutions.
Resources
TIDA-050034 Design Folder
TPS6521815 Product Folder
TPS51200 Product Folder
TPS62067 Product Folder
TPS3808 Product Folder
INA3221 Product Folder
TLV755P Product Folder
WL1831MOD Product Folder
DP83867CR Product Folder
OPT3001 Product Folder
Search Our E2E™ support forums
Features
• Full system-on-board for rapid development of NXP
i.MX 7D and i.MX 7S systems
• Low-power modes and DVFS supported
• Wi-Fi®+ Bluetooth®wireless connectivity
• Ethernet, CAN, USB wired connectivity
• LCD, HDMI®, MIPI DSI display options
• Selectable boot options (SD, eMMC, QSPI)
Applications
•Data concentrator
•Electricity meter
•HVAC gateway
•Thermostat
•Intrusion control panel
•Building security gateway
•ARM-based SoM/CoM
•Panel PLC (HMI)
•Barcode scanner
•Portable POS
i
i
i
Order from RadiumBoards.
An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other
important disclaimers and information.

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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
1 System Description
TIDA-050034 is first-and-foremost a reference design for powering the NXP i.MX 7Dual processor from
the TPS6521815 PMIC. To show that the PMIC can power the processor, it made the most sense to build
a full evaluation kit (EVK) board with a variety of peripheral devices to assist with development of various
end equipments. As a result, there are a variety of wired and wireless connections available, as well as
multiple BOOT options. The end result of adding all the peripherals is that some external DC-DCs and
LDO regulators have been added to provide more voltage rails and current delivery as needed. Finally, to
ensure the entire board is operational, we developed and tested software using the open-source
embedded Linux Yocto SDK to get started testing this design.
1.1 Key System Specifications
Table 1. Key System Specifications
PARAMETER SPECIFICATIONS DETAILS
Processor i.MX 7Dual, Dual-Core Applications Processor,
MCIMX7D7DVM10SC Section 2.2.1
PMIC TPS6521815 user-programmable PMIC with automatic
sequencing and DVFS Section 2.3.1
Auxiliary power TPS51200 DDR terminator, TPS62067 2-A buck, TLV755P
LDOs Section 2.3.7
Memory 2x4Gb DDR3L (1GB total), 512Mb QSPI NOR-Flash (64MB),
8GB eMMC 5.0, SD v3.0 interface Section 2.2.2
Audio CODEC SAI (Serial Audo Interface) to support the WM8960CGEFL/V-ND CODEC from Cirrus Logic for microphone, speaker, and
headphones. Section 2.2.3
Ethernet Gigabit ethernet interface - TI DP83867CS PHY and
J1011F21PNL RJ45 jack from Pulse Electronics Section 2.3.3
Wi-Fi + Bluetooth Support Wi-Fi + Bluetooth with TI WL1831MOD device Section 2.3.2
Debug method (USB-to-UART) FTDI FT2232D is required to implement USB to serial UART
conversion Section 2.2.4
USB ports USB Type-A (TE 1-1734775-1) and micro-AB interface (Hirose
ZX62D-AB- 5P8) Section 2.2.5
LCD display RGB TFT 50-pin connector for LCD support (Hirose FH40-50S-
0.5SV) Section 2.2.6
MIPI CSI 2-lane MIPI CSI through 30-pin connector (Panasonic
AXT530124) Section 2.2.7
mini-PCIe TE AXT530124 30-pin connector, Diodes PI6C557-03LE PCIe
clock generator, Molex 78723-1001 micro-SIM card socket Section 2.2.8
JTAG header JTAG connection to i.MX 7D processor with 50-mil pitch, 10-pin
header Section 2.2.10
USB2ANY header Debug method for PMIC separate from processor I2C bus.
Provided by USB2ANY (standard 100-mil pitch, 10-pin header) Section 2.2.11
CAN interface Microchip MCP2562-E/MF CAN Transceiver, TE 5747840-4 DB9
Male connector Section 2.2.9
Ambient Light Sensor TI OPT3001DNPR device with I2C communication Section 2.3.4
Current monitoring 2x TI INA3221 devices are used to monitor current through 6
rails in the system Section 2.3.5
Operation with Coin Cell Coin cell directly attaches to i.MX 7D SNVS input. Using TI
TPS3808G25 supervisor, system prevents turn on until coin cell
battery is inserted.
Section 2.3.6
Tactile inputs, visual feedback Push-buttons and status LEDs connected to GPIOs of the
processor to assist with debugging software Section 2.2.12

DDR3L 2x256MB
ESD Protection
PUSB3FR4
ESD Protection
PUSB3FR4 ESD Protection ESD Protection PUSB3FR4
ESD Protection
PUSB3FR4
Boot Mode
Select (8POS)
Reset
Switch
Status
LED
Ambient Light
Sensor
OPT3001DNPR
FUNC1 &
FUNC2
Ethernet PHY
DP83867CS
ESD Protection
RCLAMP0504N.TCT
USB Debug
FT2232D-REEL JTAG
ESD Protection
PUSB3FR4
ESD Protection
PUSB3FR4
ESD Protection
PESD5V0F1BL
ESD Protection
PESD5V0F1BL,315
Audio Codec
WM8960CGEFL/V-ND
mPCIe
eMMC 8Gb
MTFC8GAKAJCN-1M
NOR Flash 32 MB
MT25QL256ABA1EW9
DDR3L 2x256MB
MT41K128M16JT-125
USB
Debug Port
USB OTG SD Card Slot
LCD Expansion
Port Connector
PMIC
TPS6521815RSLR
Current
Sense To Processor GPIO/I2C
i.MX 7Dual
Applications
Processor
VIN: 5V DC
WiFi + Bluetooth
WL1831MODGBMOCT MIPI CSI
AXT530124
CAN-Transceiver
SN65HVD255DR
USB
TYPE-A
LVDS for Display
(40-pin Connector)
RGMII
GPIOs
I2C
GPIOs
RESET I/P
BOOT
MODE I/P
SDIO, UART
MIPI CSI CAN USB2.X
LVDS
I2S
PCIe x 1
MMC 5.0
QSPI
DDR3L
UART
USB 2.x
OTG
SDIO
LCD
INTERFACE
USB2.x
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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
2 System Overview
2.1 Block Diagram
Figure 1. TIDA-050034 Block Diagram

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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
2.2 Design Considerations
This design is intended to show the ability of the TI power devices to provide power to the i.MX 7Dual
processor and all of the peripheral ICs in a variety of designs. To verify this, we had to populate all of
these other ICs on the design, starting with the processor. All other devices necessary to build an
operational evaluation kit are included in this section. The power devices and other TI devices used in this
design are described in Section 2.3.
2.2.1 Processor – i.MX 7Dual Applications Processor
The i.MX 7Dual family of processors are used for high-performance processing with low-power
requirements also incorporating high degree of functional integration. These processors are targeted
towards the growing market of connected and portable devices. i.MX 7Dual processor consists of three
cores (2 × Arm®Cortex®-A7 core operating at 800MHz to 1.2GHz, depending on the part number and one
Cortex®-M4 core operating at 200MHz). It provides a 32-bit DDR3 - 1066 memory interface and also
supports DDR3L, LPDDR2 and LPDDR3 interface (DDR3L which is used in this design). This processor
has number of other interfaces like Ethernet, EPD Controller, MIPI CSI, DSI and LCD interface, WLAN,
Bluetooth, GPS, display, camera sensors along with improved security and tamper protection. A detailed
table listing the mapping for each pin on the iMX7D processor can be found in Appendix A.
DESCRIPTION MFG. PART NUMBER
i.MX 7 series 32-bit MPU, Dual ARM NXP MCIMX7D7DVM10SC
2.2.2 i.MX 7Dual Memory Interfaces
This project makes use of i.MX 7D processor’s four different external memory interfaces using 2x4Gb
DDR3L (1GB), 512Mb QSPI NOR-Flash (64MB), 8GB eMMC 5.0, and SD v3.0.
2.2.2.1 DDR3L
i.MX 7Dual has dedicated DDR memory controller which support LP-DDR2, DDR3, DDR3L and LPDDR3
all of which supports only 1066 MT/s data rate. This design is provided with two 4Gb x16 (1GB) DDR3L
memory. Micron’s, MT41K256M16TW-107:P is a 4Gb DDR3L SDRAM, currently used in this design. This
design uses two DDR3L memory, together providing 1GB memory required for this design. The memory
interface comprises of two channel of 16-bit data signals, along with shared command and address
signals. The DDR interface is shown in Figure 2.
DESCRIPTION MFG. PART NUMBER
IC, DDR3L, 4Gb, x16bit, 1866MHz, FBGA-96 Micron MT41K256M16TW-107 :P

i.MX 7Dual
DRAM_DATA[0-7]
DRAM_SDQS0_P/N
DRAM_DATA[8-15]
DRAM_SDQSQ_P/M
DRAM_DQM0/1
DRAM_RESET
DRAM_SDCLK0_P/N
DDR_ADDR[0:13]
CONTROL SIGNALS
DRAM_DATA[16-23]
DRAM_SDQS2_P/N
DRAM_DATA[24-31]
DRAM_SDQS3_P/N
DRAM_DQM2/3
NVCC_DRAM
NVCC_DRAM_CKE
DRAM_VREF
1V35
0V675
MT41K256M16TW-107 :P
MT41K256M16TW-107 :P
DQ [0:7]
LQDS, LQDS#
DQ [8:15]
UDQS, UDQS#
LDM/UDM
RESET#
CK, CK#
A[0:13]
BA[0:2}
CONTROL SIGNALS
DQ[0:7]
LQDS, LQDS#
DQ[8:15]
UDQS, UDQS#
LDM/UDM
A[0:13]
BA[0:2}
CK, CK#
RESET#
VDD
VDDQ
1V35
0V675
VREF
ZQ
VSS
240E, 1%
VDD
VDDQ
1V35
0V675
VREF
ZQ
VSS
240E, 1%
CONTROL SIGNALS
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Figure 2. DDR3L Interface
2.2.2.2 Quad SPI NOR Flash
The i.MX 7Dual processor supports both Parallel NOR Flash interface as well as Quad SPI NOR Flash
interface. This project will support only one Serial NOR Flash. Micron’s, MT25QL256ABA1EW9- 0SIT TR
is a Serial NOR Flash Memory with a density of 512Mb (64MB) at clock frequency 133MHz and data
through-put up to 90MB/s.
DESCRIPTION MFG. PART NUMBER
IC, NOR Flash, 64MB, SPI, 133MHz, 2.7- 3.6V, W-
PDFN-8 Micron MT25QL512ABB1EW9-0SIT

MTFC8GAKAJCN-4M IT
DAT[0-7]
CLK
CMD
VSS
VCC VCCQ
3V3 1V8
i.MX 7Dual
SD3_DATA[0-7]
SD3_CLK
SD3 CMD
SD3_STROBE
1V8
DS
SD3_RESET
1V8
RESET#
GND
33E
33E
NVCC_SD3
10 K x 2
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2.2.2.3 eMMC iNAND
For this design an 8GB eMMC 5.0 compliant Memory is included. The interface diagram of eMMC with
processor is shown in Figure 3. The part used here is an IC from Micron, the MTFC8GAKAJCN- 4M IT. It
supports HS400 which is High Speed Mode supporting 400MBps at 200MHz dual data-rate bus.
DESCRIPTION MFG. PART NUMBER
IC, eMMC, 8GB, VFBGA-153 Micron MTFC8GAKAJCN-4M IT
Figure 3. eMMC Interface
2.2.2.4 SD Card Connector
In this design, there is an SD card connector and interface provided. The power supply to the SD card is
selectable between 1.8 V and 3.3 V using a power multiplexer, and both input voltages to the multiplexer
are provided by the TPS6521815 PMIC. The initial voltage applied to the VDD pin of the SD card
connector must always be 3.3 V, which is achieved with additional circuitry. The power and wiring for the
SD Card connector are shown in Figure 4
DESCRIPTION MFG. PART NUMBER
Connector, SD card, Push-Pull Amphenol ICC 10067847-001RLF
Diode, ESD-Bidir, 5.5V, SOD-882D NXP PESD5V0F1BL
IC, Power Switch N-Channel 2:1, 50VCSP ROHM BD2204GUL-E2

3V3
TPS6521815
LS1
i.MX 7Dual
SD1_DATA[0-3]
SD1_CLK
SD1_CD#
SD1_WP
SD1_CMD
ESD
NVCC_SD1
SD Card Connector
DATA[0-3]
CLK
CD#
WP#
CMD
VDD_SD1
10 NŸ
22 Ÿ
22 Ÿ
22 Ÿ
10 NŸ
44
10 NŸ
NVCC_SD1
SD Card Voltage Mux
BD2204GUL
GPIO
IN1
IN2
OUT
1V8
3V3*
NVCC_SD1
GPIO1 EN
SEL
3V3* = 3V3 at start-up, then NVCC_SD1
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Figure 4. SD Card Power and Connector
2.2.3 Audio CODEC
To include an audio CODEC to this design, an IC from Cirrus Logic, the WM8960CGEFL/V-ND, is used to
provide connectivity to a microphone, speaker and a headphone. The digital interface to processor is
through SAI (Serial Audio Interface). For this project, there is an additional onboard microphone from PUI
Inc, the TOM-1545P-R.
DESCRIPTION MFG. PART NUMBER
1C, Audio codec, Stereo, Class D,QFN-32 CIRRUS LOGIC WM8960CGEFL/V-ND
MIC, Analog Electret Condenser 2V - 10V, -45dB PUI Audio, Inc. TOM-1545P-R
2.2.4 USB to UART Converter
There is a USB to Serial (UART) interface in the design. To implement this feature, the FT2232D chip
from FTDI is used which is a USB to dual port RS232 converter. The detailed diagram of interconnection
is in Figure 5.
DESCRIPTION MFG. PART NUMBER
IC, FT2232D, USB to UART Converter, Dual UART,
LQFP-48 FTDI Chip FT2232D-REEL

i.MX 7Dual
USB_OTG2_VBUS
USB_OTG2_DP
USB_OTG2_DN
USB_OTG1_VBUS
USB_OTG2_DP
USB_OTG2_DN
USB_OTG1_ID
USB_OTG2_VBUS
USB_OTG2_GP
USB_OTG2_DN
USB_OTG1_VBUS
USB_OTG2_DP
USB_OTG2_DN
USB_OTG1_ID
i.MX 7Dual
UART1_RXD
UART1_TXD
UART2_RXD
UART_TXD
NVCC_UART
3V3
FT2232D
FT_TX1
FT_RX1
FT_TX2
FT_RX2
XIN
VCC VCC10A AVCC
ESD
USB_5V0 USB_5V0 2V5
GND
SN74LVC2
G126
SN74LVC2
G126
470 E
100 nF
RESET#
USB_5V0
USB_DP
USB_DM
XOUT
10118193-0001LF
6 MHz
USB_5V0
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Figure 5. USB to Serial UART Interface With FT2232
2.2.5 USB Ports
This design incorporates two USB interfaces, one Type A interface and the other a micro-AB interface.
Both of the processor's dedicated USB interfaces OTG and connect directly to the receptacle, as shown in
Figure 6.
DESCRIPTION MFG. PART NUMBER
Conn, USB2.0 Type A, RA, TH TE 1-1734775-1
Conn, USB2.0 microAB, RA, SMD Hirose ZX62D-AB- 5P8(30)
Figure 6. USB Interface

i.MX 7Dual
LCD1_DATA[0:23]
LCD1_HSYNC
LCD1_VSYNC
LCD1_RESET
LCD1_ENABLE
NVCC_LCD
Touch Screen
Controller
VCC
VSS
1V8
X+/X-/Y+/Y-
SPI
LCD1_CLK
PWM_OUT1
I2C3
SPI3
10R
LCD1_DATA[0:23]
LCD1_HSYNC
LCD1_VSYNC
LCD1_RESET
LCD1_ENABLE
LCD1_CLK
PWM_OUT1
I2C3
SPI3
TOUCH[0:3]
3V3
VSS
VDD1 VDD2
3V3 5V0
FH40-50S-0-.5SV
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2.2.6 LCD Screen Connector
The LCD interface is a RGB TFT interface with 24 signals connected through a 50-pin connector. The
connection diagram is shown in Figure 7.
DESCRIPTION MFG. PART NUMBER
Conn, FPC, Vertical, 50 Position Hirose Electric Co Ltd FH40-50S-0.5SV
Figure 7. LCD Interface From i.MX 7D Processor to Connector
2.2.7 MIPI CSI Connector
MIPI CSI for camera is provided with this design. The i.MX 7D processor supports 2 lane MIPI interface,
which is connector to a 30-pin connector from Panasonic as shown in Figure 8.
DESCRIPTION MFG. PART NUMBER
Connector, Socket, 0.4mm, 30 Position Panasonic Electric Works AXT530124

i.MX 7Dual
MIPI_CSI_CLK_P/N
MIPI_CSI_D0P/N
MIPI_CSI_D1P/N
I2C4_SCL
I2C4_SDATA
MIPI_VIDDA_1V8
ESD
AXT530124
1V8 2V8 3V3
VCC
XCLK_OUT
24 MHz OSC
GND
1V8
1V8
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Figure 8. MIPI CSI Connector
2.2.8 Mini PCI Express®Connector
The signals for mini-PCI Express, or mPCIe, are terminated to a connector in this design as shown in
Figure 9. An onboard reference clock generator is used.
DESCRIPTION MFG. PART NUMBER
Conn, Socket, mPCIe, 52 Position TE 1775862-2
IC, PI6C557, PCIe Clock Generator, 200MHz, TSSOP-
16 Diodes PI6C557-03LE
Conn, Micro SIM Card Socket, 1X1, Shielded, RA Molex 78723-1001

MCP2562-E/MF
TXD
RXD
STBY
CANH
CANL
VSS
VIO VDD
3V3 5V0
ESD
1734351-1
i.MX 7Dual
NVCC_GPIO2 NVCC_EPDCT1
CAN2_TX
CAN2_RX
GPIO
3V3 3V3
i.MX 7Dual
PCIE_TX
PCIE_RX
PCIE_REFCLKOUT
I2C2_SCL
I2C2_SDATA
VDD_USB_OTG2
1775862-2
3V3_PERI 1V5
VDD1
3V3
USB_OTG2_DN/P
PCIE_REFCLK_P/N
PCIE
VDDA_1P8_IN
I2C4_SCL
I2C_SDA
Clock Generator
SDA
SCL
VSS
VDD2
SIM Connector
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Figure 9. mPCIe Interface
2.2.9 CAN Transceiver and Standard Connector
This design includes a CAN interface. The transceiver is a MCP2562 from Microchip, which is wired to a
standard 9-pin D-Sub connector, as shown in Figure 10.
DESCRIPTION MFG. PART NUMBER
IC, CAN Transceiver, SOIC-8 Microchip MCP2562-E/MF
Conn, DE-9, Male, 1x1, 6A, Board Lock, RA, TH TE 5747840-4
Figure 10. CAN Interface

PMIC
TPS6521815
GPIO
SPI:MISO
GPIO
SPI:CS
SPI:MOSI
SPI:SCLK
SCL
SDA
I2C1:SCL
I2C1:SDA
2
4
6
8
10 9
7
5
3
1
10-Pin USB2ANY Connector
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2.2.10 JTAG Header
The JTAG connections match the requirements of the i.MX 7Dual for direct access to the processor for
programming and debugging.
DESCRIPTION MFG. PART NUMBER
Connector, Berg strip, 2x5, 1.27mm, 1A, ST, SMD FCI 20021121-00010*4LF
2.2.11 USB2ANY Header
USB2ANY is TI MCU-based adapter intended to allow a computer to control an electronic evaluation
module (EVM) via a USB connection. In this design, the I2C interface of USB2ANY is used to externally
monitor, control, and or re-program the internal registers of PMIC. The wiring of the USB2ANY header is
shown in Figure 11.
DESCRIPTION MFG. PART NUMBER
Connector, Berg strip, 2x5, 2.54mm, 3A, RA, TH FCI 68021-210HLF
Figure 11. USB2ANY Header Connections to PMIC I2C Pins
2.2.12 Functional Switches and Status LEDs
There are two functional multi-purpose push buttons connected to GPIOs configured as inputs on the
processor that can be used for software developers to test applications developed using this board. Three
LED are connected to three GPIOs of the processor to indicate the status of processes that are running,
completed, or may have failed. Both the push-buttons and status LEDs can be used for debugging or to
provide tactile inputs and visual feedback to the user. These connections are shown in Figure 12.

i.MX 7Dual
GPIO5_IO10
GPIO5_IO11
GPIO1_IO00
GPIO1_IO01
GPIO1_IO02
Provide 470 Ÿ
series resistor
Provide 1 NŸVHULHV
resistor
NVCC_GPIO
NVCC_GPIO
NVCC_GPIO
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Figure 12. GPIO Connections to Push-buttons and LEDs
2.3 Highlighted Products
2.3.1 TPS6521815 - Power Management IC
The TPS6521815 device is a Power Management IC (PMIC) specifically designed to support Arm Cortex
processors like the i.MX 7Dual from NXP. The PMIC is a good fit for applications powered from a 5-V
supply or a Li-Ion battery. The IC consists of three adjustable step-down (buck) converters, one buck-
boost converter, one adjustable LDO regulator and three load switches with two selectable current limit.
The PMIC supports undervoltage lockout (UVLO), over-temperature warning and shutdown, separate
power-good output for all regulators, programmable power sequencing for all regulators, and an I2C
interface for register reading and writing to the device. The full power architecture of this design is shown
in Figure 17.
The I/O connections between the processor and the TPS6521815 PMIC are shown in Figure 13, as well
as analog and digital input pins on the PMIC.

TPS6521815
SCL
SDA
nINIT
PFO
PWR_EN
PGOOD
DC34_SEL
AC_DET
5 V
i.MX 7D
I2C1:SCL
I2C1:SDA
GPIO4_IO22
GPIO4_IO20
PWR_ON_REQ
POR_B
5 V
PFI
PB
5 V
100 NŸ
100 NŸ
100 NŸ23.2 NŸ
23.2 NŸ
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Figure 13. TPS6521815 PMIC I/O Wiring to i.MX 7D Processor
2.3.2 WL1831MOD - Wi-Fi®+ Bluetooth®Module
This design makes use of TI’s Wi-Fi + Bluetooth module, the WL1831MODGBMOCT device. The interface
with the processor is through UART for Bluetooth and SDIO for WLAN (Wi-Fi). The design provides two
coaxial connections for monopole antenna connection.
Description Mfg. Part Number
Module, Wi-Fi-Bluetooth,IEEE 802.11b, 802.11g,
802.11n, QFM-100 TI WL1831MODGBMOCT
2.3.3 DP83867CR - Ethernet PHY
The i.MX 7Dual processor supports dual Ethernet PHY interfaces, but for this design we are using only
one gigabit Ethernet. The 1000Base-T PHY used in this design is the DP83867CR device. The interface
to the processor is through RGMII, also connecting MDC/MDIO for management of the PHY. To connect
MDI to the Cat5e cable, we used an RJ45 with internal magnetics from Pulse Electronics. The Ethernet
interface connections are shown in Figure 14.
Description Mfg. Part Number
IC, Gigabit Ethernet PHY TI DP83867CRRGZ
Conn, RJ45 Jack with integrated magnetics, 1x1,
shielded, LED(G,Y) RA, TH PULSE ELECTRONICS J1011F21PNL

i.MX 7Dual
ENET1_TD[0-3]
ENET1_TXC
ENET1_TX_CTL
ENET1_RD[0-3]
ENET1_RXC
ENET_TX_CTL
ENET1_MDIO
GPIO
NVCC_ENET1
3V3
DP83867CRRGZ
TX_D[0-3]
GTX_CLK
TX_CTRL
RX_D[0-3]
RX_CLK
MDIO
MDC
INT#
RX_CTRL
ENET1_MDC
VDDIO VDDA1P8 VDDA2P5 VDD1P0
MEDIA
DEPENDANT
INTERFACE
ESD
Shown resistors are of value 49E9 except pull up
3V3 1V8 2V5 1V0
GND
2K2
2K2ENET1_MDIO
INT#
3V3
RJ45 with internal
magnetics
RESET
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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
Figure 14. Ethernet Interface With DP83867CR PHY
2.3.4 OPT3001 - Ambient Light Sensor
The ambient light sensor (ALS) provided in this design uses TI’s IC. The interface to the processor is
through shared I2C lines. The address (ADDR) pin of the sensor IC needs to be pulled up or down with a
resistor to determine the address setting according to Table 2.
Description Mfg. Part Number
IC, Ambient Light Sensor, I2C, USON-6 TI OPT3001DNPR
Table 2. OPT3001 I2C Slave Address Options
7-bit Binary Address 7-bit Hex Address ADDR Pin Termination
1000100b 0x44 GND
1000101b 0x45 VDD
1000110b 0x46 SDA
1000111b 0x47 SCL
2.3.5 INA3221 - Current Monitor
To measure the live current information, a current sense circuit is integrated to the Power section of this
design. The current sensing is done with the INA3221 device. There are two devices used to monitor all
the TPS6521815 PMIC power rails. The wiring is shown in Figure 15. The address pin A0 of the INA3221
device needs to be terminated according to Table 3.

TPS6521815
DCDC1
DCDC2
DCDC3
DCD4
LDO
LS2&3
INA3221
VIN+1
VIN+2
VIN+3
A0
INA3221
VIN+1
VIN+2
VIN+3
A0
VIN-1
VIN-2
VIN-3
SDA
SCL
PV
VIN-1
VIN-2
VIN-3
SDA
SCL
PV
i.MX 7D
VDD_SOC
VDD_ARM
VDD_1V8
I2C3: SDA
I2C3: SCL
GPIO1_IO12
VDD_3V3
NVCC_DRAM,
NVCC_DRAM_CKE
USB and other
peripherals
I2C3: SDA
I2C3: SCL
GPIO1_IO12
These pins require pull-up or pull-down
resistors to set the I2C slave address
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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
Figure 15. INA3221 Current Sensor Wiring From PMIC to Processor
Table 3. INA3221 I2C Slave Address Options
7-BIT BINARY ADDRESS 7-BIT HEX ADDRESS ADDR PIN TERMINATION
1000000b 0x40 GND
1000001b 0x41 VS
1000010b 0x42 SDA
1000011b 0x43 SCL
2.3.6 TPS3808 - Voltage Supervisor for Reset Scheme
The reset scheme for this project is shown in Figure 16. The TPS3808 voltage supervisor senses the
VSNS voltage from the coin-cell. Unless the coin-cell is inserted, the TPS3808 supervisor will prevent the
PMIC from turning on. This is critical to ensure the power-up sequence is correct.
The TPS3808 device has its input MR# connected to RESET Switch and watch dog from processor. If any
of the inputs de-asserts (logic low), then this will disable the PMIC. Once the reset and VSNVS is stable
along with all the power outputs, the PGOOD pin will de-assert the Power-ON Reset (POR_B).

i.MX 7D
GPIO1_IO00
PMIC_ON_REQ
POR_B
GPIO
INT_B
ON/OFF
I2C1:SDA
I2C1:SCK
To Voltage Converters,
DOORWKHU,&¶VXVLQJ
extended I/O Shift
Register
PMIC
TPS6521815
USB2ANY
VSNVS
Supervisory
Circuit
TPS3808G25DBVT
SW_WDOG
PWR_EN
RST#
PGOOD
nPFO
nINT
SDA
SCL
ON/OFF
VSNVS
RESET
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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
Figure 16. Reset Scheme With TPS3808 Supervisor
2.3.7 TLV755P, TPS62067, TPS51200 - Auxiliary Power
Figure 17 shows the full power architecture. Each peripheral device added to a design may require
additional voltage levels not required by the processor. For this design, we had to add 2.5 V for the
Ethernet PHY and 2.8 V for the MIPI CSI. Both of these power rails are generated by a TLV722P fixed-
voltage LDO.
Some designs will also require additional current to power a second rail at the same voltage as a
processor supply. In this case, the mPCIe interface could require up to 1 A of current in addition to the 1.4
A allotted for the NVCC_3V3 supply to the processor and other peripherals (Wi-Fi + Bluetooth, Ethernet,
Audio CODEC, LCD, ALS, eMMC, and NOR Flash). For this reason, the TPS62067 was added to supply
the 3V3_PERI rail for mPCIe. The TPS62067 can also be wired in parallel to the main NVCC_3V3 rail if
needed.
Finally, it is sometimes necessary to terminate DDR memory. DDR termination provides a supply (0.675
V) that is half the voltage of the main supply (1.35 V) with the ability to sink or source current. If only one
channel of DDR is used, the current consumption is low, or the routing is point-to-point, then tapping off
the center of an evenly matched voltage divider may be sufficient. In other cases, a DDR terminator is
needed. For this design, we used the TPS51200 device to terminate the two DDR3L ICs in the system.

TPS6521815
DCDC1
1.0/1.1 V, 1.8 A
DCDC2
1.35 V, 1.8 A
DCDC3
1.8 V, 1.8 A
DCDC4
3.3 V, 1.6 A
LDO
1.5 V, 400 mA
LS1
3.3 V, 920 mA
LS2
920 mA
LS3
900 mA
VDD_SNVS_IN
VDD_SOC
VCC_ARM
VDD_1V8*
VDD_3V3*
NVCC_DRAM,
NVCC_DRAM_CKE
i.MX 7D
USB
OTG
USB
HOST LCD
Audio Codec CAN
Transceiver
2x DDR3L
eMMC Serial NOR
FLASH
WiFi + BT Ethernet
Ambient
Light
Sensor
Audio
Codec
CAN
Transceiver LCD
WiFi + BT Ethernet
MIPI CSI
Ethernet PHY
mPCIe
Ethernet PHY
MIPI CSI
GPIO1
TPS651200
DDR3L Termination
Regulator
EN
USB to UART
FT2232D
DC-DC
3.3 V, 2 A
TPS62067
EN
LDO
2.5 V, 800 mA
TLV75525PDQNR
LDO
2.5 V, 800 mA
TLV75528PDQNR
GPIO1
GPIO1
GPIO1
2V5 @ 0.085 A
2V8 @ 0.04 A
3V3_PERI @ 1A
1V5 @ 250mA
1V0 @ 115mA
1V8 @ 0.25 A
GPIO1
1V35
VREF
3V3 @ 1.4 A
1V35 @
600 mA
5V0 @
1.7 A
3V3 @
100 mA
1V8 @
100 mA
GPIO3
SD
Card
SD Card Voltage
Selector
Switch
BD2204GUL
3V3 / 1V8
VIN
5 V DC
VREF
USB
2.0
Coin
Cell
Dashed boxed represent peripherals
3V3_PERI
3V3 @ 150 mA
1V8 @ 650 mA
1V0/1V1 @ 1.5 A
1V35 @ 85 mA
3 V @ 1 mA
3V3
1V8
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Integrated Power Supply Reference Design for NXP i.MX 7D Processor
Figure 17. TIDA-050034 Full Power Architecture
2.4 System Design Theory
The full power architecture is the result of carefully estimating the power consumed by ICs on the board
and peripherals that can be connected to the board. The ideal power sequencing of the i.MX 7D processor
must be known to ensure the power sequencing of the TPS6521815 is correct. The I2C chain must be
drawn in its entirety to ensure there are no I2C address conflicts. The BOOT Mode settings must be
mapped to boot the processor using the intended memory storage IC. And finally, PCB floor planning must
be completed to make sure the layout of the board is reasonable. All of this system design theory is taken
into consideration in this section.

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2.4.1 Power Estimation
This design is powered from a 5-V adapter. This 5 V is the main power supply to the TPS6521815 device.
The PMIC will generate 5 different voltages: 1.0 V/1.1 V with dynamic voltage scaling (DVS), 1.8 V, 3.3 V,
1.35 V, and 1.5 V. The load switches LS2 and LS3 are used to power ICs and USBs with 5.0 V. The
estimated current consumption for each rail is listed in Table 4.
Table 4. System Power Estimation
VOLTAGE (V) SUPPLY IC, RAIL NAME SUPPLY
CURRENT
(mA)
LOAD IC, RAIL NAME CURRENT
(mA) POWER (mW)
1/1.1 TPS6521815, DCDC1 1800 iMX7 VDD_ARM 500 550
iMX7 VDD_SOC 1000 1100
DP83867 VDD1P1 115 127
1.35 TPS6521815, DCDC2 1800 iMX7 NVCC_DRAM 85 115
DDR3L VDD/VDDQ 295 400
0.675 TPS51200 3000 iMX7 VREF 1 0.675
DDR3L VREF/VTT 295 (max) 200
1.8 TPS6521815, DCDC3 1800 iMX7 NVCC_1P8 625 1125
WL1831MOD Vxx 200 360
DP83867 VDDA1P8 50 90
MIPI CSI 350 630
1.5 TPS6521815, LDO1 400 mPCIe 250 375
3.3 TPS6521815, DCDC4 1600 i.MX7 NVCC_3V3 148 489
MTFC8GAKAJCN-1M WT 150 495
MT25QL256 35 116
WL1831MOD 1105 3647
DP83867 VDDIO 50 165
OPT3001 VDD 0.0037 0.0122
MCP2562 0.5 1.65
WM8960CGEFL 16 53
LCD 15 50
3.3 (Auxiliary) TPS62067 2000 mPCIe 1000 3300
5 TPS6521815, LS2/3 1820 FTD2232D 31 155
2x USB2 Ports 1000 5000
MCP2562 70 350
WM8960CGEFL 511 2555
LCD Not Tested -
2.5 TLV75525P 500 DP83867 VDDA2P5 86 215
2.8 TLV75528PP 500 MIPI CSI 350 980
Total Estimated Power 23 W
2.4.2 Power Sequencing
The processor power sequencing is shown in Figure 18. First the VDD_SNVS needs to turn on up before
any other power. For our design, VDD_SNVS is powered through a coin cell connected directly to the
processor input. Once SNVS voltage is stabilized all other power except NVCC_DRAM and
NVCC_DRAM_CKE can be turned on. NVCC_DRAM and NVCC_CKE can only power up after
VDD_SOC. Once all these voltages stabilize, should lead to power on reset (POR_B).

USB2ANY
i.MX 7Dual
I2C1
PMIC
EEPROM
mPCIe - SMB
Ambient Light
Sensor
LCD
2x Current Sense
AUDIO CODEC
MIPI CSI
PCIe ±Clock
Generator
Level
Translator
I2C2
I2C3
I2C4
Addr: 0x24
Optional
Addr: 0x44
Addr: 0x40,
0x41
Addr: 0x34
Addr: 0x68
VDD_SNVS
VDD_SOC
NVCC_DRAM
All Other
Voltages
POR_B
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Figure 18. Required Power Sequence for i.MX 7D Processor
2.4.3 I2C Device Chain
Figure 19 shows the I2C channel mapping from the processor to each slave device.
Figure 19. I2C Device Chain