Texas Instruments 27 User manual

ADS5525/27/45/46/47 EVM UserGuide
User's Guide
November 2006
SLWU028B

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Contents
1 Overview .................................................................................................................... 51.1 EVM Basic Functions ............................................................................................ 52 EVM Quick Start Guide ................................................................................................ 62.1 EVM LVDS Output Mode Quick Start (Default) .............................................................. 62.2 EVM CMOS Output Mode Quick Start ........................................................................ 63 Circuit Description ...................................................................................................... 73.1 Schematic Diagram .............................................................................................. 73.2 Circuit Function ................................................................................................... 74 Expansion Options .................................................................................................... 134.1 Custom FPGA Code ........................................................................................... 134.2 Expansion Slot .................................................................................................. 134.3 Optional USB SPI Interface ................................................................................... 135 Physical Description .................................................................................................. 145.1 PCB Layout ...................................................................................................... 145.2 Bill of Materials .................................................................................................. 205.3 PCB Schematics ................................................................................................ 25
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List of Figures
1 ADS5547 SNR Performance vs Decoupling ............................................................................. 82 THS4509 + ADS5545 EVM Performance ................................................................................ 93 Eye Diagram of Data on Header J4. ..................................................................................... 114 Top Layer .................................................................................................................... 145 Layer 2, Ground Plane .................................................................................................... 156 Layer 3, Power Plane #1 .................................................................................................. 167 Layer 4, Power Plane #2 .................................................................................................. 178 Layer 5, Ground Plane .................................................................................................... 189 Layer 6, Bottom Layer ..................................................................................................... 19
List of Tables
1 DIP Switch SW1 ............................................................................................................. 72 EVM Power Options ......................................................................................................... 83 Output Connector J4 ....................................................................................................... 104 Test Points .................................................................................................................. 125 Bill of Materials ............................................................................................................. 21
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1 Overview
1.1 EVM Basic Functions
User's GuideSLWU028B – January 2006 – Revised November 2006
This manual assists users in using the ADS5525/27/45/46/47 evaluation module (EVM) for evaluating theperformance of the ADS5525/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability inevaluation of the many features of the ADCs and the performance of the device der many conditions.
Analog input to the ADC is provided via external SMA connectors. The user supplies a single-ended input,which is converted into a differential signal. One input path uses a differential amplifier, while the otherinput is transformer-coupled.
The EVM provides an external SMA connector for input of the ADC clock. The single-ended input isconverted into a differential signal at the input of the device.
Digital output from the EVM is via a 40-pin connector.
Power connections to the EVM are via banana jack sockets. Separate sockets are provided for the ADCanalog and digital supplies, the FPGA supply, and the differential amplifier supply.
CAUTION
Exceeding the maximum input voltages can damage EVM components.Undervoltage may cause improper operation of some or all of the EVMcomponents.
Xilinx, Spartan, WebPACK are trademarks of Xilinx, Inc.All other trademarks are the property of their respective owners.
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2 EVM Quick Start Guide
2.1 EVM LVDS Output Mode Quick Start (Default)
2.2 EVM CMOS Output Mode Quick Start
EVM Quick Start Guide
The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems.Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output modeor CMOS output mode.
Note: Follow the steps in the listed order; not doing so could result in improper operation.
1. Ensure a jumper is installed between pins 1 and 2 on JP2.2. Ensure DIP switch SW1, switch 2 is set to LVDS.3. Ensure DIP switch SW1, switch 8 is set to PARALLEL.4. Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the correspondingreturns connected to J9 and J16.5. Use a regulated power supply to provide a 5-VDC input to J14, while connecting the return to J17.6. Provide a filtered, low-phase-noise, sinusoidal 1.5-Vrms, 170-MHz clock to J7.7. Provide a filtered, sinusoidal analog input to J3.8. Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.
1. Ensure a jumper is installed between pins 2 and 3 on JP2.2. Ensure DIP switch SW1, switch 2 is set to CMOS.3. Ensure DIP switch SW1, switch 8 is set to PARALLEL.4. Use a regulated power supply to provide 3.3 VDC to the ADC at J11 and J15, with the correspondingreturns connected to J9 and J16.5. Use a regulated power supply to provide a 5-VDC input to J14, while connecting the return to J17.6. Provide a low-phase-noise, sinusoidal 1.5-Vrms, 170-MHz clock to J7.7. Provide a filtered sinusoidal analog input to J3.8. Briefly depress S1, which resets the EVM.9. Using a logic analyzer and Table 3 in this manual, monitor the ADC output on J4.
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3 Circuit Description
3.1 Schematic Diagram
3.2 Circuit Function
3.2.1 Configuration Options
3.2.2 Power
Circuit Description
The schematic diagram for the EVM is in Section 5.3 of this document.
The following paragraphs describe the function of individual circuits. See the data sheet for completedevice operating characteristics.
The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM isconfigured for parallel-mode operation. Table 1 describes the functionality of the DIP switches.
Note: When the device is configured for serial-mode operation (SW1, switch 8), the DIP settingson SW1, switch 1 through SW1, switch 7 are ignored.
Table 1. DIP Switch SW1
SW1 SWITCH
OFF ON DESCRIPTIONNUMBER
1 2s complement Offset binary Determines device output format2 LVDS CMOS Determines device output mode3 Reserved Reserved Reserved4 Internal reference External reference When set to External Reference, ADC uses common-modevoltage on TP1.5 Edge = 1 Edge = 2 Allows for output edge programmability6 Edge = 3 Edge = 4 Allows for output edge programmability7 Normal Power down Allows for power down8 Serial Parallel Determines mode for register interface
By switching SW1, switch 8 to OFF, the ADC operates in serial mode, using its programmed registercontents. A complete register map can be found in the device datasheet. Three pins on header J6 havebeen reserved for programming the device while it operates in serial mode. To program the deviceregisters using header J6, place SCLK on pin 21, SDATA on pin 23, and SEN on pin 25. A patterngenerator can be used to generate the patterns needed for programming. Alternatively, TI provides anoptional USB daughtercard that plugs into the expansion slot of the EVM. The USB daughtercard allowsADC register control via a software package loaded onto the PC.
Power is supplied to the EVM via banana jack sockets. The EVM offers the capability to supply analogand digital 3.3 V independently to the ADC. Table 2 offers a snapshot of the power-supply options. Allsupply connections are required for default operation, except J12, J10, J13, and J20.
The EVM provides local decoupling for the ADC; however, the ADC features internal decoupling, and inmany cases minimal external decoupling can be used without loss in performance. Users are encouragedto experiment to find the optimal amount of external decoupling required for their application. Figure 1shows the ADS5547 LVDS-mode performance with all of the decoupling capacitors installed and theperformance with C4, C5, C6, C7, C8, C9, and C10 removed. By default, the EVM comes with all of thedecoupling capacitors installed.
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fIN − Input Frequency − MHz
SNR − Signal-to-Noise Ratio − dBFS
G001
9.97 19.94 30.13 40.33 50.13 60.13 69.59 79.87 89.75 100.33 130.13 170.13
68
69
70
71
72
73
74
1 Decoupling Cap
Baseline-All Decoupling Caps
3.2.3 Analog Inputs
Circuit Description
Table 2. EVM Power Options
BANANA JACK NAME VOLTAGE DESCRIPTION
J9 Device AGND GNDJ10 AGND GNDJ11 Device AVDD 3.3 Device analog supplyJ12 Amplifier negative –5 THS4509 Vs– supplyrailJ13 Amplifier positive rail 5 THS4509 Vs+ supplyJ14 Auxiliary power 5 Supplies power to all peripheral circuitry including the FPGAand PROM. Voltages rails are created by using TI's TPS75003voltage regulator.J15 Device DVDD 3.3 Device internal digital output supplyJ16 DGND GNDJ17 DGND GNDJ20 If TP11, TP12, and TP13 are tied low, the TPS75003 isdisabled. In this case, one can supply 3.3 V to pin 1, 1.2 V topin 2, and 2.2 V to pin 3 of J20 while connecting the ground toJ17.
Figure 1. ADS5547 SNR Performance vs Decoupling
The EVM can be configured to provide the ADC with either transformer-coupled or differential amplifierinputs from a single-ended source. The inputs are provided via SMA connector J3 for transformer-coupledinput or SMA connector J1 for differential amplifier input. To set up for one of these options, the EVM mustbe configured as follows:1. For a 1:1 transformer-coupled input to the ADC, a single-ended source is connected to J3. Confirmthat SJP4 has pins 2 and 3 shorted, and that SJP5 has pins 2 and 3 shorted. The transformer used,the Mini-Circuits TC4-1W, forms an inherent band-pass filter with a pass band from 3 MHz to 800 MHz.This is the default configuration for the EVM.2. One can use a TI THS4509 amplifier to drive the ADC by applying an input to J1. Reconfigure SJP4and SJP5 such that both have pins 1 and 2 shorted. A 5-VDC supply must be connected to the boardto provide power to U3 for this configuration.The THS4509 amplifier path converts a single-ended signal presented on J1 into a differential signal.
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0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
f − Frequency − MHz
Amplitude − dBFS
G002
1
−135
−120
10
−130
−110
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
2
3
4
5x
3.2.4 Clock Input
3.2.5 Digital Outputs
Circuit DescriptionThe schematics present various interface options between the amplifier and the ADC. Depending onthe input frequencies of interest, further performance optimization can be had by designing acorresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filterwith a cutoff frequency of 70 MHz. Figure 2 shows the performance of the ADS5545 using theTHS4509 path.
Figure 2. THS4509 + ADS5545 EVM Performance
A single-ended, harmonically filtered, low-phase-noise, 1.5-Vrms sinusoidal input should be applied to J7.The frequency must not exceed the device specification. In the EVM default configuration, both SPJ1 andSJP2 must have pins 1 and 2 shorted.
In the board default configuration, the transformer provides single-ended to differential conversion. Thetransformer has an impedance ratio of 4.
For compatibility with a broad range of logic analyzers, the EVM outputs 3.3-V parallel CMOS data onheader J4, independent of the ADC operational mode. The Xilinx™Spartan™-3E FPGA provides thenecessary translation, and it configures itself using one of two different logic files stored in the PROM,based on the EVM configuration. The CMOS data output of the FPGA is contained in data header J4 andis a standard 40-pin header on a 100-mil grid, which allows easy connection to a logic analyzer. Theconnector pinout is listed in Table 3 . For quick setup, the eye diagram is shown in Figure 3 . No setup orhold-time adjustments must be made to the logic analyzer if using the rising edge of the output clock tolatch in the data.
Note: The eye diagram shown is the output of the FPGA at 210 MSPS, not that of the ADC. Forthe ADC output timing, see the respective device data sheet.
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Circuit Description
Table 3. Output Connector J4
J4 PIN ADS5525/27 DESCRIPTION ADS5545/46/47 DESCRIPTION
1 CLK CLK2 GND GND3 NC NC4 GND GND5 Reserved Reserved6 GND GND7 Reserved Reserved8 GND GND9 NC Data bit 0 (LSB)10 GND GND11 NC Data bit 112 GND GND13 Data bit 0 (LSB) Data bit 214 GND GND15 Data bit 1 Data bit 316 GND GND17 Data bit 2 Data bit 418 GND GND19 Data bit 3 Data bit 520 GND GND21 Data bit 4 Data bit 622 GND GND23 Data bit 5 Data bit 724 GND GND25 Data bit 6 Data bit 826 GND GND27 Data bit 7 Data bit 928 GND GND29 Data bit 8 Data bit 1030 GND GND31 Data bit 9 Data bit 1132 GND GND33 Data bit 10 Data bit 1234 GND GND35 Data bit 11 (MSB) Data bit 13 (MSB)36 GND GND37 NC NC38 GND GND39 NC NC40 GND GND
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C001
3.2.6 Test Points
Circuit Description
Figure 3. Eye Diagram of Data on Header J4.
For added EVM visibility and control, several test points are provided. Table 4 summarizes the test pointsavailable.
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3.2.7 LED Operation
Circuit Description
Table 4. Test Points
TP DESCRIPTION
TP1 ADC common mode, input or outputdepending on the setting of SW1, switch 4TP3 THS4509 power downTP4 ADC output enableTP5 AGNDTP6 AGNDTP7 AGNDTP8 DGNDTP9 FPGA M0 pin; determines which FPGA logicfile to loadTP10 ADC SCLKTP11 TPS75003 1.2 enableTP12 TPS75003 2.5 enableTP13 TPS75003 3.3 enable
To give greater visibility into the EVM operations, two LEDs are provided, D3 and D4. On power up, D4 isasserted when a successful FPGA boot up is complete. For correct EVM operation, the LED should beasserted at all times. LED D3 is asserted when the ADC and FPGA are operating and decoding in DDRLVDS mode, and is not asserted when the ADC is functioning in CMOS mode. Furthermore, in either DDRLVDS mode or CMOS mode, LED D3 blinks when an ADC overrange condition occurs.
CAUTION
If LED D3 is blinking, the amplitude coming into the ADC input (J3 or J4) mustbe attenuated immediately; otherwise, damage to the ADC could occur.
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4 Expansion Options
4.1 Custom FPGA Code
4.2 Expansion Slot
4.3 Optional USB SPI Interface
Expansion Options
The EVM offers several exciting possibilities to expand the capabilities of the EVM. This allows the utmostflexibility when prototyping an ADC circuit under conditions that mimic the end system, without the need todevelop a custom prototype board.
Using a standard JTAG interface on JP1, users have the ability to load custom logic onto the FPGA,rapidly speeding up digital development time. This allows the flexibility of prototyping and debugging anADC digital interface design before developing application-specific hardware.
To take advantage of the onboard FPGA, users can download the free Xilinx WebPACK™ from the XilinxWeb site. Select the XC3S250E-4FT256 as the FPGA and the XCF16PFSG48 as the PROM.
Note: See the Xilinx Spartan-3E Web site for complete documentation of the FPGA at:http://direct.xilinx.com/bvdocs/publications/ds312.pdf
Schematically, the FPGA is configured in BPI mode, and it samples FPGA pins M2, M1, and M0 when theFPGA's INIT_B is brought low. Depending of the status of M0, it boots from either the top or the bottom ofthe PROM contents. The PROM allows for the storage of two FPGA bit files. In its default condition, theEVM stores one file for ADC CMOS output at the beginning of the PROM address space and one file forADC LVDS output at the end of the PROM address space.
Note: When creating custom FPGA code, store any custom-developed bit files for ADC CMOSoperation in the PROM revision 0 space, and store any custom-developed FPGA code forADC LVDS operation in the PROM revision 1 space.
For those users who make use of a custom FPGA program on the EVM, J5 and J6 provide anexpansion-slot capability. Users can design daughtercards or breakout boards to make use of the unusedFPGA I/O pins which are brought out to the headers.
Note: The EVM provides 5 V from J14 to pin 1 of both J5 and J6. This can be used to providepower to any designed daughtercards.
In most cases, users can use the ADC parallel interface mode to change the operational modes of theADC. For users requiring SPI control of the ADC, TI has developed an optional USB daughter card thatplugs into the expansion slot. With the USB daughter card, users can use a PC interface to communicateto the ADC three-wire SPI interface, which allows for complete control of the ADC register map. Contactthe factory for this optional accessory.
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5 Physical Description
5.1 PCB Layout
K001
Physical Description
This chapter describes the physical characteristics and PCB layout of the EVM.
The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers areshown in Figure 4 through Figure 9 . The layout features split analog and digital ground planes; however,similar performance can be had with careful layout using a single ground plane. Users can connect theanalog and digital ground planes underneath the EVM by soldering the two exposed tinned strips together.
Figure 4. Top Layer
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K002
Physical Description
Figure 5. Layer 2, Ground Plane
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K003
Physical Description
Figure 6. Layer 3, Power Plane #1
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K004
Physical Description
Figure 7. Layer 4, Power Plane #2
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K005
Physical Description
Figure 8. Layer 5, Ground Plane
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K006
Physical Description
Figure 9. Layer 6, Bottom Layer
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5.2 Bill of Materials
Physical Description
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