Texas Instruments UCD3138 Product manual

UCD3138 Digital Power Supply Controller
Technical Reference Manual
Literature Number: SNIU028A
February 2016–Revised April 2016

2SNIU028A–February 2016–Revised April 2016
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Contents
Contents
1 Introduction....................................................................................................................... 30
1.1 Scope of This Document.................................................................................................. 30
1.2 A Guide to Other Documentation for all Members of UCD3138 Family of Products.............................. 30
2 Digital Pulse Width Modulator (DPWM) ................................................................................. 33
2.1 DPWM Block Diagram..................................................................................................... 35
2.2 Introduction to DPWM (DPWM Multi-Mode, Open Loop)............................................................. 37
2.3 DPWM Normal Mode ...................................................................................................... 39
2.4 DPWM Phase Shift Mode................................................................................................. 41
2.5 DPWM Multiple Output Mode (Multi Mode)............................................................................. 42
2.6 DPWM Resonant Mode ................................................................................................... 43
2.7 Triangular Mode............................................................................................................ 45
2.8 DPWM Leading Edge Mode .............................................................................................. 46
2.9 Sync FET Ramp and IDE Calculation ................................................................................... 47
2.10 Automatic Mode Switching................................................................................................ 48
2.10.1 Resonant LLC Example......................................................................................... 48
2.10.2 Mechanism for Automatic Mode Switching ................................................................... 48
2.11 DPWMC, Edge Generation, IntraMax ................................................................................... 50
2.12 Time Resolution of Various DPWM Registers.......................................................................... 51
2.13 PWM Counter and Clocks................................................................................................. 53
2.14 DPWM Registers - Overview ............................................................................................. 53
2.15 DPWM Control Register 0 (DPWMCTRL0)............................................................................. 53
2.15.1 DPWM Auto Config Mid and Max Registers.................................................................. 53
2.15.2 Intra Mux .......................................................................................................... 53
2.15.3 Cycle by Cycle Current Limit Enable .......................................................................... 54
2.15.4 Multi Mode On/Off................................................................................................ 56
2.15.5 Minimum Duty Mode............................................................................................. 56
2.15.6 Master Sync Control Select..................................................................................... 58
2.15.7 Master Sync Slave Enable...................................................................................... 58
2.15.8 D Enable........................................................................................................... 58
2.15.9 Resonant Mode Fixed Duty Enable............................................................................ 58
2.15.10 DPWM A and B Fault Priority ................................................................................. 58
2.15.11 Blank Enable .................................................................................................... 59
2.15.12 DPWM Mode.................................................................................................... 59
2.15.13 DPWM Invert.................................................................................................... 59
2.15.14 1.15.14 Filter Enable (CLA_EN) .............................................................................. 59
2.15.15 DPWM Enable .................................................................................................. 59
2.16 DPWM Control Register 1................................................................................................. 59
2.16.1 Period Counter Preset Enable.................................................................................. 59
2.16.2 Sync FET Ramp Enable......................................................................................... 60
2.16.3 Burst Mode Enable............................................................................................... 60
2.16.4 Current/Flux Balancing Duty Adjust............................................................................ 60
2.16.5 1.16.5 Sync Out Divisor Selection ............................................................................. 60
2.16.6 FIlter Scale........................................................................................................ 60
2.16.7 External Sync Enable............................................................................................ 60
2.16.8 Cycle By Cycle B Side Active Enable ......................................................................... 60

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2.16.9 Auto Mode Switching Enable................................................................................... 60
2.16.10 1.16.10 Event Update Select.................................................................................. 61
2.16.11 Check Override ................................................................................................. 61
2.16.12 Global Period Enable........................................................................................... 61
2.16.13 Using DPWM Pins as General Purpose I/O................................................................. 61
2.16.14 High Resolution enable/disable............................................................................... 62
2.16.15 Asynchronous Protection Disable ............................................................................ 62
2.16.16 Single Frame Enable........................................................................................... 62
2.17 DPWM Control Register 2................................................................................................. 62
2.17.1 External Synchronization Input Divide Ratio.................................................................. 62
2.17.2 Resonant Deadtime Compensation Enable .................................................................. 62
2.17.3 Filter Duty Select................................................................................................. 63
2.17.4 IDeal Diode Emulation (IDE) Enable for PWMB ............................................................. 63
2.17.5 Sample Trigger 1 Oversampling ............................................................................... 63
2.17.6 Sample Trigger 1 Mode ......................................................................................... 63
2.17.7 Sample Trigger Enable Bits..................................................................................... 64
2.18 Period and Event Registers............................................................................................... 64
2.19 Phase Trigger Registers................................................................................................... 64
2.20 Cycle Adjust Registers..................................................................................................... 64
2.21 Resonant Duty Register................................................................................................... 64
2.22 DPWM Fault Control Register............................................................................................ 64
2.23 DPWM Overflow Register................................................................................................. 64
2.24 DPWM Interrupt Register.................................................................................................. 65
2.24.1 DPWM Period Interrupt Bits .................................................................................... 65
2.24.2 Mode Switching Interrupt Bits .................................................................................. 65
2.24.3 INT Bit ............................................................................................................. 65
2.25 DPWM Counter Preset Register ......................................................................................... 65
2.26 Blanking Registers ......................................................................................................... 65
2.27 DPWM Adaptive Sample Register ....................................................................................... 66
2.28 DPWM Fault Status Register ............................................................................................. 66
2.29 DPWM Auto Switch Registers............................................................................................ 66
2.30 DPWM Edge PWM Generation Register................................................................................ 66
2.31 DPWM 0-3 Registers Reference......................................................................................... 66
2.31.1 DPWM Control Register 0 (DPWMCTRL0)................................................................... 66
2.31.2 DPWM Control Register 1 (DPWMCTRL1)................................................................... 70
2.31.3 DPWM Control Register 2 (DPWMCTRL2)................................................................... 73
2.31.4 DPWM Period Register (DPWMPRD)......................................................................... 75
2.31.5 DPWM Event 1 Register (DPWMEV1)........................................................................ 76
2.31.6 DPWM Event 2 Register (DPWMEV2)........................................................................ 77
2.31.7 DPWM Event 3 Register (DPWMEV3)........................................................................ 78
2.31.8 DPWM Event 4 Register (DPWMEV4)........................................................................ 79
2.31.9 DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1).................................................. 80
2.31.10 DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2) ................................................ 81
2.31.11 DPWM Phase Trigger Register (DPWMPHASETRIG) .................................................... 82
2.31.12 DPWM Cycle Adjust A Register (DPWMCYCADJA)....................................................... 83
2.31.13 DPWM Cycle Adjust B Register (DPWMCYCADJB)....................................................... 84
2.31.14 DPWM Resonant Duty Register (DPWMRESDUTY)...................................................... 85
2.31.15 DPWM Fault Control Register (DPWMFLTCTRL) ......................................................... 86
2.31.16 DPWM Overflow Register (DPWMOVERFLOW)........................................................... 87
2.31.17 DPWM Interrupt Register (DPWMINT) ...................................................................... 88
2.31.18 DPWM Counter Preset Register (DPWMCNTPRE)........................................................ 90
2.31.19 DPWM Blanking A Begin Register (DPWMBLKABEG).................................................... 91
2.31.20 DPWM Blanking A End Register (DPWMBLKAEND)...................................................... 92

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2.31.21 DPWM Blanking B Begin Register (DPWMBLKBBEG).................................................... 93
2.31.22 DPWM Blanking B End Register (DPWMBLKBEND)...................................................... 94
2.31.23 DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)....................................... 95
2.31.24 DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO) ...................................... 96
2.31.25 DPWM Adaptive Sample Register (DPWMADAPTIVE)................................................... 97
2.31.26 DPWM Fault Status (DPWMFLTSTAT)...................................................................... 98
2.31.27 DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH) ................. 99
2.31.28 DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH).............. 100
2.31.29 DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH)................ 101
2.31.30 DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH) ............. 102
2.31.31 DPWM Auto Config Max Register (DPWMAUTOMAX).................................................. 103
2.31.32 DPWM Auto Config Mid Register (DPWMAUTOMID).................................................... 105
2.31.33 DPWM Edge PWM Generation Control Register (DPWMEDGEGEN) ................................ 107
2.31.34 DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD)........................................ 109
2.31.35 DPWM BIST Status Register (DPWMBISTSTAT)........................................................ 110
3 Front End......................................................................................................................... 111
3.1 Error ADC and Front End Gain ......................................................................................... 113
3.1.1 Front End Gain................................................................................................... 113
3.1.2 EADC Error Output.............................................................................................. 113
3.1.3 EADC Triggering, EADC Output to Filter..................................................................... 115
3.1.4 EADC Timing..................................................................................................... 115
3.1.5 EADC Averaging................................................................................................. 116
3.1.6 Enabling EADC and Front End ................................................................................ 117
3.2 Front End DAC............................................................................................................ 118
3.3 Ramp Module ............................................................................................................. 119
3.3.1 DAC Ramp Overview............................................................................................ 119
3.3.2 DAC Ramp Start and End Points.............................................................................. 119
3.3.3 DAC Ramp Steps................................................................................................ 120
3.3.4 DAC Ramp Start, Interrupts, Start Delay ..................................................................... 121
3.3.5 RAMPSTAT Register............................................................................................ 121
3.3.6 DAC RAMP when EADC is Saturated ........................................................................ 121
3.3.7 Using Ramp Module for Peak Current Mode ................................................................ 121
3.3.8 Sync FET Soft On/Off using Ramp Module .................................................................. 122
3.4 Successive Approximation Mode....................................................................................... 123
3.4.1 SAR Control Parameters ....................................................................................... 123
3.4.2 SAR Algorithm Overview ....................................................................................... 123
3.4.3 Non-Continuous SAR Mode.................................................................................... 123
3.4.4 Continuous SAR Mode.......................................................................................... 123
3.5 Absolute Value Without SAR............................................................................................ 124
3.6 EADC Modes.............................................................................................................. 124
3.7 Front End Control Registers............................................................................................. 124
3.7.1 Ramp Control Register (RAMPCTRL) ....................................................................... 124
3.7.2 Ramp Status Register (RAMPSTAT) ......................................................................... 126
3.7.3 Ramp Cycle Register (RAMPCYCLE) ........................................................................ 127
3.7.4 EADC DAC Value Register (EADCDAC)..................................................................... 128
3.7.5 Ramp DAC Ending Value Register (RAMPDACEND)...................................................... 129
3.7.6 DAC Step Register (DACSTEP)............................................................................... 130
3.7.7 DAC Saturation Step Register (DACSATSTEP)............................................................. 131
3.7.8 EADC Trim Register (EADCTRIM) – (For Factory Test Use Only) ....................................... 132
3.7.9 EADC Control Register (EADCCTRL) ........................................................................ 133
3.7.10 Analog Control Register (ACTRL) (For Test Use Only) ................................................... 135
3.7.11 Pre-Bias Control Register 0 (PREBIASCTRL0) ............................................................ 136
3.7.12 Pre-Bias Control Register 1 (PREBIASCTRL1) ............................................................ 137

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3.7.13 SAR Control Register (SARCTRL)........................................................................... 138
3.7.14 SAR Timing Register (SARTIMING) ......................................................................... 139
3.7.15 EADC Value Register (EADCVALUE) ....................................................................... 140
3.7.16 EADC Raw Value Register (EADCRAWVALUE)........................................................... 141
3.7.17 DAC Status Register (DACSTAT)............................................................................ 142
4 Filter ............................................................................................................................... 143
4.1 Filter Math Details ........................................................................................................ 144
4.1.1 Filter Input and Branch Calculations .......................................................................... 144
4.1.2 Proportional Branch ............................................................................................. 145
4.1.3 Integral Branch................................................................................................... 145
4.1.4 Differential Branch............................................................................................... 145
4.1.5 Add, Saturate, Scale and Clamp .............................................................................. 146
4.1.6 Filter Output Stage............................................................................................... 147
4.2 Filter Status Register..................................................................................................... 148
4.3 Filter Control Register.................................................................................................... 148
4.3.1 Filter Enable...................................................................................................... 149
4.3.2 Use CPU Sample................................................................................................ 149
4.3.3 Force Start........................................................................................................ 149
4.3.4 Kp Off, Kd Off, Ki Off............................................................................................ 149
4.3.5 Kd Stall, Ki Stall.................................................................................................. 149
4.3.6 Nonlinear Mode .................................................................................................. 149
4.3.7 Output Scaling.................................................................................................... 149
4.3.8 Output Multiplier Select ......................................................................................... 150
4.3.9 Switching Period as Output Multiplier......................................................................... 150
4.3.10 KComp as Output Multiplier................................................................................... 151
4.3.11 Feed Forward as Output Multiplier ........................................................................... 151
4.3.12 Period Multiplier Select ........................................................................................ 151
4.3.13 Ki Adder Mode .................................................................................................. 151
4.4 XN, YN Read and Write Registers ..................................................................................... 152
4.4.1 CPU Xn Register................................................................................................. 152
4.4.2 Filter XN Read Register......................................................................................... 152
4.4.3 Filter YN Read Registers ....................................................................................... 152
4.5 Coefficient Configuration Register...................................................................................... 153
4.6 Kp, Ki, and Kd Registers................................................................................................. 155
4.7 Alpha Registers ........................................................................................................... 155
4.8 Filter Nonlinear Limit Registers ......................................................................................... 155
4.9 Clamp Registers .......................................................................................................... 156
4.10 Filter Preset Register..................................................................................................... 156
4.11 Filter Registers Reference............................................................................................... 156
4.11.1 Filter Status Register (FILTERSTATUS) .................................................................... 156
4.11.2 Filter Control Register (FILTERCTRL)....................................................................... 158
4.11.3 CPU XN Register (CPUXN)................................................................................... 160
4.11.4 Filter XN Read Register (FILTERXNREAD) ................................................................ 161
4.11.5 Filter KI_YN Read Register (FILTERKIYNREAD).......................................................... 162
4.11.6 Filter KD_YN Read Register (FILTERKDYNREAD) ....................................................... 163
4.11.7 Filter YN Read Register (FILTERYNREAD) ................................................................ 164
4.11.8 Coefficient Configuration Register (COEFCONFIG) ....................................................... 165
4.11.9 Filter KP Coefficient 0 Register (FILTERKPCOEF0)....................................................... 168
4.11.10 Filter KP Coefficient 1 Register (FILTERKPCOEF1)..................................................... 169
4.11.11 Filter KI Coefficient 0 Register (FILTERKICOEF0) ...................................................... 170
4.11.12 Filter KI Coefficient 1 Register (FILTERKICOEF1) ....................................................... 171
4.11.13 Filter KD Coefficient 0 Register (FILTERKDCOEF0)..................................................... 172
4.11.14 Filter KD Coefficient 1 Register (FILTERKDCOEF1)..................................................... 173

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4.11.15 Filter KD Alpha Register (FILTERKDALPHA) ............................................................. 174
4.11.16 Filter Nonlinear Limit Register 0 (FILTERNL0)............................................................ 175
4.11.17 Filter Nonlinear Limit Register 1 (FILTERNL1)............................................................ 176
4.11.18 Filter Nonlinear Limit Register 2 (FILTERNL2)............................................................ 177
4.11.19 Filter KI Feedback Clamp High Register (FILTERKICLPHI) ............................................ 178
4.11.20 Filter KI Feedback Clamp Low Register (FILTERKICLPLO) ............................................ 179
4.11.21 Filter YN Clamp High Register (FILTERYNCLPHI)....................................................... 180
4.11.22 Filter YN Clamp Low Register (FILTERYNCLPLO) ...................................................... 181
4.11.23 Filter Output Clamp High Register (FILTEROCLPHI).................................................... 182
4.11.24 Filter Output Clamp Low Register (FILTEROCLPLO).................................................... 183
4.11.25 Filter Preset Register (FILTERPRESET)................................................................... 184
5 Loop Mux......................................................................................................................... 185
5.1 Front End Control Muxes (FECTRL0MUX, FECTRL1MUX, FECTRL2MUX) .................................... 187
5.2 Sample Trigger Control (SAMPTRIGCTRL)........................................................................... 187
5.3 External DAC Control (EXTDACCTRL)................................................................................ 187
5.4 Filter Mux Register (FILTERMUX)...................................................................................... 188
5.5 Filter KComp Registers (FILTERKCOMPx) ........................................................................... 188
5.6 DPWM Mux Register (DPWMMUX) ................................................................................... 188
5.7 Global Enable Register (GLBEN)....................................................................................... 188
5.8 PWM Global Period Register (PWMGLBPRD) ....................................................................... 189
5.9 Sync Control (SYNCCTRL).............................................................................................. 189
5.10 Light Load (Burst) Mode ................................................................................................. 189
5.11 Constant Current / Constant Power.................................................................................... 189
5.12 Analog Peak Current Mode.............................................................................................. 190
5.13 Automatic Cycle Adjustment ............................................................................................ 190
5.13.1 Calculation....................................................................................................... 190
5.13.2 Configuration .................................................................................................... 191
5.13.3 Scaling ........................................................................................................... 191
5.14 Loop Mux Registers Reference......................................................................................... 191
5.14.1 Front End Control 0 Mux Register (FECTRL0MUX) ....................................................... 191
5.14.2 Front End Control 1 Mux Register (FECTRL1MUX) ....................................................... 193
5.14.3 Front End Control 2 Mux Register (FECTRL2MUX) ....................................................... 195
5.14.4 Sample Trigger Control Register (SAMPTRIGCTRL)...................................................... 197
5.14.5 External DAC Control Register (EXTDACCTRL) .......................................................... 198
5.14.6 Filter Mux Register (FILTERMUX) ........................................................................... 199
5.14.7 Filter KComp A Register (FILTERKCOMPA) ............................................................... 201
5.14.8 Filter KComp B Register (FILTERKCOMPB) ............................................................... 202
5.14.9 DPWM Mux Register (DPWMMUX) ......................................................................... 203
5.14.10 Constant Power Control Register (CPCTRL) ............................................................. 205
5.14.11 Constant Power Nominal Threshold Register (CPNOM) ................................................ 207
5.14.12 Constant Power Max Threshold Register (CPMAX) ..................................................... 208
5.14.13 Constant Power Configuration Register (CPCONFIG) .................................................. 209
5.14.14 Constant Power Max Power Register (CPMAXPWR) ................................................... 210
5.14.15 Constant Power Integrator Threshold Register (CPINTTHRESH) ..................................... 211
5.14.16 Constant Power Firmware Divisor Register (CPFWDIVISOR) ......................................... 212
5.14.17 Constant Power Status Register (CPSTAT) .............................................................. 213
5.14.18 Cycle Adjustment Control Register (CYCADJCTRL) .................................................... 214
5.14.19 Cycle Adjustment Limit Register (CYCADJLIM) .......................................................... 215
5.14.20 Cycle Adjustment Status Register (CYCADJSTAT) ..................................................... 216
5.14.21 Global Enable Register (GLBEN)........................................................................... 217
5.14.22 PWM Global Period Register (PWMGLBPRD)............................................................ 218
5.14.23 Sync Control Register (SYNCCTRL) ....................................................................... 219
5.14.24 Light Load Control Register (LLCTRL)..................................................................... 220

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5.14.25 Light Load Enable Threshold Register (LLENTHRESH)................................................. 221
5.14.26 Light Load Disable Threshold Register (LLDISTHRESH) ............................................... 222
5.14.27 Peak Current Mode Control Register (PCMCTRL) ....................................................... 223
5.14.28 Analog Peak Current Mode Control Register (APCMCTRL) ............................................ 224
5.14.29 Loop Mux Test Register (LOOPMUXTEST) (Test Use Only)........................................... 225
6 Fault Mux......................................................................................................................... 226
6.1 Analog Comparator Configuration...................................................................................... 228
6.1.1 ACOMP_EN ...................................................................................................... 228
6.1.2 ACOMP_x_THRESH............................................................................................ 228
6.1.3 ACOMP_x_POL.................................................................................................. 228
6.1.4 ACOMP_x_INT_EN ............................................................................................. 228
6.1.5 ACOMP_x_OUT_EN............................................................................................ 228
6.1.6 ACOMP_x_SEL.................................................................................................. 228
6.1.7 ACOMP_F_REF_SEL........................................................................................... 229
6.1.8 ACOMPCTRL Register Arrangement......................................................................... 229
6.2 Analog Comparator Ramp............................................................................................... 229
6.3 Digital Comparator Configuration....................................................................................... 229
6.4 Fault Pin Configuration................................................................................................... 230
6.5 Analog Peak Current ..................................................................................................... 230
6.6 Fault Status Registers.................................................................................................... 230
6.7 Fault Mux Control Registers............................................................................................. 230
6.8 DPWM Fault Action....................................................................................................... 231
6.9 IDE / DCM Detection Control............................................................................................ 232
6.10 Oscillator Failure Detection.............................................................................................. 234
6.10.1 High Frequency Oscillator Failure Detection................................................................ 234
6.10.2 Low Frequency Oscillator Failure Detection ................................................................ 234
6.11 Fault Mux Registers Reference......................................................................................... 234
6.11.1 Analog Comparator Control 0 Register (ACOMPCTRL0) ................................................ 234
6.11.2 Analog Comparator Control 1 Register (ACOMPCTRL1) ................................................ 237
6.11.3 Analog Comparator Control 2 Register (ACOMPCTRL2) ................................................ 239
6.11.4 Analog Comparator Control 3 Register (ACOMPCTRL3) ................................................ 241
6.11.5 External Fault Control Register (EXTFAULTCTRL) ....................................................... 242
6.11.6 Fault Mux Interrupt Status Register (FAULTMUXINTSTAT) ............................................. 243
6.11.7 Fault Mux Raw Status Register (FAULTMUXRAWSTAT) ................................................ 245
6.11.8 Comparator Ramp Control 0 Register (COMPRAMP0) .................................................. 247
6.11.9 Digital Comparator Control 0 Register (DCOMPCTRL0).................................................. 249
6.11.10 Digital Comparator Control 1 Register (DCOMPCTRL1) ................................................ 250
6.11.11 Digital Comparator Control 2 Register (DCOMPCTRL2) ................................................ 251
6.11.12 Digital Comparator Control 3 Register (DCOMPCTRL3) ................................................ 252
6.11.13 Digital Comparator Counter Status Register (DCOMPCNTSTAT) ..................................... 253
6.11.14 DPWM 0 Current Limit Control Register (DPWM0CLIM)................................................ 254
6.11.15 DPWM 0 Fault AB Detection Register (DPWM0FLTABDET) ........................................... 256
6.11.16 DPWM 0 Fault Detection Register (DPWM0FAULTDET) ............................................... 257
6.11.17 DPWM 1 Current Limit Control Register (DPWM1CLIM)................................................ 260
6.11.18 DPWM 1 Fault AB Detection Register (DPWM1FLTABDET) ........................................... 262
6.11.19 DPWM 1 Fault Detection Register (DPWM1FAULTDET) ............................................... 264
6.11.20 DPWM 2 Current Limit Control Register (DPWM2CLIM)................................................ 267
6.11.21 DPWM 2 Fault AB Detection Register (DPWM2FLTABDET) ........................................... 269
6.11.22 DPWM 2 Fault Detection Register (DPWM2FAULTDET) ............................................... 271
6.11.23 DPWM 3 Current Limit Control Register (DPWM3CLIM)................................................ 274
6.11.24 DPWM 3 Fault AB Detection Register (DPWM3FLTABDET) ........................................... 276
6.11.25 DPWM 3 Fault Detection Register (DPWM3FAULTDET) ............................................... 278
6.11.26 HFO Fail Detect Register (HFOFAILDET)................................................................. 281

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6.11.27 LFO Fail Detect Register (LFOFAILDET).................................................................. 282
6.11.28 IDE Control Register (IDECTRL)............................................................................ 283
7 GIO Module...................................................................................................................... 284
7.1 Fault IO Direction Register (FAULTDIR)............................................................................... 285
7.2 Fault Input Register (FAULTIN)......................................................................................... 286
7.3 Fault Output Register (FAULTOUT).................................................................................... 287
7.4 Fault Interrupt Enable Register (FAULTINTENA) .................................................................... 288
7.5 Fault Interrupt Polarity Register (FAULTINTPOL).................................................................... 289
7.6 Fault Interrupt Pending Register (FAULTINTPEND)................................................................. 290
7.7 External Interrupt Direction Register (EXTINTDIR) .................................................................. 291
7.8 External Interrupt Input Register (EXTINTIN)......................................................................... 292
7.9 External Interrupt Output Register (EXTINTOUT).................................................................... 293
7.10 External Interrupt Enable Register (EXTINTENA).................................................................... 294
7.11 External Interrupt Polarity Register (EXTTINTPOL).................................................................. 295
7.12 External Interrupt Pending Register (EXTINTPEND) ................................................................ 296
7.13 References ................................................................................................................ 296
8 ADC12 Overview............................................................................................................... 297
8.1 ADC12 Input Impedance Model ........................................................................................ 299
8.2 ADC12 Impedance vs. Sampling Frequency Data................................................................... 300
8.3 Effect of External Capacitance.......................................................................................... 301
8.4 Channel to Channel Crosstalk .......................................................................................... 301
8.5 Impedance Roll-Off Due to Crosstalk .................................................................................. 302
8.6 ADC12 Control FSM...................................................................................................... 302
8.7 Conversion................................................................................................................. 302
8.8 Sequencing................................................................................................................ 303
8.9 Digital Comparators ...................................................................................................... 304
8.10 ADC Averaging............................................................................................................ 305
8.11 Temperature Sensor ..................................................................................................... 305
8.12 Temp Sensor Control Register (TEMPSENCTRL)................................................................... 306
8.13 PMBus Addressing ....................................................................................................... 307
8.13.1 PMBus Control Register 3 (PMBCTRL3).................................................................... 307
8.14 Dual Sample and Hold................................................................................................... 308
8.14.1 ADC Control Register (ADCCTRL)........................................................................... 309
8.15 Usage of Sample and Hold Circuitry for High Impedance Measurement ......................................... 309
8.15.1 C Code Example................................................................................................ 311
8.16 ADC Configuration Examples........................................................................................... 311
8.16.1 Software Initiated Conversions ............................................................................... 311
8.16.2 Single Sweep Operation....................................................................................... 312
8.16.3 Auto-Triggered Conversions .................................................................................. 313
8.16.4 Continuous Conversions....................................................................................... 313
8.16.5 Start/Stop Operation (External Trigger)...................................................................... 314
8.17 Useful C Language Statement Examples ............................................................................. 315
8.18 ADC Registers ............................................................................................................ 316
8.18.1 ADC Control Register (ADCCTRL) .......................................................................... 316
8.18.2 ADC Status Register (ADCSTAT) ........................................................................... 318
8.18.3 ADC Test Control Register (ADCTSTCTRL)................................................................ 319
8.18.4 ADC Sequence Select Register 0 (ADCSEQSEL0) ....................................................... 320
8.18.5 ADC Sequence Select Register 1 (ADCSEQSEL1) ....................................................... 321
8.18.6 ADC Sequence Select Register 2 (ADCSEQSEL2) ....................................................... 322
8.18.7 ADC Sequence Select Register 3 (ADCSEQSEL3) ....................................................... 323
8.18.8 ADC Result Registers 0-15 (ADCRESULTx, x=0:15)...................................................... 324
8.18.9 ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15)..................................... 325
8.18.10 ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5)................................... 326

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8.18.11 ADC Digital Compare Enable Register (ADCCOMPEN)................................................. 327
8.18.12 ADC Digital Compare Results Register (ADCCOMPRESULT)......................................... 329
8.18.13 ADC Averaging Control Register (ADCAVGCTRL)....................................................... 331
9 Advanced Power Management Control Functions................................................................. 333
9.1 Package ID Information.................................................................................................. 334
9.2 Brownout................................................................................................................... 334
9.3 Temperature Sensor Control............................................................................................ 334
9.4 I/O Mux Control ........................................................................................................... 334
9.5 Current Sharing Control.................................................................................................. 334
9.6 Temperature Reference.................................................................................................. 336
9.7 Power Disable Control or (Clock Gating Control) .................................................................... 336
9.8 Miscellaneous Analog Control Registers .............................................................................. 336
9.8.1 Package ID Register (PKGID) ................................................................................. 336
9.8.2 Brownout Register (BROWNOUT) ............................................................................ 337
9.8.3 Temp Sensor Control Register (TEMPSENCTRL).......................................................... 338
9.8.4 I/O Mux Control Register (IOMUX)............................................................................ 339
9.8.5 Current Sharing Control Register (CSCTRL) ................................................................ 340
9.8.6 Temperature Reference Register (TEMPREF) .............................................................. 341
9.8.7 Power Disable Control Register (PWRDISCTRL)........................................................... 342
9.9 GPIO Overview ........................................................................................................... 343
9.10 Interaction with a Single Pin............................................................................................. 344
9.11 Interaction with Multiple Pins............................................................................................ 345
9.12 Registers................................................................................................................... 346
9.12.1 Global I/O EN Register (GBIOEN) ........................................................................... 346
9.12.2 Global I/O OE Register (GLBIOOE).......................................................................... 347
9.12.3 Global I/O Open Drain Control Register (GLBIOOD)...................................................... 348
9.12.4 Global I/O Value Register (GLBIOVAL) ..................................................................... 349
9.12.5 Global I/O Read Register (GLBIOREAD).................................................................... 350
9.13 Trim and Test Registers - Note ......................................................................................... 351
9.13.1 Clock Trim Register (CLKTRIM) (For Factory Test Use Only, Except HFO_LN_FILTER_EN) ...... 351
10 PMBus Interface/I2C Interface ............................................................................................ 352
10.1 PMBus Register Summary .............................................................................................. 353
10.2 PMBus Slave Mode Initialization........................................................................................ 353
10.2.1 Initialization for Polling and Maximum Automatic Acknowledgement.................................... 353
10.2.2 Initialization for Interrupts and for Manual Acknowledgement ............................................ 353
10.2.3 Initialization for I2C ............................................................................................. 354
10.2.4 Initialization for Advanced Features in Some Devices..................................................... 354
10.3 PMBus Slave Mode Command Examples............................................................................. 355
10.3.1 Write Command (Send Byte), No PEC ...................................................................... 355
10.3.2 Other Simple Writes with Auto Acknowledge ............................................................... 357
10.3.3 Quick Command Write......................................................................................... 358
10.3.4 Writes of 4 Bytes or More With Full Auto Acknowledge................................................... 358
10.3.5 Writes with Less than 3 Bytes Auto-Acknowledged........................................................ 360
10.3.6 Manual Slave Address ACK for Write........................................................................ 360
10.3.7 Manual Command ACK........................................................................................ 361
10.3.8 Read Messages with Full Automation ....................................................................... 361
10.3.9 Simple Read of 4 Bytes with Full Automation............................................................... 362
10.3.10 Simple Read of More than 4 Bytes with Full Automation................................................ 363
10.3.11 Quick Command Read ....................................................................................... 364
10.3.12 Simple Read with Manual Slave Address ACK ........................................................... 364
10.3.13 Write/Read with Repeated Start............................................................................. 365
10.3.14 Automatic PEC Addition...................................................................................... 366
10.4 Avoiding Clock Stretching ............................................................................................... 367

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10.4.1 Using Early TXBUF Write to Avoid Clock Stretch.......................................................... 367
10.4.2 Alert Response.................................................................................................. 368
10.5 PMBus Slave Mode Low Level Timing................................................................................. 369
10.6 Effect of MAN_SLAVE_ACK bit on EOM Handling .................................................................. 371
10.7 Master Mode Operation Reference..................................................................................... 372
10.7.1 Quick Command................................................................................................ 373
10.7.2 Send Byte........................................................................................................ 373
10.7.3 Receive Byte .................................................................................................... 373
10.7.4 Write Byte/Word ................................................................................................ 374
10.7.5 Read Byte/Read Word......................................................................................... 375
10.7.6 Process Call..................................................................................................... 376
10.7.7 Block Write ...................................................................................................... 377
10.7.8 Block Read ...................................................................................................... 378
10.7.9 Block Write-Block Read Process Call........................................................................ 379
10.7.10 Alert Response ................................................................................................ 379
10.7.11 Extended Command - Write Byte/Word, Read Byte/Word .............................................. 380
10.7.12 Group Command.............................................................................................. 381
10.8 PMBUS Communications Fault Handling.............................................................................. 381
10.8.1 Bit Counter....................................................................................................... 381
10.8.2 Test Mode (Manufacturer Reserved Address Match)...................................................... 382
10.9 Other Functions of the PMBus Module ................................................................................ 382
10.10 PMBus Interface Registers Reference ................................................................................ 382
10.10.1 PMBUS Control Register 1 (PMBCTRL1) ................................................................. 382
10.10.2 PMBus Transmit Data Buffer (PMBTXBUF)............................................................... 384
10.10.3 PMBus Receive Data Register (PMBRXBUF) ............................................................ 385
10.10.4 PMBus Acknowledge Register (PMBACK) ................................................................ 386
10.10.5 PMBus Status Register (PMBST)........................................................................... 387
10.10.6 PMBus Interrupt Mask Register (PMBINTM).............................................................. 389
10.10.7 PMBus Control Register 2 (PMBCTRL2) .................................................................. 390
10.10.8 PMBus Hold Slave Address Register (PMBHSA)......................................................... 392
10.10.9 PMBus Control Register 3 (PMBCTRL3) .................................................................. 393
11 Timer Module Overview..................................................................................................... 396
11.1 T24 – 24 Bit Free-Running Timer with Capture and Compare ..................................................... 397
11.2 T24 Clock Source, Prescaler and Counter............................................................................ 397
11.3 T24 Capture Block........................................................................................................ 398
11.4 T24 Compare Blocks..................................................................................................... 399
11.5 T24 Interrupts ............................................................................................................. 399
11.6 T16PWMx - 16 Bit PWM Timers ....................................................................................... 399
11.7 T16PWMx Summary ..................................................................................................... 399
11.8 T16PWMx Prescaler and Counter...................................................................................... 400
11.9 T16PWMx Compare Blocks............................................................................................. 400
11.10 T16 Shadow Bit........................................................................................................... 401
11.11 T16 Interrupts............................................................................................................. 401
11.12 Using the T16 for a Timer Interrupt .................................................................................... 402
11.13 Using the T16 for PWM Generation.................................................................................... 402
11.14 WD - Watchdog........................................................................................................... 402
11.15 Watchdog Prescale and Counter....................................................................................... 403
11.16 Watchdog Compare Blocks ............................................................................................. 403
11.17 Watchdog Protect Bit .................................................................................................... 403
11.18 Watchdog Timer Example............................................................................................... 404
11.19 Warnings for Watchdog Status Register .............................................................................. 404
11.20 System Fault Recovery Basics ......................................................................................... 404
11.21 Timer Module Register Reference ..................................................................................... 405

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11.21.1 24-bit Counter Data Register (T24CNTDAT).............................................................. 405
11.21.2 24-bit Counter Control Register (T24CNTCTRL) ......................................................... 406
11.21.3 24-bit Capture Channel Data Register (T24CAPDAT) or (T24CAPDATx) ............................ 407
11.21.4 24-bit Capture Channel Control Register (T24CAPCTRLx or T24CAPCTRL......................... 408
11.21.5 24-bit Capture I/O Control and Data Register (T24CAPIO) ............................................. 409
11.21.6 24-bit Output Compare Channel 0 Data Register (T24CMPDAT0) .................................... 410
11.21.7 24-bit Output Compare Channel 1 Data Register (T24CMPDAT1) .................................... 411
11.21.8 24-bit Output Compare Channel 0 Control Register (T24CMPCTRL0)................................ 412
11.21.9 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1)................................ 413
11.21.10 PWMx Counter Data Register (T16PWMxCNTDAT) ................................................... 414
11.21.11 PWMx Counter Control Register (T16PWMxCNTCTRL)............................................... 415
11.21.12 PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT)......................... 416
11.21.13 PWMx Compare Control Register (T16PWMxCMPCTRL)............................................. 417
11.21.14 Watchdog Status (WDST).................................................................................. 419
11.21.15 Watchdog Control (WDCTRL) ............................................................................. 420
12 UART Overview ................................................................................................................ 421
12.1 UART Frame Format..................................................................................................... 422
12.2 Asynchronous Timing Mode............................................................................................. 422
12.3 UART Interrupts........................................................................................................... 423
12.4 Transmit Interrupt......................................................................................................... 424
12.5 Receive Interrupt.......................................................................................................... 424
12.6 Error Interrupts............................................................................................................ 424
12.7 UART Registers Reference ............................................................................................. 426
12.7.1 UART Control Register 0 (UARTCTRL0) ................................................................... 426
12.7.2 UART Receive Status Register (UARTRXST) ............................................................. 427
12.7.3 UART Transmit Status Register (UARTTXST) ............................................................. 428
12.7.4 UART Control Register 3 (UARTCTRL3) ................................................................... 429
12.7.5 UART Interrupt Status Register (UARTINTST) ............................................................ 430
12.7.6 UART Baud Divisor High Byte Register (UARTHBAUD) ................................................. 431
12.7.7 UART Baud Divisor Middle Byte Register (UARTMBAUD) .............................................. 432
12.7.8 UART Baud Divisor Low Byte Register (UARTLBAUD)................................................... 433
12.7.9 UART Receive Buffer (UARTRXBUF) ....................................................................... 434
12.7.10 UART Transmit Buffer (UARTTXBUF) ..................................................................... 435
12.7.11 UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX)........... 436
13 Boot ROM and Boot Flash ................................................................................................. 437
13.1 Boot ROM Function ...................................................................................................... 438
13.1.1 Initializing UCD3138............................................................................................ 438
13.1.2 Verifying Checksums........................................................................................... 438
13.1.3 Uses for 2 Different Checksums.............................................................................. 438
13.1.4 Avoiding Program Flash Lockup.............................................................................. 440
13.1.5 Using BOOT ROM PMBus Interface......................................................................... 441
13.2 Memory Read Functionality ............................................................................................. 441
13.2.1 Configure Read Address....................................................................................... 441
13.2.2 Read 4 Bytes.................................................................................................... 442
13.2.3 Read 16 Bytes .................................................................................................. 442
13.2.4 Read Next 16 Bytes............................................................................................ 442
13.3 Read Version.............................................................................................................. 442
13.4 Memory Write Functionality ............................................................................................. 443
13.4.1 Write 4 Bytes.................................................................................................... 443
13.4.2 Write 16 Bytes................................................................................................... 443
13.4.3 Write Next 16 Bytes ............................................................................................ 444
13.5 Flash Functions ........................................................................................................... 444
13.5.1 Mass Erase...................................................................................................... 444

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13.5.2 Page Erase...................................................................................................... 445
13.5.3 Execute Flash................................................................................................... 446
13.5.4 Flash Programming Sequence using Boot ROM........................................................... 446
13.6 Checksum Functions..................................................................................................... 447
13.6.1 Calculation of Checksum ...................................................................................... 447
13.6.2 Reading Checksum............................................................................................. 447
13.7 Trim Flash Checksum Verification...................................................................................... 447
13.8 Boot ROM for the Other Members of the UCD3138 Family ........................................................ 448
13.8.1 UCD3138064 and UCD3138064A............................................................................ 448
13.8.2 UCD3138A64 and UCD3138A64A........................................................................... 449
13.8.3 UCD3138128 and UCD3138128A............................................................................ 450
14 ARM7TDMI-S MPUSS ........................................................................................................ 452
14.1 ARM7TDMI-S Modes of Operation..................................................................................... 453
14.1.1 Exceptions....................................................................................................... 455
14.2 Hardware Interrupts ...................................................................................................... 455
14.2.1 Standard Interrupt (IRQ)....................................................................................... 455
14.2.2 Fast Interrupt (FIQ)............................................................................................. 456
14.3 Software Interrupt......................................................................................................... 456
14.4 ARM7TDMI-S Instruction Set ........................................................................................... 457
14.4.1 Instruction Compression....................................................................................... 457
14.4.2 The Thumb Instruction Set .................................................................................... 457
14.5 Dual-State Interworking.................................................................................................. 457
14.5.1 Level of Dual-State Support................................................................................... 458
14.5.2 Implementation.................................................................................................. 459
14.5.3 Naming Conventions for Entry Points (CCS 3.x)........................................................... 459
14.5.4 Indirect Calls..................................................................................................... 459
14.5.5 UCD3138 Reference Code.................................................................................... 461
15 Memory ........................................................................................................................... 465
15.1 Memory Controller – MMC Registers Reference..................................................................... 468
15.1.1 Static Memory Control Register (SMCTRL)................................................................. 468
15.1.2 Write Control Register (WCTRL) ............................................................................. 470
15.1.3 Peripheral Control Register (PCTRL)........................................................................ 471
15.1.4 Peripheral Location Register (PLOC)........................................................................ 472
15.1.5 Peripheral Protection Register (PPROT) .................................................................... 473
15.2 DEC – Address Manager Registers Reference....................................................................... 473
15.2.1 Memory Fine Base Address High Register 0 (MFBAHR0)................................................ 473
15.2.2 Memory Fine Base Address Low Register 0 (MFBALR0)................................................. 475
15.2.3 1.1.1 Memory Fine Base Address High Register 1-3,17-19 (MFBAHRx)............................... 476
15.2.4 Memory Fine Base Address Low Register 1-3, 17-19 (MFBALRx)...................................... 477
15.2.5 Memory Fine Base Address High Load Differences for Enhanced 3138 Devices..................... 478
15.2.6 Memory Fine Base Address High Register 4 (MFBAHR4)................................................ 479
15.2.7 Memory Fine Base Address Low Register 4-16 (MFBALRx)............................................. 480
15.2.8 Memory Fine Base Address High Register 5 (MFBAHR5)................................................ 481
15.2.9 Memory Fine Base Address High Register 6 (MFBAHR6)................................................ 482
15.2.10 Memory Fine Base Address High Register 7 (MFBAHR7) .............................................. 483
15.2.11 Memory Fine Base Address High Register 8 (MFBAHR8) .............................................. 484
15.2.12 Memory Fine Base Address High Register 9 (MFBAHR9) .............................................. 485
15.2.13 Memory Fine Base Address High Register 10 (MFBAHR10) ........................................... 486
15.2.14 Memory Fine Base Address High Register 11 (MFBAHR11) ........................................... 487
15.2.15 Memory Fine Base Address High Register 12 (MFBAHR12) ........................................... 488
15.2.16 Memory Fine Base Address High Register 13 (MFBAHR13) ........................................... 489
15.2.17 Memory Fine Base Address High Register 14 (MFBAHR14) ........................................... 490
15.2.18 Memory Fine Base Address High Register 15 (MFBAHR15) ........................................... 491

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15.2.19 Memory Fine Base Address High Register 16 (MFBAHR16) ........................................... 492
15.2.20 Program Flash Control Register (PFLASHCTRL) ........................................................ 493
15.2.21 Data Flash Control Register (DFLASHCTRL)............................................................. 494
15.2.22 Flash Interlock Register (FLASHILOCK)................................................................... 495
16 Control System Module ..................................................................................................... 496
16.1 Address Decoder (DEC)................................................................................................. 497
16.1.1 Memory Mapping Basics....................................................................................... 497
16.1.2 Why Change Memory Map? .................................................................................. 499
16.1.3 How do Memory Map Registers Work?...................................................................... 499
16.1.4 RONLY Bit....................................................................................................... 499
16.1.5 Boot ROM Memory Initialization .............................................................................. 499
16.1.6 Erasing the Programming Flash.............................................................................. 500
16.1.7 Waiting for Flash Operations to Finish....................................................................... 500
16.1.8 Flash Interlock Register........................................................................................ 501
16.1.9 Clearing RDONLY Bit .......................................................................................... 501
16.1.10 Switching from User Mode to Supervisor Mode........................................................... 501
16.1.11 Erasing Data Flash............................................................................................ 501
16.1.12 Writing to Data Flash ......................................................................................... 501
16.1.13 Erasing Program Flash....................................................................................... 502
16.1.14 Writing to Program Flash..................................................................................... 502
16.2 Memory Management Controller (MMC) .............................................................................. 502
16.3 System Management (SYS)............................................................................................. 502
16.4 Central Interrupt Module (CIM).......................................................................................... 502
16.4.1 Interrupt Handling by CPU..................................................................................... 504
16.4.2 Interrupt Generation at Peripheral............................................................................ 504
16.4.3 CIM Interrupt Management (CIM) ............................................................................ 504
16.4.4 CIM Input Channel Management............................................................................. 505
16.4.5 CIM Prioritization................................................................................................ 506
16.4.6 CIM Operation................................................................................................... 506
16.4.7 Register Map.................................................................................................... 508
16.5 SYS – System Module Registers Reference.......................................................................... 508
16.5.1 Clock Control Register (CLKCNTL) .......................................................................... 508
16.5.2 System Exception Control Register (SYSECR) ............................................................ 510
16.5.3 System Exception Status Register (SYSESR).............................................................. 511
16.5.4 Abort Exception Status Register (ABRTESR) .............................................................. 513
16.5.5 Global Status Register (GLBSTAT) .......................................................................... 514
16.5.6 Device Identification Register (DEV)......................................................................... 515
16.5.7 System Software Interrupt Flag Register (SSIF) ........................................................... 516
16.5.8 System Software Interrupt Request Register (SSIR) ...................................................... 517
16.5.9 References ...................................................................................................... 517
17 Flash Memory Programming, Integrity, and Security............................................................. 518
17.1 Quick Start Summary..................................................................................................... 519
17.1.1 ROM Bootstrap and Program Flash Checksum ............................................................ 519
17.1.2 Firmware Development Setup ................................................................................ 519
17.1.3 Production Setup ............................................................................................... 519
17.2 Flash Memory Operations ............................................................................................... 519
17.2.1 UCD3138 Memory Maps ...................................................................................... 519
17.2.2 Flash Programming in ROM Mode........................................................................... 520
17.2.3 Clearing the Flash .............................................................................................. 520
17.2.4 3138 Family Members with Multiple Flash Blocks.......................................................... 520
17.3 Flash Management for Firmware Development ...................................................................... 521
17.3.1 Best Practice for Firmware Development.................................................................... 521
17.3.2 Firmware Development with "Backdoors" ................................................................... 521

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17.3.3 I/O Line Based Backdoors..................................................................................... 521
17.3.4 Communications Backdoors................................................................................... 522
17.4 Flash Management in Production....................................................................................... 522
17.5 Firmware Examples ...................................................................................................... 523
17.5.1 Checksum Clearing............................................................................................. 523
17.5.2 Erasing Flash.................................................................................................... 524
17.5.3 Serial Port Based Backdoor................................................................................... 524
17.5.4 I/O Line Based Back Door..................................................................................... 524
18 CIM – Central Interrupt Module Registers Reference............................................................. 525
18.1 IRQ Index Offset Vector Register (IRQIVEC)......................................................................... 526
18.2 FIQ Index Offset Vector Register (FIQIVEC) ......................................................................... 527
18.3 FIQ/IRQ Program Control Register (FIRQPR)........................................................................ 528
18.4 Pending Interrupt Read Location Register (INTREQ)................................................................ 529
18.5 Interrupt Mask Register (REQMASK).................................................................................. 530
Revision History........................................................................................................................ 531

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List of Figures
List of Figures
1-1. ................................................................................................................................ 31
2-1. Block Diagram of a DPWM Module...................................................................................... 35
2-2. Block Diagram of Timing Module in the DPWM module .............................................................. 36
2-3. DPWM Mode - Multi-mode, Open Loop................................................................................. 38
2-4. DPWM - Normal Mode .................................................................................................... 39
2-5. DPWM - Phase Shift Mode ............................................................................................... 41
2-6. DPWM – Multiple Output Mode (Multi Mode) .......................................................................... 42
2-7. DPWM – Resonant Mode................................................................................................. 44
2-8. DPWM – Triangular Mode ................................................................................................ 45
2-9. DPWM – Leading Edge Mode............................................................................................ 46
2-10. SyncFET IDE (Normal Mode)............................................................................................. 47
2-11. Resonant LLC implementation in UCD3138 with Automatic Mode Switching ..................................... 48
2-12. Mechanism for Automatic Mode Switching in UCD3138.............................................................. 49
2-13. UCD3138 Edge-Gen & Intra-Mux........................................................................................ 50
2-14. ................................................................................................................................ 55
2-15. Minimum Duty Mode 1..................................................................................................... 57
2-16. Minimum Duty Mode 2..................................................................................................... 57
2-17. DPWM Control Register 0 (DPWMCTRL0)............................................................................. 67
2-18. DPWM Control Register 1 (DPWMCTRL1)............................................................................. 70
2-19. DPWM Control Register 2 (DPWMCTRL2)............................................................................. 73
2-20. DPWM Period Register (DPWMPRD)................................................................................... 75
2-21. DPWM Event 1 Register (DPWMEV1) .................................................................................. 76
2-22. DPWM Event 2 Register (DPWMEV2) .................................................................................. 77
2-23. DPWM Event 3 Register (DPWMEV3) .................................................................................. 78
2-24. DPWM Event 4 Register (DPWMEV4) .................................................................................. 79
2-25. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)............................................................ 80
2-26. DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2)............................................................ 81
2-27. DPWM Phase Trigger Register (DPWMPHASETRIG)................................................................ 82
2-28. DPWM Cycle Adjust A Register (DPWMCYCADJA) .................................................................. 83
2-29. DPWM Cycle Adjust B Register (DPWMCYCADJB) .................................................................. 84
2-30. DPWM Resonant Duty Register (DPWMRESDUTY).................................................................. 85
2-31. DPWM Fault Control Register (DPWMFLTCTRL)..................................................................... 86
2-32. DPWM Overflow Register (DPWMOVERFLOW) ...................................................................... 87
2-33. DPWM Interrupt Register (DPWMINT).................................................................................. 88
2-34. DPWM Counter Preset Register (DPWMCNTPRE) ................................................................... 90
2-35. DPWM Blanking A Begin Register (DPWMBLKABEG) ............................................................... 91
2-36. DPWM Blanking A End Register (DPWMBLKAEND) ................................................................. 92
2-37. DPWM Blanking B Begin Register (DPWMBLKBBEG) ............................................................... 93
2-38. DPWM Blanking B End Register (DPWMBLKBEND) ................................................................. 94
2-39. DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI) .................................................. 95
2-40. DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO).................................................. 96
2-41. DPWM Adaptive Sample Register (DPWMADAPTIVE)............................................................... 97
2-42. DPWM Fault Status (DPWMFLTSTAT) ................................................................................. 98
2-43. DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH)............................. 99
2-44. DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH) ......................... 100
2-45. DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH) ........................... 101
2-46. DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH)......................... 102

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List of Figures
2-47. DPWM Auto Config Max Register (DPWMAUTOMAX).............................................................. 103
2-48. DPWM Auto Config Mid Register (DPWMAUTOMID) ............................................................... 105
2-49. DPWM Edge PWM Generation Control Register (DPWMEDGEGEN)............................................ 107
2-50. DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD) ................................................... 109
2-51. DPWM BIST Status Register (DPWMBISTSTAT).................................................................... 110
3-1. Simplified Block Diagram of Front End in UCD3138 (Front End 2 recommended for Peak Current Mode
Control)..................................................................................................................... 111
3-2. .............................................................................................................................. 114
3-3. Consecutive Mode of Averaging by EADC............................................................................ 116
3-4. Spatial Mode of Averaging by EADC .................................................................................. 116
3-5. .............................................................................................................................. 118
3-6. DAC Dither................................................................................................................. 118
3-7. .............................................................................................................................. 120
3-8. Ideal Diode Emulation (IDE) Module in UCD3138 ................................................................... 122
3-9. Ramp Control Register (RAMPCTRL) ................................................................................ 124
3-10. Ramp Status Register (RAMPSTAT) .................................................................................. 126
3-11. Ramp Cycle Register (RAMPCYCLE) ................................................................................. 127
3-12. EADC DAC Value Register (EADCDAC).............................................................................. 128
3-13. Ramp DAC Ending Value Register (RAMPDACEND)............................................................... 129
3-14. DAC Step Register (DACSTEP)........................................................................................ 130
3-15. DAC Saturation Step Register (DACSATSTEP)...................................................................... 131
3-16. EADC Trim Register (EADCTRIM)..................................................................................... 132
3-17. EADC Control Register (EADCCTRL) ................................................................................. 133
3-18. Analog Control Register (ACTRL)...................................................................................... 135
3-19. Pre-Bias Control Register 0 (PREBIASCTRL0) ...................................................................... 136
3-20. Pre-Bias Control Register 1 (PREBIASCTRL1) ...................................................................... 137
3-21. SAR Control Register (SARCTRL) ..................................................................................... 138
3-22. SAR Timing Register (SARTIMING) ................................................................................... 139
3-23. EADC Value Register (EADCVALUE) ................................................................................. 140
3-24. EADC Raw Value Register (EADCRAWVALUE)..................................................................... 141
3-25. DAC Status Register (DACSTAT)...................................................................................... 142
4-1. .............................................................................................................................. 144
4-2. .............................................................................................................................. 146
4-3. .............................................................................................................................. 147
4-4. .............................................................................................................................. 153
4-5. .............................................................................................................................. 154
4-6. Filter Status Register (FILTERSTATUS) .............................................................................. 156
4-7. Filter Control Register (FILTERCTRL)................................................................................. 158
4-8. CPU XN Register (CPUXN) ............................................................................................. 160
4-9. Filter XN Read Register (FILTERXNREAD) .......................................................................... 161
4-10. Filter KI_YN Read Register (FILTERKIYNREAD).................................................................... 162
4-11. Filter KD_YN Read Register (FILTERKDYNREAD) ................................................................. 163
4-12. Filter YN Read Register (FILTERYNREAD) .......................................................................... 164
4-13. Coefficient Configuration Register (COEFCONFIG) ................................................................. 165
4-14. Filter KP Coefficient 0 Register (FILTERKPCOEF0)................................................................. 168
4-15. Filter KP Coefficient 1 Register (FILTERKPCOEF1)................................................................. 169
4-16. Filter KI Coefficient 0 Register (FILTERKICOEF0) .................................................................. 170
4-17. Filter KI Coefficient 1 Register (FILTERKICOEF1)................................................................... 171
4-18. Filter KD Coefficient 0 Register (FILTERKDCOEF0) ................................................................ 172

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4-19. Filter KD Coefficient 1 Register (FILTERKDCOEF1) ................................................................ 173
4-20. Filter KD Alpha Register (FILTERKDALPHA)......................................................................... 174
4-21. Filter Nonlinear Limit Register 0 (FILTERNL0) ....................................................................... 175
4-22. Filter Nonlinear Limit Register 1 (FILTERNL1) ....................................................................... 176
4-23. Filter Nonlinear Limit Register 2 (FILTERNL2) ....................................................................... 177
4-24. Filter KI Feedback Clamp High Register (FILTERKICLPHI)........................................................ 178
4-25. Filter KI Feedback Clamp Low Register (FILTERKICLPLO)........................................................ 179
4-26. Filter YN Clamp High Register (FILTERYNCLPHI) .................................................................. 180
4-27. Filter YN Clamp Low Register (FILTERYNCLPLO).................................................................. 181
4-28. Filter Output Clamp High Register (FILTEROCLPHI)................................................................ 182
4-29. Filter Output Clamp Low Register (FILTEROCLPLO) ............................................................... 183
4-30. Filter Preset Register (FILTERPRESET) .............................................................................. 184
5-1. UCD3138 Flux Balancing Approach.................................................................................... 190
5-2. Front End Control 0 Mux Register (FECTRL0MUX) ................................................................. 191
5-3. Front End Control 1 Mux Register (FECTRL1MUX) ................................................................. 193
5-4. Front End Control 2 Mux Register (FECTRL2MUX) ................................................................. 195
5-5. Sample Trigger Control Register (SAMPTRIGCTRL)................................................................ 197
5-6. External DAC Control Register (EXTDACCTRL) .................................................................... 198
5-7. Filter Mux Register (FILTERMUX) ..................................................................................... 199
5-8. Filter KComp A Register (FILTERKCOMPA) ......................................................................... 201
5-9. Filter KComp B Register (FILTERKCOMPB) ......................................................................... 202
5-10. DPWM Mux Register (DPWMMUX) ................................................................................... 203
5-11. Constant Power Control Register (CPCTRL) ........................................................................ 205
5-12. Constant Power Nominal Threshold Register (CPNOM) ........................................................... 207
5-13. Constant Power Max Threshold Register (CPMAX) ................................................................ 208
5-14. Constant Power Configuration Register (CPCONFIG) .............................................................. 209
5-15. Constant Power Max Power Register (CPMAXPWR) ............................................................... 210
5-16. Constant Power Integrator Threshold Register (CPINTTHRESH) ................................................ 211
5-17. Constant Power Firmware Divisor Register (CPFWDIVISOR) ..................................................... 212
5-18. onstant Power Status Register (CPSTAT) ............................................................................ 213
5-19. Cycle Adjustment Control Register (CYCADJCTRL) ................................................................ 214
5-20. Cycle Adjustment Limit Register (CYCADJLIM) ..................................................................... 215
5-21. Cycle Adjustment Status Register (CYCADJSTAT) ................................................................. 216
5-22. Global Enable Register (GLBEN)....................................................................................... 217
5-23. PWM Global Period Register (PWMGLBPRD) ....................................................................... 218
5-24. Sync Control Register (SYNCCTRL)................................................................................... 219
5-25. Light Load Control Register (LLCTRL)................................................................................. 220
5-26. Light Load Enable Threshold Register (LLENTHRESH) ............................................................ 221
5-27. Light Load Disable Threshold Register (LLDISTHRESH)........................................................... 222
5-28. Peak Current Mode Control Register (PCMCTRL)................................................................... 223
5-29. Analog Peak Current Mode Control Register (APCMCTRL)........................................................ 224
5-30. Loop Mux Test Register (LOOPMUXTEST) (Test Use Only)....................................................... 225
6-1. UCD3138 Fault Handling System ...................................................................................... 226
6-2. UCD3138 Analog Comparator Control................................................................................. 228
6-3. UCD3138 DPWM Fault Action.......................................................................................... 231
6-4. .............................................................................................................................. 233
6-5. Analog Comparator Control 0 Register (ACOMPCTRL0) .......................................................... 235
6-6. Analog Comparator Control 1 Register (ACOMPCTRL1) .......................................................... 237
6-7. Analog Comparator Control 2 Register (ACOMPCTRL2) .......................................................... 239

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List of Figures
6-8. Analog Comparator Control 3 Register (ACOMPCTRL3) .......................................................... 241
6-9. External Fault Control Register (EXTFAULTCTRL) ................................................................. 242
6-10. Fault Mux Interrupt Status Register (FAULTMUXINTSTAT) ....................................................... 243
6-11. Fault Mux Raw Status Register (FAULTMUXRAWSTAT) .......................................................... 245
6-12. Comparator Ramp Control 0 Register (COMPRAMP0) ............................................................. 247
6-13. Digital Comparator Control 0 Register (DCOMPCTRL0)............................................................ 249
6-14. Digital Comparator Control 1 Register (DCOMPCTRL1)............................................................ 250
6-15. Digital Comparator Control 2 Register (DCOMPCTRL2)............................................................ 251
6-16. Digital Comparator Control 3 Register (DCOMPCTRL3)............................................................ 252
6-17. Digital Comparator Counter Status Register (DCOMPCNTSTAT)................................................. 253
6-18. DPWM 0 Current Limit Control Register (DPWM0CLIM)............................................................ 254
6-19. DPWM 0 Fault AB Detection Register (DPWM0FLTABDET)....................................................... 256
6-20. DPWM 0 Fault Detection Register (DPWM0FAULTDET)........................................................... 257
6-21. DPWM 1 Current Limit Control Register (DPWM1CLIM)............................................................ 260
6-22. DPWM 1 Fault AB Detection Register (DPWM1FLTABDET)....................................................... 262
6-23. DPWM 1 Fault Detection Register (DPWM1FAULTDET)........................................................... 264
6-24. DPWM 2 Current Limit Control Register (DPWM2CLIM)............................................................ 267
6-25. DPWM 2 Fault AB Detection Register (DPWM2FLTABDET)....................................................... 269
6-26. DPWM 2 Fault Detection Register (DPWM2FAULTDET)........................................................... 271
6-27. DPWM 3 Current Limit Control Register (DPWM3CLIM)............................................................ 274
6-28. DPWM 3 Fault AB Detection Register (DPWM3FLTABDET)....................................................... 276
6-29. DPWM 3 Fault Detection Register (DPWM3FAULTDET)........................................................... 278
6-30. HFO Fail Detect Register (HFOFAILDET)............................................................................. 281
6-31. LFO Fail Detect Register (LFOFAILDET) ............................................................................. 282
6-32. IDE Control Register (IDECTRL) ....................................................................................... 283
7-1. Fault IO Direction Register (FAULTDIR)............................................................................... 285
7-2. Fault Input Register (FAULTIN)......................................................................................... 286
7-3. Fault Output Register (FAULTOUT).................................................................................... 287
7-4. Fault Interrupt Enable Register (FAULTINTENA) .................................................................... 288
7-5. Fault Interrupt Polarity Register (FAULTINTPOL).................................................................... 289
7-6. Fault Interrupt Pending Register (FAULTINTPEND)................................................................. 290
7-7. External Interrupt Direction Register (EXTINTDIR) .................................................................. 291
7-8. External Interrupt Input Register (EXTINTIN)......................................................................... 292
7-9. External Interrupt Output Register (EXTINTOUT).................................................................... 293
7-10. External Interrupt Enable Register (EXTINTENA).................................................................... 294
7-11. External Interrupt Polarity Register (EXTTINTPOL).................................................................. 295
7-12. External Interrupt Pending Register (EXTINTPEND) ................................................................ 296
8-1. ADC12 Control Block Diagram.......................................................................................... 297
8-2. ADC12 Input Impedance Model ........................................................................................ 299
8-3. ADC Input Impedance Model Containing External Circuits ......................................................... 299
8-4. Impedance Test Setup................................................................................................... 300
8-5. ADC12 Channel Impedance............................................................................................. 300
8-6. S/H Capacitor Charge vs. Settling Time............................................................................... 301
8-7. External Capacitance Makes Lower Source Impedance ............................................................ 301
8-8. Channel to Channel Crosstalk .......................................................................................... 301
8-9. ADC Control Register (ADCCTRL) .................................................................................... 302
8-10. UCS3138 Digital Comparators Control Block Diagram.............................................................. 304
8-11. Temp Sensor Control Register (TEMPSENCTRL)................................................................... 306
8-12. PMBus Control Register 3 (PMBCTRL3).............................................................................. 307

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List of Figures
8-13. PMBus Addressing ....................................................................................................... 308
8-14. ADC Control Register (ADCCTRL)..................................................................................... 309
8-15. Dual Sample and Hold Circuitry in ADC12............................................................................ 310
8-16. ADC12 Dual Sample and Hold Configuration......................................................................... 310
8-17. .............................................................................................................................. 313
8-18. .............................................................................................................................. 315
8-19. ADC Control Register (ADCCTRL) .................................................................................... 316
8-20. ADC Status Register (ADCSTAT) ..................................................................................... 318
8-21. ADC Test Control Register (ADCTSTCTRL).......................................................................... 319
8-22. ADC Sequence Select Register 0 (ADCSEQSEL0).................................................................. 320
8-23. ADC Sequence Select Register 1 (ADCSEQSEL1).................................................................. 321
8-24. ADC Sequence Select Register 2 (ADCSEQSEL2).................................................................. 322
8-25. ADC Sequence Select Register 3 (ADCSEQSEL3).................................................................. 323
8-26. ADC Result Registers 0-15 (ADCRESULTx, x=0:15)................................................................ 324
8-27. ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15) ............................................... 325
8-28. ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5) .............................................. 326
8-29. ADC Digital Compare Enable Register (ADCCOMPEN) ............................................................ 327
8-30. ADC Digital Compare Results Register (ADCCOMPRESULT)..................................................... 329
8-31. ADC Averaging Control Register (ADCAVGCTRL) .................................................................. 331
9-1. .............................................................................................................................. 334
9-2. .............................................................................................................................. 335
9-3. .............................................................................................................................. 336
9-4. Package ID Register (PKGID) .......................................................................................... 336
9-5. Brownout Register (BROWNOUT) ..................................................................................... 337
9-6. Temp Sensor Control Register (TEMPSENCTRL)................................................................... 338
9-7. I/O Mux Control Register (IOMUX)..................................................................................... 339
9-8. Current Sharing Control Register (CSCTRL) ......................................................................... 340
9-9. Temperature Reference Register (TEMPREF) ....................................................................... 341
9-10. Power Disable Control Register (PWRDISCTRL).................................................................... 342
9-11. Global I/O EN Register (GBIOEN)...................................................................................... 346
9-12. Global I/O OE Register (GLBIOOE).................................................................................... 347
9-13. Global I/O Open Drain Control Register (GLBIOOD) ................................................................ 348
9-14. Global I/O Value Register (GLBIOVAL)................................................................................ 349
9-15. Global I/O Read Register (GLBIOREAD).............................................................................. 350
9-16. Clock Trim Register (CLKTRIM) (For Factory Test Use Only, Except HFO_LN_FILTER_EN) ................ 351
10-1. .............................................................................................................................. 356
10-2. Command with PEC...................................................................................................... 357
10-3. Write Command and Byte - No PEC................................................................................... 357
10-4. Write Command and Byte - with PEC.................................................................................. 358
10-5. Write 2 Bytes with no PEC .............................................................................................. 358
10-6. Timing Diagram ........................................................................................................... 359
10-7. Write 4 Bytes + Command .............................................................................................. 359
10-8. Slave Address Manual ACK for Write.................................................................................. 360
10-9. Manual ACK Command.................................................................................................. 361
10-10. Simple Read with Full Automation...................................................................................... 362
10-11. Simple Read of 4 Bytes with Full Automation......................................................................... 363
10-12. Simple Read of 5 Bytes with Full Automation......................................................................... 363
10-13. Slave Address Manual ACK on a Read Address..................................................................... 364
10-14. Write/Read with Repeated Start ........................................................................................ 365

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List of Figures
10-15. Clock Stretch Timing for Read.......................................................................................... 367
10-16. Alert Response............................................................................................................ 368
10-17. Address Byte Timing ..................................................................................................... 369
10-18. Repeated Start Timing ................................................................................................... 369
10-19. Read Byte Timing......................................................................................................... 370
10-20. Write Byte Timing......................................................................................................... 370
10-21. Write Byte Stop Timing................................................................................................... 370
10-22. Quick Command Format................................................................................................. 373
10-23. Send Byte w/o PEC Byte ................................................................................................ 373
10-24. Send Byte with PEC Byte................................................................................................ 373
10-25. Receive Byte w/o PEC Byte............................................................................................. 373
10-26. Receive Byte with PEC Byte ............................................................................................ 373
10-27. Write Byte w/o PEC Byte ................................................................................................ 374
10-28. Write Byte with PEC Byte................................................................................................ 374
10-29. Write Word w/o PEC Byte ............................................................................................... 374
10-30. Write Word with PEC Byte............................................................................................... 374
10-31. Read Byte w/o PEC Byte................................................................................................ 375
10-32. Read Byte with PEC Byte ............................................................................................... 375
10-33. Read Word w/o PEC Byte............................................................................................... 375
10-34. Read Word with PEC Byte .............................................................................................. 375
10-35. Process Call w/o PEC Byte ............................................................................................. 376
10-36. Process Call with PEC Byte............................................................................................. 376
10-37. Block Write w/o PEC Byte............................................................................................... 377
10-38. Block Write with PEC Byte .............................................................................................. 377
10-39. Block Read w/o PEC Byte............................................................................................... 378
10-40. Block Read with PEC Byte .............................................................................................. 378
10-41. Block Write-Block Read Process Call w/o PEC Byte ................................................................ 379
10-42. Block Write-Block Read Process Call with PEC Byte................................................................ 379
10-43. Alert Response............................................................................................................ 379
10-44. Extended Command Write Byte w/o PEC Byte....................................................................... 380
10-45. Extended Command Write Byte with PEC Byte ...................................................................... 380
10-46. Extended Command Write Word w/o PEC Byte...................................................................... 380
10-47. Extended Command Write Word with PEC Byte ..................................................................... 380
10-48. Extended Command Read Byte w/o PEC Byte....................................................................... 380
10-49. Extended Command Read Byte with PEC Byte...................................................................... 380
10-50. Extended Command Read Word w/o PEC Byte...................................................................... 380
10-51. Extended Command Read Word with PEC Byte..................................................................... 380
10-52. .............................................................................................................................. 381
10-53. PMBUS Control Register 1 (PMBCTRL1)............................................................................. 382
10-54. PMBus Transmit Data Buffer (PMBTXBUF) .......................................................................... 384
10-55. PMBus Receive Data Register (PMBRXBUF)........................................................................ 385
10-56. PMBus Acknowledge Register (PMBACK)............................................................................ 386
10-57. PMBus Status Register (PMBST) ...................................................................................... 387
10-58. PMBus Interrupt Mask Register (PMBINTM).......................................................................... 389
10-59. PMBus Control Register 2 (PMBCTRL2).............................................................................. 390
10-60. PMBus Hold Slave Address Register (PMBHSA) .................................................................... 392
10-61. PMBus Control Register 3 (PMBCTRL3).............................................................................. 393
11-1. .............................................................................................................................. 397
11-2. .............................................................................................................................. 400