Texas Instruments ADS868 A Series User manual

-0.05
-0.03
-0.01
0.01
0.03
0.05
±40 ±7 26 59 92 125
Gain (% FS)
Free-Air Temperature (oC) C039
---- ± 2.5*VREF, ---- 1.25*VREF
---- 0.625*VREF, ------0.3125*VREF
-------0.156 VREF, ---- + 2.5*VREF
---- + 1.25*VREF, ---- + 0.625*VREF
---- + 0.3125*VREF
Multiplexer
Oscillator
CS
SCLK
SDI
SDO
DAISY
REFSEL
RST / PD
REFCAP
REFIO
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB0
AIN_0P
AIN_0GND OVP
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB1
AIN_1P
AIN_1GND OVP
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB2
AIN_2P
AIN_2GND OVP
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB3
AIN_3P
AIN_3GND OVP
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB4
AIN_4P
AIN_4GND OVP
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB5
AIN_5P
AIN_5GND OVP
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB6
AIN_6P
AIN_6GND OVP
PGA
1 M:
OVP
1 M:
2nd-Order
LPF ADC
Driver
VB7
AIN_7P
AIN_7GND OVP
AUX_IN
AUX_GND
16-Bit
SAR ADC
Digital
Logic
and
Interface
4.096-V
Reference
REFGND
DGNDAGND
DVDD
AVDD
Additional Channels in ADS8688A
ADS8688A
ADS8684A
ALARM
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
Reference
Design
ADS8684A , ADS8688A
SBAS680 –JULY 2015
ADS868xA 16-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with
Bipolar Input Ranges
1 Features 2 Applications
1• 16-Bit ADCs with Integrated Analog Front-End • Power Automation
• 4-, 8-Channel MUX with Auto and Manual Scan • Protection Relays
• Channel-Independent Programmable Inputs: • PLC Analog Input Modules
– ±10.24 V, ±5.12 V, ±2.56 V, ±1.28 V, ±0.64 V 3 Description
– 10.24 V, 5.12 V, 2.56 V, 1.28 V The ADS8684A and ADS8688A are 4- and 8-
• 5-V Analog Supply: 1.65-V to 5-V I/O Supply channel, integrated data acquisition systems based
• Constant Resistive Input Impedance: 1 MΩon a 16-bit successive approximation (SAR) analog-
to-digital converter (ADC), operating at a throughput
• Input Overvoltage Protection: Up to ±20 V of 500 kSPS. The devices feature integrated analog
• On-Chip, 4.096-V Reference with Low Drift front-end circuitry for each input channel with
• Excellent Performance: overvoltage protection up to ±20 V, a 4- or 8-channel
multiplexer with automatic and manual scanning
– 500-kSPS Aggregate Throughput modes, and an on-chip, 4.096-V reference with low
– DNL: ±0.5 LSB; INL: ±0.75 LSB temperature drift. Operating on a single 5-V analog
– Low Drift for Gain Error and Offset supply, each input channel on the devices can
– SNR: 92 dB; THD: –102 dB support true bipolar input ranges of ±10.24 V,
±5.12 V, ±2.56 V, ±1.28V and ±0.64V, as well as
– Low Power: 65 mW unipolar input ranges of 0 V to 10.24 V, 0 V to 5.12 V,
• AUX Input →Direct Connection to ADC Inputs 0 V to 2.56 V and 0 V to 1.28 V. The gain of the
• ALARM →High and Low Thresholds per Channel analog front-end for all input ranges is accurately
trimmed to ensure a high dc precision. The input
• SPI™-Compatible Interface with Daisy-Chain range selection is software-programmable and
• Industrial Temperature Range: –40°C to 125°C independent for each channel. The devices offer a
• TSSOP-38 Package (9.7 mm × 4.4 mm) 1-MΩconstant resistive input impedance irrespective
of the selected input range.
Block Diagram The ADS8684A and ADS8688A offer a simple SPI-
compatible serial interface to the digital host and also
support daisy-chaining of multiple devices. The digital
supply operates from 1.65 V to 5.25 V, enabling
direct interface to a wide range of host controllers.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
ADS868xA TSSOP (38) 9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Gain Error versus Temperature
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

ADS8684A , ADS8688A
SBAS680 –JULY 2015 www.ti.com
Table of Contents
8.4 Device Functional Modes........................................ 37
1 Features.................................................................. 18.5 Register Maps......................................................... 50
2 Applications ........................................................... 19 Application and Implementation ........................ 66
3 Description............................................................. 19.1 Application Information............................................ 66
4 Revision History..................................................... 29.2 Typical Applications ................................................ 66
5 Device Comparison Table..................................... 310 Power-Supply Recommendations..................... 69
6 Pin Configuration and Functions......................... 311 Layout................................................................... 70
7 Specifications......................................................... 511.1 Layout Guidelines ................................................. 70
7.1 Absolute Maximum Ratings ...................................... 511.2 Layout Example .................................................... 71
7.2 ESD Ratings.............................................................. 512 Device and Documentation Support................. 72
7.3 Recommended Operating Conditions....................... 512.1 Documentation Support ........................................ 72
7.4 Thermal Information.................................................. 512.2 Related Links ........................................................ 72
7.5 Electrical Characteristics........................................... 612.3 Community Resources.......................................... 72
7.6 Timing Requirements: Serial Interface.................... 11 12.4 Trademarks........................................................... 72
7.7 Typical Characteristics............................................ 12 12.5 Electrostatic Discharge Caution............................ 72
8 Detailed Description............................................ 23 12.6 Glossary................................................................ 72
8.1 Overview................................................................. 23 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram....................................... 23 Information ........................................................... 73
8.3 Feature Description................................................. 24
4 Revision History
DATE REVISION NOTES
July 2014 * Initial release.
2Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ADS8684A ADS8688A

1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
CS
SCLK
SDO
ALARM
DVDD
DGND
AGND
AGND
SDI
RST/PD
DAISY
REFSEL
REFIO
REFGND
REFCAP
22
21
20
AVDD
AGND
AGND
AIN_5P
AIN_5GND
AIN_4P
AIN_4GND
9AVDD
AUX_IN
AUX_GND
AIN_6P
AIN_6GND
AIN_7P
AIN_7GND
10
11
12
13
14
15
23 AIN_3P
AIN_3GND
AIN_2P
AIN2_GND
AIN_0P
AIN_0GND
AIN_1P
AIN_1GND
16
17
18
19
31
32
33
34
35
36
37
38
AGND
ADS8688A
1
2
3
4
5
6
7
8
30
29
28
27
26
25
24
CS
SCLK
SDO
ALARM
DVDD
DGND
AGND
AGND
SDI
RST/PD
DAISY
REFSEL
REFIO
REFGND
REFCAP
22
21
20
AVDD
AGND
AGND
NC
NC
NC
NC
9AVDD
AUX_IN
AUX_GND
NC
NC
NC
NC
10
11
12
13
14
15
23 AIN_3P
AIN_3GND
AIN_2P
AIN2_GND
AIN_0P
AIN_0GND
AIN_1P
AIN_1GND
16
17
18
19
31
32
33
34
35
36
37
38
AGND
ADS8684A
ADS8684A , ADS8688A
www.ti.com SBAS680 –JULY 2015
5 Device Comparison Table
PRODUCT RESOLUTION (Bits) CHANNELS SAMPLE RATE (kSPS)
ADS8684A 16 4, single-ended 500
ADS8688A 16 8, single-ended 500
6 Pin Configuration and Functions
DBT Package
38-Pin TSSOP
Top View (Not to Scale)
Pin Functions
PIN
NAME I/O DESCRIPTION
NO. ADS8684A ADS8688A
1 SDI Digital input Data input for serial communication.
Active low logic input.
2 RST/PD Digital input Dual functionality to reset or power-down the device.
3 DAISY Digital input Chain the data input during serial communication in daisy-chain mode.
Active low logic input to enable the internal reference.
When low, the internal reference is enabled;
4 REFSEL Digital input REFIO becomes an output that includes the VREF voltage.
When high, the internal reference is disabled;
REFIO becomes an input to apply the external VREF voltage.
5 REFIO Analog input, output Internal reference output and external reference input pin. Decouple with REFGND on pin 6.
Reference GND pin; short to the analog GND plane.
6 REFGND Power supply Decouple with REFIO on pin 5 and REFCAP on pin 7.
7 REFCAP Analog output ADC reference decoupling capacitor pin. Decouple with REFGND on pin 6.
8 AGND Power supply Analog ground pin. Decouple with AVDD on pin 9.
9 AVDD Power supply Analog supply pin. Decouple with AGND on pin 8.
10 AUX_IN Analog input Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11.
11 AUX_GND Analog input Auxiliary input channel: negative input. Decouple with AUX_IN on pin 10.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: ADS8684A ADS8688A

ADS8684A , ADS8688A
SBAS680 –JULY 2015 www.ti.com
Pin Functions (continued)
PIN
NAME I/O DESCRIPTION
NO. ADS8684A ADS8688A
Analog input channel 6, positive input. Decouple with AIN_6GND on pin 13.
12 NC AIN_6P Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
Analog input channel 6, negative input. Decouple with AIN_6P on pin 12.
13 NC AIN_6GND Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
Analog input channel 7, positive input. Decouple with AIN_7GND on pin 15.
14 NC AIN_7P Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
Analog input channel 7, negative input. Decouple with AIN_7P on pin 14.
15 NC AIN_7GND Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
16 AIN_0P Analog input Analog input channel 0, positive input. Decouple with AIN_0GND on pin 17.
17 AIN_0GND Analog input Analog input channel 0, negative input. Decouple with AIN_0P on pin 16.
18 AIN_1P Analog input Analog input channel 1, positive input. Decouple with AIN_1GND on pin 19.
19 AIN_1GND Analog input Analog input channel 1, negative input. Decouple with AIN_1P on pin 18.
20 AIN2_GND Analog input Analog input channel 2, negative input. Decouple with AIN_2P on pin 21.
21 AIN_2P Analog input Analog input channel 2, positive input. Decouple with AIN_2GND on pin 20.
22 AIN_3GND Analog input Analog input channel 3, negative input. Decouple with AIN_3P on pin 23.
23 AIN_3P Analog input Analog input channel 3, positive input. Decouple with AIN_3GND on pin 22.
Analog input channel 4, negative input. Decouple with AIN_4P on pin 25.
24 NC AIN_4GND Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
Analog input channel 4, positive input. Decouple with AIN_4GND on pin 24.
25 NC AIN_4P Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
Analog input channel 5, negative input. Decouple with AIN_5P on pin 27.
26 NC AIN_5GND Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
Analog input channel 5, positive input. Decouple with AIN_5GND on pin 26.
27 NC AIN_5P Analog input No connection for the ADS8684A; this pin can be left floating or connected to AGND.
28 AGND Power supply Analog ground pin
29 AGND Power supply Analog ground pin
30 AVDD Power supply Analog supply pin. Decouple with AGND on pin 31.
31 AGND Power supply Analog ground pin. Decouple with AVDD on pin 30.
32 AGND Power supply Analog ground pin
33 DGND Power supply Digital ground pin. Decouple with DVDD on pin 34.
34 DVDD Power supply Digital supply pin. Decouple with DGND on pin 33.
35 ALARM Digital output Active high alarm output
36 SDO Digital output Data output for serial communication
37 SCLK Digital input Clock input for serial communication
38 CS Digital input Active low logic input; chip-select signal
4Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ADS8684A ADS8688A

ADS8684A , ADS8688A
www.ti.com SBAS680 –JULY 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
AIN_nP, AIN_nGND to GND(2) –20 20 V
AIN_nP, AIN_nGND to GND(3) –11 11 V
AUX_GND to GND –0.3 0.3 V
AUX_IN to GND –0.3 AVDD + 0.3 V
AVDD to GND or DVDD to GND –0.3 7 V
REFCAP to REFGND or REFIO to REFGND –0.3 5.7 V
GND to REFGND –0.3 0.3 V
Digital input pins to GND –0.3 DVDD + 0.3 V
Digital output pins to GND –0.3 DVDD + 0.3 V
Operating temperature, TA–40 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AVDD = 5 V or offers a low impedance of < 30 kΩ.
(3) AVDD = floating with an impedance > 30 kΩ.
7.2 ESD Ratings VALUE UNIT
Analog input pins ±4000
(AIN_nP; AIN_nGND)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
V(ESD) V
discharge All other pins ±2000
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
AVDD Analog supply voltage 4.75 5 5.25 V
DVDD Digital supply voltage 1.65 3.3 AVDD V
7.4 Thermal Information ADS8684A,
ADS8688A
THERMAL METRIC(1) UNIT
DBT (TSSOP)
38 PINS
RθJA Junction-to-ambient thermal resistance 68.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.9 °C/W
RθJB Junction-to-board thermal resistance 30.4 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 29.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance NA °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: ADS8684A ADS8688A

ADS8684A , ADS8688A
SBAS680 –JULY 2015 www.ti.com
7.5 Electrical Characteristics
Minimum and maximum specifications are at TA= –40°C to 125°C. Typical specifications are at TA= 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted. TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1)
ANALOG INPUTS
Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF A
–0.3125 ×
Input range = ±0.3125 × VREF 0.3125 × VREF A
VREF
Full-scale input span(2) –0.15625 × 0.15625 × V
(AIN_nP to AIN_nGND) Input range = ±0.15625 × VREF A
VREF VREF
Input range = 2.5 × VREF 0 2.5 × VREF A
Input range = 1.25 × VREF 0 1.25 × VREF A
Input range = 0.625 × VREF 0 0.625 × VREF A
Input range = 0.3125 × VREF 0 0.3125 × VREF A
Input range = ±2.5 × VREF –2.5 × VREF 2.5 × VREF A
Input range = ±1.25 × VREF –1.25 × VREF 1.25 × VREF A
Input range = ±0.625 × VREF –0.625 × VREF 0.625 × VREF A
–0.3125 ×
Input range = ±0.3125 × VREF 0.3125 × VREF A
VREF
Operating input range,
AIN_nP –0.15625 × 0.15625 × V
positive input Input range = ±0.15625 × VREF A
VREF VREF
Input range = 2.5 × VREF 0 2.5 × VREF A
Input range = 1.25 × VREF 0 1.25 × VREF A
Input range = 0.625 × VREF 0 0.625 × VREF A
Input range = 0.3125 × VREF 0 0.3125 × VREF A
Operating input range,
AIN_nGND All input ranges –0.1 0 0.1 V B
negative input
At TA= 25°C,
ziInput impedance 0.85 1 1.15 MΩB
all input ranges
Input impedance drift All input ranges 7 25 ppm/°C B
VIN – 2.25
With voltage at AIN_nP pin = VIN,———— A
input range = ±2.5 × VREF RIN
VIN – 2.00
With voltage at AIN_nP pin = VIN,———— A
input range = ±1.25 × VREF RIN
With voltage at AIN_nP pin = VIN, VIN – 1.60
IIkg(in) Input leakage current input ranges = ±0.625 × VREF; ———— µA A
±0.3125 × VREF; ±0.15625 × VREF RIN
VIN – 2.50
With voltage at AIN_nP pin = VIN,———— A
input range = 2.5 × VREF RIN
With voltage at AIN_nP pin = VIN, VIN – 2.50
input range = 1.25 × VREF; 0.625 × ———— A
VREF; 0.3125 × VREF RIN
INPUT OVERVOLTAGE PROTECTION
AVDD = 5 V or offers low –20 20 B
impedance < 30 kΩ, all input ranges
VOVP Overvoltage protection voltage V
AVDD = floating with impedance –11 11 B
> 30 kΩ, all input ranges
(1) Test Levels: (A) Tested at final test. Over temperature limits are set by characterization and simulation. (B) Limits set by characterization
and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.
(2) Ideal input span, does not include gain or offset error.
6Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ADS8684A ADS8688A

ADS8684A , ADS8688A
www.ti.com SBAS680 –JULY 2015
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 125°C. Typical specifications are at TA= 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted. TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1)
SYSTEM PERFORMANCE
Resolution 16 Bits A
NMC No missing codes 16 Bits A
DNL Differential nonlinearity –0.99 ±0.5 1.5 LSB(3) A
INL Integral nonlinearity(4) –2 ±0.75 2 LSB A
EGGain error At TA= 25°C, all input ranges ±0.02 ±0.05 %FSR(5) A
Gain error matching At TA= 25°C, all input ranges ±0.02 ±0.05 %FSR A
(channel-to-channel)
Gain error temperature drift All input ranges 1 4 ppm/°C B
At TA= 25°C, ±0.5 ±1 A
input range = ±2.5 × VREF(6)
At TA= 25°C, ±0.5 ±1 A
input range = ±1.25 × VREF
At TA= 25°C, ±0.5 ±1.5 A
input range = ±0.625 × VREF
EOOffset error mV
At TA= 25°C, ±0.5 ±1.5 A
input range = ±0.3125 × VREF
At TA= 25°C, ±0.5 ±1.5 A
input range = ±0.15625 × VREF
At TA= 25°C, ±0.5 ±2 A
all unipolar input ranges
At TA= 25°C, ±0.5 ±1 A
input range = ±2.5 × VREF(6)
At TA= 25°C, ±0.5 ±1 A
input range = ±1.25 × VREF
At TA= 25°C, ±0.5 ±1.5 A
input range = ±0.625 × VREF
Offset error matching mV
(channel-to-channel) At TA= 25°C, ±0.5 ±1.5 A
input range = ±0.3125 × VREF
At TA= 25°C, ±0.5 ±1.5 A
input range = ±0.15625 × VREF
At TA= 25°C, ±0.5 ±2 A
all unipolar input ranges
Input range = ±2.5 × VREF 1 3 B
Input range = ±1.25 × VREF 1 3 B
Input range = ±0.625 × VREF 1 3 B
Input range = ±0.3125 × VREF 2 6 B
Offset error temperature drift Input range = ±0.15625 × VREF 4 12 ppm/°C B
Input range = 0 to 2.5 × VREF 1 3 B
Input range = 0 to 1.25 × VREF 1 3 B
Input range = 0 to 0.625 × VREF 2 6 B
Input range = 0 to 0.3125 × VREF 4 12 B
SAMPLING DYNAMICS
tCONV Conversion time 850 ns A
tACQ Acquisition time 1150 ns A
Maximum throughput rate
fS500 kSPS A
without latency
(3) LSB = least significant bit.
(4) This parameter is the endpoint INL, not best-fit INL.
(5) FSR = full-scale range.
(6) Does not include the shift in offset over time.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: ADS8684A ADS8688A

ADS8684A , ADS8688A
SBAS680 –JULY 2015 www.ti.com
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 125°C. Typical specifications are at TA= 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted. TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1)
DYNAMIC CHARACTERISTICS
Input range = ±2.5 × VREF 90 92 A
Input range = ±1.25 × VREF 89 91 A
Input range = ±0.625 × VREF 87.5 89 A
Input range = ±0.3125 × VREF 81.5 83 A
Signal-to-noise ratio
SNR Input range = ±0.15625 × VREF 75.5 77 dB A
(VIN – 0.5 dBFS at 1 kHz) Input range = 2.5 × VREF 88.5 90.5 A
Input range = 1.25 × VREF 87.5 89 A
Input range = 0.625 × VREF 81.5 83 A
Input range = 0.3125 × VREF 75.5 77 A
Input ranges = ±2.5 × VREF, ±1.25 ×
VREF, ±0.625 × VREF, 2.5 × VREF, -102
1.25 × VREF
Total harmonic distortion(7)
THD dB B
(VIN – 0.5 dBFS at 1 kHz) Input ranges = ±0.3125 × VREF,
±0.15625 × VREF, 0.625 × VREF, -100
0.3125 × VREF
Input range = ±2.5 × VREF 89 91.5 A
Input range = ±1.25 × VREF 88.5 91 A
Input range = ±0.625 × VREF 87 89 A
Input range = ±0.3125 × VREF 81 83 A
Signal-to-noise ratio
SINAD Input range = ±0.15625 × VREF 75 77 dB A
(VIN – 0.5 dBFS at 1 kHz) Input range = 2.5 × VREF 87.5 90.5 A
Input range = 1.25 × VREF 87 89 A
Input range = 0.625 × VREF 81 83 A
Input range = 0.3125 × VREF 75 77 A
Input ranges = ±2.5 × VREF, ±1.25 ×
VREF, ±0.625 × VREF, 2.5 × VREF, 103
1.25 × VREF
Spurious-free dynamic range
SFDR dB B
(VIN – 0.5 dBFS at 1 kHz) Input ranges = ±0.3125 × VREF,
±0.15625 × VREF, 0.625 × VREF, 101
0.3125 × VREF
Aggressor channel input overdriven
Crosstalk isolation(8) 110 dB B
to 2 × maximum input voltage
Aggressor channel input overdriven
Crosstalk memory(9) 90 dB B
to 2 × maximum input voltage
BW(–3 dB) Small-signal bandwidth, –3 dB At TA= 25°C, all input ranges 15 kHz B
BW(–0.1 dB) Small-signal bandwidth, –0.1 dB At TA= 25°C, all input ranges 2.5 kHz B
(7) Calculated on the first nine harmonics of the input frequency.
(8) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing
sequence, and measuring its effect on the output of any selected channel.
(9) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel that is selected in the multiplexing
sequence, and measuring its effect on the output of the next selected channel for all combinations of input channels.
8Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ADS8684A ADS8688A

ADS8684A , ADS8688A
www.ti.com SBAS680 –JULY 2015
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 125°C. Typical specifications are at TA= 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted. TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1)
AUXILIARY CHANNEL
Resolution 16 Bits A
V(AUX_IN) AUX_IN voltage range (AUX_IN – AUX_GND) 0 VREF V A
AUX_IN 0 VREF V A
Operating input range AUX_GND 0 V A
During sampling 75 pF C
CiInput capacitance During conversion 5 pF C
IIkg(in) Input leakage current 100 nA A
DNL Differential nonlinearity –0.99 ±0.6 1.5 LSB A
INL Integral nonlinearity –4 ±1.5 4 LSB A
EG(AUX) Gain error At TA= 25°C ±0.02 ±0.2 %FSR A
EO(AUX) Offset error At TA= 25°C –5 5 mV A
SNR Signal-to-noise ratio V(AUX_IN) = –0.5 dBFS at 1 kHz 87 89 dB A
THD Total harmonic distortion(7) V(AUX_IN) = –0.5 dBFS at 1 kHz –102 dB B
SINAD Signal-to-noise + distortion V(AUX_IN) = –0.5 dBFS at 1 kHz 86 88.5 dB A
SFDR Spurious-free dynamic range V(AUX_IN) = –0.5 dBFS at 1 kHz 103 dB B
INTERNAL REFERENCE OUTPUT
Voltage on REFIO pin
V(REFIO_INT)(10) At TA= 25°C 4.095 4.096 4.097 V A
(configured as output)
Internal reference temperature 6 10 ppm/°C B
drift
C(OUT_REFIO) Decoupling capacitor on REFIO 10 22 µF B
Reference voltage to ADC
V(REFCAP) At TA= 25°C 4.095 4.096 4.097 V A
(on REFCAP pin)
Reference buffer output 0.5 1 ΩB
impedance
Reference buffer temperature 0.6 1.5 ppm/°C B
drift
Decoupling capacitor on
C(OUT_REFCAP) 10 22 μF B
REFCAP
C(OUT_REFCAP) = 22 µF,
Turn-on time 15 ms B
C(OUT_REFIO) = 22 µF
EXTERNAL REFERENCE INPUT
External reference voltage on
VREFIO_EXT 4.046 4.096 4.146 V C
REFIO (configured as input)
(10) Does not include the variation in voltage resulting from solder-shift and long-term effects.
Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Links: ADS8684A ADS8688A

ADS8684A , ADS8688A
SBAS680 –JULY 2015 www.ti.com
Electrical Characteristics (continued)
Minimum and maximum specifications are at TA= –40°C to 125°C. Typical specifications are at TA= 25°C.
AVDD = 5 V, DVDD = 3 V, VREF = 4.096 V (internal), and fSAMPLE = 500 kSPS, unless otherwise noted. TEST
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1)
POWER-SUPPLY REQUIREMENTS
AVDD Analog power-supply voltage Analog supply 4.75 5 5.25 V B
Digital supply range 1.65 3.3 AVDD B
DVDD Digital power-supply voltage V
Digital supply range for specified 2.7 3.3 5.25 B
performance
For the ADS8688; AVDD = 5 V, fS=13 16 A
maximum and internal reference
Dynamic,
IAVDD_DYN mA
AVDD For the ADS8684; AVDD = 5 V, fS=8.5 11.5 A
maximum and internal reference
For the ADS8688; AVDD = 5 V,
device not converting and internal 10 12 A
reference
IAVDD_STC Analog supply current Static mA
For the ADS8684; AVDD = 5 V,
device not converting and internal 5.5 8.5 A
reference
At AVDD = 5 V, device in STDBY
ISTDBY Standby 3 4.5 mA A
mode and internal reference
Power-
IPWR_DN At AVDD = 5 V, device in PWR_DN 3 20 μA B
down
IDVDD_DYN Digital supply current At DVDD = 3.3 V, output = 0000h 0.5 mA A
DIGITAL INPUTS (CMOS)
VIH 0.7 × DVDD DVDD + 0.3 A
Digital input logic levels V
DVDD > 2.1 V
VIL –0.3 0.3 × DVDD A
VIH 0.8 × DVDD DVDD + 0.3 A
Digital input logic levels V
DVDD ≤2.1 V
VIL –0.3 0.2 × DVDD A
Input leakage current 100 nA A
Input pin capacitance 5 pF C
DIGITAL OUTPUTS (CMOS)
VOH IO= 500-μA source 0.8 × DVDD DVDD A
Digital output logic levels V
VOL IO= 500-μA sink 0 0.2 × DVDD A
Floating state leakage current Only for SDO 1 µA A
Internal pin capacitance 5 pF C
TEMPERATURE RANGE
TAOperating free-air temperature –40 125 °C B
10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: ADS8684A ADS8688A