Texas Tms320x281 series User manual

TMS320x281x DSP

Multichannel Buffered Serial Port (McBSP)

Reference Guide

Literature Number: SPRU061B

May 2003 − Revised November 2004

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iii

Read This First

Preface



About This Manual

This guide describes how Multichannel Buffered Serial Port (McBSP) works in the TMS320x281x de-

vices.

Related Documentation From Texas Instruments

The following books describe the TMS320x281x and related support tools that

are available on the TI website.

TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810,

TMS320C2811, and TMS320C2812 Digital Signal Processors

(literature number SPRS174) data sheet contains the electrical and

timing specifications for these devices, as well as signal descriptions and

pinouts for all of the available packages.

TMS320R2811 and TMS320R2812 Digital Signal Processors (literature

number SPRS257) data sheet contains the electrical and timing

specifications for these devices, as well as signal descriptions and

pinouts for all of the available packages.

TMS320C28x DSP CPU and Instruction Set Reference Guide (literature

number SPRU430) describes the central processing unit (CPU) and the

assembly language instructions of the TMS320C28xfixed-point digital

signal processors (DSPs). It also describes emulation features available

on these DSPs.

TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide (liter-

ature number SPRU060) describes the ADC module. The module is a

12−bit pipelined ADC. The analog circuits of this converter, referred to

as the core in this document, include the front-end analog multiplexers

(MUXs), sample−and−hold (S/H) circuits, the conversion core, voltage

regulators, and other analog supporting circuits. Digital circuits, referred

to as the wrapper in this document, include programmable conversion

sequencer, result registers, interface to analog circuits, interface to de-

vice peripheral bus, and interface to other on-chip modules.

TMS320x281x Boot ROM Reference Guide (literature number SPRU095)

describes the purpose and features of the bootloader (factory-pro-

Related Documentation From Texas Instruments

grammed boot-loading software). It also describes other contents of the

device on-chip boot ROM and identifies where all of the information is lo-

cated within that memory.

TMS320x281x, 280x Enhanced Controller Area Network (eCAN) Refer-

ence Guide (literature number SPRU074) describes the eCAN that uses

established protocol to communicate serially with other controllers in

electrically noisy environments. With 32 fully configurable mailboxes and

time-stamping feature, the eCAN module provides a versatile and robust

serial communication interface. The eCAN module implemented in the

C28x DSP is compatible with the CAN 2.0B standard (active).

TMS320x281x Event Manager (EV) Reference Guide (literature number

SPRU065) describes the EV modules that provide a broad range of func-

tions and features that are particularly useful in motion control and motor

control applications. The EV modules include general-purpose (GP) tim-

ers, full-compare/PWM units, capture units, and quadrature-encoder

pulse (QEP) circuits.

TMS320x281x External Interface (XINTF) Reference Guide (literature

number SPRU067) describes the external interface (XINTF) of the 28x

digital signal processors (DSPs).

TMS320x281x, 280x Peripheral Reference Guide (literature number

SPRU566) describes the peripheral reference guides of the 28x digital

signal processors (DSPs).

TMS320x281x, 280x Serial Communication Interface (SCI) Reference

Guide(literature number SPRU051) describes the SCI that is a two-wire

asynchronous serial port, commonly known as a UART. The SCI mod-

ules support digital communications between the CPU and other asyn-

chronous peripherals that use the standard non-return-to-zero (NRZ)

format.

TMS320x281x, 280x Serial Peripheral Interface (SPI) Reference Guide (lit-

erature number SPRU059) describes the SPI − a high-speed synchro-

nous serial input/output (I/O) port that allows a serial bit stream of pro-

grammed length (one to sixteen bits) to be shifted into and out of the de-

vice at a programmed bit−transfer rate. The SPI is used for communica-

tions between the DSP controller and external peripherals or another

controller.

TMS320x281x System Control and Interrupts Reference Guide (literature

number SPRU078) describes the various interrupts and system control

features of the 281x digital signal processors (DSPs).

Related Documentation From Texas Instruments

Read This First

The TMS320C28x Instruction Set Simulator Technical Overview (litera-

ture number SPRU608) describes the simulator, available within the

Code Composer Studio for TMS320C2000 IDE, that simulates the in-

struction set of the C28x core.

TMS320C28x DSP/BIOS Application Programming Interface (API) Refer-

ence Guide (literature number SPRU625) describes development using

DSP/BIOS.

3.3 V DSP for Digital Motor Control Application Report (literature num-

ber SPRA550). New generations of motor control digital signal proc-

essors (DSPs) lower their supply voltages from 5 V to 3.3 V to offer

higher performance at lower cost. Replacing traditional 5-V digital

control circuitry by 3.3-V designs introduce no additional system cost

and no significant complication in interfacing with TTL and CMOS

compatible components, as well as with mixed voltage ICs such as

power transistor gate drivers. Just like 5-V based designs, good engi-

neering practice should be exercised to minimize noise and EMI ef-

fects by proper component layout and PCB design when 3.3-V DSP,

ADC, and digital circuitry are used in a mixed signal environment, with

high and low voltage analog and switching signals, such as a motor

control system. In addition, software techniques such as Random

PWM method can be used by special features of the Texas Instru-

ments (TI) TMS320x24xx DSP controllers to significantly reduce noise

effects caused by EMI radiation.

This application report reviews designs of 3.3-V DSP versus 5-V DSP

for low HP motor control applications.The application report first de-

scribes a scenario of a 3.3-V-only motor controller indicating that for

most applications, no significant issue of interfacing between 3.3 V

and 5 V exists. Cost-effective 3.3-V − 5-V interfacing techniques are

then discussed for the situations where such interfacing is needed.

On-chip 3.3-V ADC versus 5-V ADC is also discussed. Sensitivity and

noise effects in 3.3-V and 5-V ADC conversions are addressed.

Guidelines for component layout and printed circuit board (PCB) de-

sign that can reduce system’s noise and EMI effects are summarized

in the last section.

Thermo-Electric Cooler Control Using a TMS320F2812 DSP & DRV592

Power Amplifier Application Note (literature number SPRA873).

This application report presents a thermoelectric cooler system con-

sisting of a Texas Instruments TMS320F2812 digital signal processor

(DSP) and DRV592 power amplifier. The DSP implements a digital

proportional-integral-derivative feedback controller using an integrated

12-bit analog-to-digital converter to read the thermistor, and direct out-

put of pulse-width-modulated waveforms to the H-bridge DRV592

power amplifier. The system presented provides up to 6.1 watts of

heating or cooling to the laser mount, although the DRV592 amplifier

is actually capable of delivering up to 15 watts when configured ap-

propriately. The closed-loop TEC system is seen to achieve

±0.0006°C temperature accuracy, depending on the needed operating

temperature range, with a step response settling time of 14 to 16 sec-

onds. A complete description of the experimental system, along with

software and software operating instructions, are provided.

Running an Application from Internal Flash Memory on the

TMS320F281x DSP Application Report (literature number

SPRA958). Several special requirements exist for running an applica-

tion from on-chip flash memory on the TMS320F28x DSP. These re-

quirements generally do not manifest themselves during development

in RAM since the Code Composer Studio™ debugger can mask

problems associated with initialized sections and how they are linked

to memory. This application report covers the requirements needed to

properly configure application software for execution from on-chip

flash memory. Requirements for both DSP/BIOS™ and non-

DSP/BIOS projects are presented. Some performance considerations

and techniques are also discussed. Example code projects are in-

cluded that run from on-chip flash on the eZdsp™ F2812 devel-

opment board (or alternately any F2812, F2811, or F2810 DSP

board). Code examples that run from internal RAM are also provided

for completeness. These code examples provide a starting point for

code development, if desired.

Trademarks

Code Composer Studio and C28x are trademarks of Texas Instruments.

Contents

vii

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1 Overview 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Introduces the multichannel buffered serial port (McBSP).

1.1 Introduction to the McBSP 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.1 Key Features of the McBSP 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1.2 Block Diagram of the McBSP Module With FIFO 1-4. . . . . . . . . . . . . . . . . . . . . . . . .

1.1.3 McBSP Signals 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Register Summary 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 McBSP Operation 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.1 Data Transfer Process of a McBSP 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.2 Companding (Compressing and Expanding) Data 1-11. . . . . . . . . . . . . . . . . . . . . .

1.3.3 Clocking and Framing Data 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.4 Frame Phases 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.5 McBSP Reception 1-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.6 McBSP Transmission 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3.7 Interrupts and FIFO Events Generated by a McBSP 1-24. . . . . . . . . . . . . . . . . . . .

1.4 Sample Rate Generator of the McBSP 1-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4.1 Clock Generation in the Sample Rate Generator 1-28. . . . . . . . . . . . . . . . . . . . . . . .

1.4.2 Frame Sync Generation in the Sample Rate Generator 1-31. . . . . . . . . . . . . . . . . .

1.4.3 Synchronizing Sample Rate Generator Outputs to an External Clock 1-32. . . . . .

1.4.4 Reset and Initialization Procedure for the Sample Rate Generator 1-34. . . . . . . .

1.4.5 Sample Rate Generator Clocking Examples 1-35. . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 McBSP Exception/Error Conditions 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.1 Overrun in the Receiver 1-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.2 Unexpected Receive Frame-Sync Pulse 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.3 Overwrite in the Transmitter 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.4 Underflow in the Transmitter 1-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.5 Unexpected Transmit Frame-Sync Pulse 1-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Multichannel Selection Modes 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the process for using multichannel selection.

2.1 Channels, Blocks, and Partitions 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Multichannel Selection 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Configuring a Frame for Multichannel Selection 2-2. . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Using Two Partitions 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Using Eight Partitions 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

viii

2.1.5 Receive Multichannel Selection Mode 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 Transmit Multichannel Selection Modes 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 Disabling/Enabling Versus Masking/Unmasking 2-9. . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 Activity on McBSP Pins for Different Values of XMCM 2-10. . . . . . . . . . . . . . . . . . .

2.1.9 Using Interrupts Between Block Transfers 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 A-bis Mode 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 A-bis Mode Receive Operation 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 A-bis Mode Transmit Operation 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 SPI Protocol 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Clock Stop Mode 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Bits Used to Enable and Configure the Clock Stop Mode 2-16. . . . . . . . . . . . . . . .

2.3.3 Clock Stop Mode Timing Diagrams 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Procedure for Configuring a McBSP for SPI Operation 2-19. . . . . . . . . . . . . . . . . .

2.3.5 McBSP as the SPI Master 2-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6 McBSP as an SPI Slave 2-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Configure the Receiver and Transmitter 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes how to configure the receiver and transmitter.

3.1 Receiver Configuration 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1 Programming the McBSP Registers for the Desired Receiver Operation 3-2. . . .

3.1.2 Resetting and Enabling the Receiver 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.3 Clock Stop Mode 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.4 Receive Multichannel Selection and A-bis Modes 3-6. . . . . . . . . . . . . . . . . . . . . . . .

3.1.5 Choose 1 or 2 Phases for the Receive Frame 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.6 Set the Receive Companding Mode 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.7 Set the Receive Data Delay 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.8 Set the Receive Sign-Extension and Justification Mode 3-12. . . . . . . . . . . . . . . . . .

3.1.9 Set the Receive Interrupt Mode 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.10 Set the Receive Frame-Sync Mode 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.11 Set the Receive Frame-Sync Polarity 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Transmitter Configuration 3-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Programming the McBSP Registers for the Desired Transmitter Operation 3-26.

3.2.2 Resetting and Enabling the Transmitter 3-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.3 Set the Transmitter Pins to Operate as McBSP Pins 3-28. . . . . . . . . . . . . . . . . . . .

3.2.4 Enable/Disable the Digital Loopback Mode 3-28. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 Enable/Disable the Clock Stop Mode 3-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.6 Enable/Disable Transmit Multichannel Selection 3-30. . . . . . . . . . . . . . . . . . . . . . . .

3.2.7 Enable/Disable the A-bis Mode 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.8 Choose 1 or 2 Phases for the Transmit Frame 3-31. . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.9 Set the Transmit Word Length(s) 3-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.10 Set the Transmit Frame Length 3-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.11 Set the Transmit Companding Mode 3-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.12 Set the Transmit Data Delay 3-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.13 Set the Transmit DXENA Mode 3-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

3.2.14 Set the Transmit Interrupt Mode 3-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.15 Set the Transmit Frame-Sync Mode 3-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.16 Set the Transmit Frame-Sync Polarity 3-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.17 Set the SRG Frame-Sync Period and Pulse Width 3-42. . . . . . . . . . . . . . . . . . . . . .

3.2.18 Set the Transmit Clock Mode 3-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.19 Set the SRG Clock Divide-Down Value 3-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.20 Set the SRG Clock Mode (Choose an Input Clock) 3-47. . . . . . . . . . . . . . . . . . . . . .

4 Emulation and Reset Considerations 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes resetting and initializing the McBSP.

4.1 McBSP Emulation Mode 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Resetting and Initializing a McBSP 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Data Packing Examples 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Data Packing Using Frame Length and Word Length 4-8. . . . . . . . . . . . . . . . . . . . .

4.2.2 Data Packing Using Word Length and the Frame-Sync Ignore Function 4-9. . . .

4.3 GPIO Function 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 McBSP FIFO and Interrupts 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the FIFO interface logic.

5.1 McBSP FIFO Overview 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 McBSP Functionality and Limitation Under FIFO Mode 5-3. . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 McBSP FIFO Operation 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 McBSP Receive Interrupt Generation 5-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 McBSP Transmit Interrupt Generation 5-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.1 FIFO Data Register Access Constraints 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.2 FIFO Error Flags 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.3 McBSP IDLE Mode 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5.4 McBSP Reset Conditions 5-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 McBSP FIFO Register Descriptions 5-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 McBSP Registers 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the McBSP registers and bit descriptions.

6.1 Data Receive and Transmit Registers 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1 Data Receive Registers (DRR2 and DRR1) 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2 How Data Travels From the Data Receive (DR) Pin to the DRRs 6-2. . . . . . . . . . .

6.1.3 Data Transmit Registers (DXR2 and DXR1) 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.4 How Data Travels From the DXRs to the Data Transmit (DX) Pin 6-3. . . . . . . . . .

6.2 Serial Port Control Registers (SPCR1 and SPCR2) 6-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Receive Control Registers (RCR1 and RCR2) 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Transmit Control Registers (XCR1 and XCR2) 6-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Sample Rate Generator Registers (SRGR1 and SRGR2) 6-14. . . . . . . . . . . . . . . . . . . . . . .

6.6 Multichannel Control Registers (MCR1 and MCR2) 6-17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 Pin Control Register (PCR) 6-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.8 Receive Channel Enable Registers (RCERA − RCERH) 6-24. . . . . . . . . . . . . . . . . . . . . . . .

Contents

6.8.1 RCERs Used in the Receive Multichannel Selection Mode 6-26. . . . . . . . . . . . . . .

6.8.2 RCERs Used in the A-bis Mode 6-27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.9 Transmit Channel Enable Registers (XERA − XCERH) 6-29. . . . . . . . . . . . . . . . . . . . . . . . .

6.9.1 XCERs Used in a Transmit Multichannel Selection Mode 6-30. . . . . . . . . . . . . . . .

6.9.2 XCERs Used in the A-bis Mode 6-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.10 Register Bit Summary 6-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Revision History A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .