Toshiba 27WLT56B User manual

TOSHIBA
27WLT56B
SERVICE MANUAL

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27” TFT TV Service Manual 05/09/2005
TABLE OF CONTENTS
1. INTRODUCTION ...................................................................................................................................... 1
2. TUNER...................................................................................................................................................... 1
3. IF PART (TDA9886) ................................................................................................................................. 1
4. MULTI STANDARD SOUND PROCESSOR ............................................................................................ 2
5. VIDEO SWITCH TEA6415 ....................................................................................................................... 2
6. AUDIO AMPLIFIER STAGE WITH TPA3002D2 ...................................................................................... 2
7. MAIN POWER SUPPLY (SMPS) AND POWER INTERFACE BOARD .................................................. 3
8. MICROCONTROLLER ............................................................................................................................. 3
9. SERIAL ACCESS CMOS 4K x 8 (32K bit) EEPROM 24C32A................................................................. 3
10. CLASS AB STEREO HEADPHONE DRIVER TDA1308 ......................................................................... 3
11. SAW FILTERS.......................................................................................................................................... 3
12. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM ....................................................................... 4
12.1. TDA9886 ........................................................................................................................................... 5
12.2. TEA6415C ......................................................................................................................................... 6
12.3. 24C32A.............................................................................................................................................. 7
12.4. SAA5264 ........................................................................................................................................... 8
12.5. LM317.............................................................................................................................................. 10
12.6. ST24LC21 ....................................................................................................................................... 10
12.7. TLC7733.......................................................................................................................................... 11
12.8. 74LVC257A ..................................................................................................................................... 12
12.9. 74LVC14A ....................................................................................................................................... 12
12.10. LM1117............................................................................................................................................ 13
12.11. IRF7314- IRF7316........................................................................................................................... 14
12.12. MC34063A....................................................................................................................................... 15
12.13. LM2576- 52kHz Simple 3A Buck Regulator.................................................................................... 16
12.14. DS90C385 ....................................................................................................................................... 17
12.15. MSP34X1G...................................................................................................................................... 19
12.16. TPA3002D ....................................................................................................................................... 22
12.17. TDA1308 ......................................................................................................................................... 22
12.18. PI5V330........................................................................................................................................... 23
12.19. MST9883 ......................................................................................................................................... 23
12.20. SAA7118E ....................................................................................................................................... 25
12.21. TPS72501........................................................................................................................................ 30
12.22. TSOP1136....................................................................................................................................... 32
12.23. PCF8591 ......................................................................................................................................... 32
12.24. PW1231........................................................................................................................................... 33
12.25. PW181............................................................................................................................................. 34
12.26. SIL1169 ........................................................................................................................................... 35
12.27. SDRAM 4M x 16 (MT48LC4M16A2TG-75)..................................................................................... 36
12.28. FLASH 16MBit................................................................................................................................. 38
12.29. ASM3P2814 .................................................................................................................................... 39
12.30. 74LX1G86 ....................................................................................................................................... 40
12.31. 74HCT4053 ..................................................................................................................................... 41
13. IC DESCRIPTIONS (FOR DIGITAL) ...................................................................................................... 42
13.1. STI5518 ........................................................................................................................................... 42
13.2. MAX232_SMD................................................................................................................................. 42
13.3. 74HCU04......................................................................................................................................... 43
13.4. TSH22 ............................................................................................................................................. 44
13.5. CS4334............................................................................................................................................ 44
13.6. AMIC A43L2616 .............................................................................................................................. 45
13.7. MX29LV160T................................................................................................................................... 47
13.8. 24C32 .............................................................................................................................................. 48
13.9. STV0360.......................................................................................................................................... 49
13.10. MAX809........................................................................................................................................... 52
13.11. TDCC2345TV39A............................................................................................................................ 53
13.12. STV0700.......................................................................................................................................... 53

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27” TFT TV Service Manual 05/09/2005
14. SERVICE MENU SETTINGS ................................................................................................................. 58
14.1. display menu ................................................................................................................................... 58
14.2. calibration menu .............................................................................................................................. 60
14.3. deinterlacer menu............................................................................................................................ 62
14.4. factory settings menu ...................................................................................................................... 64
15. BLOCK DIAGRAMS ............................................................................................................................... 65
16. CIRCUIT DIAGRAMS ............................................................................................................................. 67

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27” TFT TV Service Manual 05/09/2005
1. INTRODUCTION
27” TFT IDTV is a progressive TV control system with built-in de-interlacer and scaler. It uses a
1280*720 panel with 16:9 aspect ratio.The TV is capable of operation in PAL, SECAM, NTSC
(playback) colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including
German and NICAM stereo. Sound system output is supplying 2x8W (10%THD) for stereo 8
speakers. The chassis is equipped with many inputs and outputs allowing it to be used as a center of a
media system.
It supports following peripherals:
2 SCART’s with all of them supporting full SCART features including RGB input
1 AV input. (CVBS+ Stereo Audio)
1 SVHS iput
1 Stereo Headphone output
1 D-Sub 15 PC input
1 DVI input (supports HDCP)
1 Audio line out
1 Stereo audio input for PC/DVI
2 CI (Common Interface) slots
Other features include, 10 pg Teletext, Picture-In-Picture (PIP) , Picture-And-Picture (PAP) , Picture-
And-Text (PAT).
2. TUNER
The tuners used in the design are combined VHF, UHF tuners suitable for CCIR systems B/G, H, L, L’,
I/I’, and D/K. The tuning is available through the digitally controlled I2C bus (PLL). Below you will find
info on one of the Tuners in use.
General description of UV1316:
The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’. The low
IF output impedance has been designed for direct drive of a wide variety of SAW filters with sufficient
suppression of triple transient.
Features of UV1316:
1. Member of the UV1300 family small sized UHF/VHF tuners
2. Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
3. Digitally controlled (PLL) tuning via I2C-bus
4. Off-air channels, S-cable channels and Hyperband
5. World standardised mechanical dimensions and world standard pinning
6. Compact size
7. Complies to “CENELEC EN55020” and “EN55013”
Pinning:
1. Gain control voltage (AGC) : 4.0V, Max: 4.5V
2. Tuning voltage
3. I²C-bus address select : Max: 5.5V
4. I²C-bus serial clock : Min:-0.3V, Max: 5.5V
5. I²C-bus serial data : Min:-0.3V, Max: 5.5V
6. Not connected
7. PLL supply voltage : 5.0V, Min: 4.75V, Max: 5.5V
8. ADC input
9. Tuner supply voltage : 33V, Min: 30V, Max: 35V
10. Symmetrical IF output 1
11. Symmetrical IF output 2
3. IF PART (TDA9886)
The TDA9886 is an alignment-free multistandard (PAL, SECAM and NTSC) vision and sound IF signal PLL
Both devices can be used for TV, VTR, PC and set-top box applications.
The following figure shows the simplified block diagram of the integrated circuit.
The integrated circuit comprises the following functional blocks:

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27” TFT TV Service Manual 05/09/2005
VIF amplifier, Tuner and VIF-AGC, VIF-AGC detector, Frequency Phase-Locked Loop (FPLL) detector, VCO
and divider, Digital acquisition help and AFC, Video demodulator and amplifier, Sound carrier trap, SIF
amplifier, SIF-AGC detector, Single reference QSS mixer, AM demodulator, FM demodulator and acquisition
help, Audio amplifier and mute time constant, I²C-bus transceivers and MAD (module address), Internal
voltage stabilizer.
4. MULTI STANDARD SOUND PROCESSOR
The MSP34x1G family of single-chip Multistandard Sound Processors covers the sound processing of
all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound
processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on
a single chip.
These TV sound processing ICs include versions for processing the multichannel television sound
(MTS) signal conforming to the standard recommended by the Broadcast Television Systems
Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is
performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard
(EIA-J) and the FM Stereo Radio standard.
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for
BTSC and EIA-J. The MSP34x1G has optimum stereo performance without any adjustments.
5. VIDEO SWITCH TEA6415
In case of three or more external sources are used, the video switch IC TEA6415 is used. The main
function of this device is to switch 8 video-input sources on the 6 outputs.
Each output can be switched on only one of each input. On each input an alignment of the lowest level
of the signal is made (bottom of sync. top for CVBS or black level for RGB signals).
Each nominal gain between any input and output is 6.5dB.For D2MAC or Chroma signal the alignment
is switched off by forcing, with an external resistor bridge, 5VDC on the input. Each input can be used
as a normal input or as a MAC or Chroma input (with external Resistor Bridge). All the switching
possibilities are changed through the BUS. Driving 75ohm load needs an external resistor. It is possible
to have the same input connected to several outputs.
6. AUDIO AMPLIFIER STAGE WITH TPA3002D2
The TPA3002D2 is a 9-W (per channel) efficient, Class-D audio amplifier for driving bridged-tied stereo
speakers. The TPA3002D2 can drive stereo speakers as low as 8 . The high efficiency of the
TPA3002D2 eliminates the need for external heatsinks when playing music.

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7. MAIN POWER SUPPLY (SMPS) AND POWER INTERFACE BOARD
The DC voltages required at various parts of the chassis and inverters are provided by an main power
supply unit and power interface board. The main power supply unit is designed for 24V and 12V DC
supply. Power interface board generates +12V for audio amplifier, 5V and 3.3V stand by voltage and
8V, 12V, 5V and 3V3 supplies for other different parts of the chassis.
An optocoupler is used to control the regulation of line voltage and stand-by power consumption. There
is a regulation circuit in secondary side. During the switch on period of the transistor, energy is stored in
the transformer. During the switch off period energy is fed to the load via secondary winding. By varying
switch-on time of the power transistor, it controls each portion of energy transferred to the second side
such that the output voltage remains nearly independent of load variations.
8. MICROCONTROLLER
The microprocessor is embedded inside PW181 chip which also handles scaling, frame rate conversion
and OSD generation. The on-chip 16-bit microprocessor is a Turbo x86-compatible processor core with
on-chip peripherals (timers, interrupt controller, 2-wire serial master/slave interface, UART, I/O ports,
and more). Special peripherals such as Infrared (IR) pulse decoders and a digital pulse width modulator
(PWM) are also included. There are two independent 2-wire serial master/slave interface modules that
can be multiplexed to control up to five 2-wire serial ports. The slave 2-wire interface is designed for
HDCP use only (and requires the use of HDCP Image Processors). On-chip RAM of up to 64 Kbytes is
available. A complete microprocessor system can be implemented simply by adding external ROM. The
on-chip processor can be disabled to allow external processor control of all internal functions.
9. SERIAL ACCESS CMOS 4K x 8 (32K bit) EEPROM 24C32A
The Microchip Technology Inc. 24C32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. It has
been developed for advanced, low power applications such as personal communications or data
acquisition. The 24C32A also has a page-write capability of up to 32 bytes of data. The 24C32A is
capable of both random and sequential reads up to the 32K boundary. Functional address lines allow
up to eight 24C32A devices on the same bus, for up to 256K bits address space. Advanced CMOS
technology and broad voltage range make this device ideal for low-power/low-voltage, non-volatile code
and data applications.
10.CLASS AB STEREO HEADPHONE DRIVER TDA1308
The TDA1308 is an integrated class AB stereo headphone driver contained in a DIP8 plastic package.
The device is fabricated in a 1 mm CMOS process and has been primarily developed for portable digital
audio applications.
11.SAW FILTERS
K9656M:
Standard:
• B/G
• D/K
• I
• L/L’
Features
• TV IF audio filter with two channels
• Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75 MHz (L’- NICAM)
• Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz and 33,40 MHz
Terminals
• Tinned CuFe alloy
Pin configuration
1 Input
2 Switching input
3 Chip carrier - ground
4 Output
5 Output

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27” TFT TV Service Manual 05/09/2005
K3953M:
Standard:
• B/G
• D/K
• I
• L/L’
Features
TV IF video filter with Nyquist slopes at 33,90 MHz and 38,90 MHz
Constant group delay
Suitable for CENELEC EN 55020
Terminals
Tinned CuFe alloy
Pin configuration
1 Input
2 Input - ground
3 Chip carrier - ground
4 Output
5 Output
12.IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM
TDA9886
TEA6415C
24C32
SAA5264
LM317T
ST24LC21
TLC7733
74LVC257A
74LVC14A
LM1117
IRF7314
IRF7316
MC34063A
LM2576
DS90C385
MSP3411G
TPA3002D
TDA1308
PI5V330
MST9883
SAA7118E
TPS72501
TSOP1136
PCF8591
PW1231
PW181
SIL1169
SDRAM 4M x 16 (MT48LC4M16A2TG-75)
FLASH
ASM3P2814
74LX1G86
74HCT4053

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27” TFT TV Service Manual 05/09/2005
12.1. TDA9886
12.1.1. General Description
The TDA9885 is an alignment-free single standard (without positive modulation) vision and sound IF signal
PLL.
12.1.2. Features
• 5 V supply voltage
• Gain controlled wide-band Vision Intermediate Frequency (VIF) amplifier (AC-coupled)
• Multistandard true synchronous demodulation with active carrier regeneration (very linear demodulation,
good intermodulation figures, reduced harmonics, excellent pulse response)
• Gated phase detector for L/L accent standard
• Fully integrated VIF Voltage Controlled Oscillator (VCO), alignment-free; frequencies switchable for all
negative and positive modulated standards via I2C-bus
• Digital acquisition help, VIF frequencies of 33.4, 33.9, 38.0, 38.9, 45.75 and 58.75 MHz
• 4 MHz reference frequency input [signal from Phase-Locked Loop (PLL) tuning system] or operating as
crystal oscillator
• VIF Automatic Gain Control (AGC) detector for gain control, operating as peak sync detector for negative
modulated signals and as a peak white detector for positive modulated signals
• Precise fully digital Automatic Frequency Control (AFC) detector with 4-bit digital-to-analog converter; AFC
bits via I2C -bus readable
• TakeOver Point (TOP) adjustable via I2C-bus or alternatively with potentiometer
• Fully integrated sound carrier trap for 4.5, 5.5, 6.0 and 6.5 MHz, controlled by FM-PLL oscillator
• Sound IF (SIF) input for single reference Quasi Split Sound (QSS) mode (PLL controlled)
• SIF AGC for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance
single reference QSS mode and in intercarrier mode, switchable via I2C-bus
• AM demodulator without extra reference circuit
• Alignment-free selective FM-PLL demodulator with high linearity and low noise
• I2C-bus control for all functions
• I2C-bus transceiver with pin programmable Module Address (MAD).
12.1.3. Pinning
SYMBOL PIN DESCRIPTION
VIF1 1
VIF differential input 1
VIF2 2 VIF differential input 2
OP1 3 output 1 (open-collector)
FMPLL 4 FM-PLL for loop filter
DEEM 5 de-emphasis output for capacitor
AFD 6 AF decoupling input for capacitor
DGND 7 digital ground
AUD 8 audio output
TOP 9 tuner AGC TakeOver Point (TOP)
SDA 10 I2C-bus data input/output
SCL 11 I2C-bus clock input
SIOMA 12 sound intercarrier output and MAD select
n.c. 13 not connected
TAGC 14 tuner AGC output
REF 15 4 MHz crystal or reference input
VAGC 16 VIF-AGC for capacitor; note 1
CVBS 17 video output
AGND 18 analog ground
VPLL 19 VIF-PLL for loop filter
VP20
supply voltage (+5 V)
AFC 21 AFC output

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27” TFT TV Service Manual 05/09/2005
OP2 22 output 2 (open-collector)
SIF1 23 SIF differential input 1
SIF2 24 SIF differential input 2
12.2. TEA6415C
12.2.1. General Description
The main function of the IC is to switch 8 video input sources on 6 outputs. Each output can be
switched on only one of each input. On each input an alignment of the lowest level of the signal is made
(bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input
and output is 6.5dB. For D2MAC or Chroma signal the alignment is switched off by forcing, with an
external resistor bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or
Chroma input (with external resistor bridge). All the switching possibilities are changed through the
BUS. Driving 75load needs an external transistor. It is possible to have the same input connected to
several outputs. The starting configuration upon power on (power supply: 0 to 10V) is undetermined. In
this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16
bits is necessary to determine one configuration.
12.2.2. Features
• 20MHz Bandwidth
• Cascadable with another TEA6415C (Internal address can be changed by pin 7 voltage)
• 8 Inputs (CVBS, RGB, MAC, CHROMA,...)
• 6 Outputs
• Possibility of MAC or chroma signal for each input by switching-off the clamp with an external resistor
bridge
• Bus controlled
• 6.5dB gain between any input and output
• 55dB crosstalk at 5mHz
• Fully ESD protected
12.2.3. Pinning
1. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
2. Data : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
3. Input : Max : 2Vpp, Input Current: 1mA, Max : 3mA
4. Clock : Low level : -0.3V Max: 1.5V,
High level : 3.0V Max : Vcc+0.5V
5. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
6. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
7. Prog
8. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
9. Vcc : 12V
10. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
11. Input : Max : 2Vpp, Input Current: 1mA, Max: 3mA
12. Ground
13. Output : 5.5Vpp, Min : 4.5Vpp
14. Output : 5.5Vpp, Min : 4.5Vpp
15. Output : 5.5Vpp, Min : 4.5Vpp
16. Output : 5.5Vpp, Min : 4.5Vpp
17. Output : 5.5Vpp, Min : 4.5Vpp
18. Output : 5.5Vpp, Min : 4.5Vpp
19. Ground
20. Input : Max : 2Vpp, Input Current : 1mA, Max : 3mA

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27” TFT TV Service Manual 05/09/2005
12.3. 24C32A
12.3.1. Features
• Voltage operating range: 4.5V to 5.5V
- Maximum write current 3 mA at 5.5V
- Standby current 1 mA typical at 5.0V
• 2-wire serial interface bus, I2CTM compatible
• 100 kHz and 400 kHz compatibility
• Self-timed ERASE and WRITE cycles
• Power on/off data protection circuitry
• Hardware write protect
• 1,000,000 Erase/Write cycles guaranteed
• 32-byte page or byte write modes available
• Schmitt trigger filtered inputs for noise suppression
• Output slope control to eliminate ground bounce
• 2 ms typical write cycle time, byte or page
• Up to eight devices may be connected to the same bus for up to 256K bits total memory
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP and SOIC packages
• Temperature ranges
- Commercial (C): 0°C to 70°C
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
12.3.2. Description
The Microchip Technology Inc. 24C32A is a 4K x 8 (32K bit) Serial Electrically Erasable PROM. It has
been developed for advanced, low power applications such as personal communications or data
acquisition. The 24C32A also has a page-write capability of up to 32 bytes of data. The 24C32A is
capable of both random and sequential reads up to the 32K boundary. Functional address lines allow
up to eight 24C32A devices on the same bus, for up to 256K bits address space. Advanced CMOS
technology and broad voltage range make this device ideal for low-power/low-voltage, non-volatile code
and data applications. The 24C32A is available in the standard 8-pin plastic DIP and both 150 mil and
200 mil SOIC packaging.
12.3.3. Pin Function table
Name Function
A0, A1, A2 User Configurable Chip Selects
Vss Ground
SDA Serial Address/Data I/O
SCL Serial Clock
WP Write Protect Input
Vcc +4.5V to 5.5V Power Supply

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12.3.4. Functional Descriptions
The 24C32A supports a Bi-directional 2-wire bus and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be
controlled by a master device which generates the Serial Clock (SCL), controls the bus access, and
generates the START and STOP conditions, while the 24C32A works as slave. Both master and slave
can operate as transmitter or receiver but the master device determines which mode is activated.
12.4. SAA5264
12.4.1. Features
The following features apply to both SAA5264 and SAA5265:
• Complete 625 line teletext decoder in one chip reduces printed circuit board area and cost
• Automatic detection of transmitted fastext links or service information (packet 8/30)
• On-Screen Display (OSD) for user interface menus using teletext and dedicated menu icons
• Video Programming System (VPS) decoding
• Wide Screen Signalling (WSS) decoding
• Pan-European, Cyrillic, Greek/Turkish and French/Arabic character sets in each chip
• High-level command interface via I2C-bus gives easy control with a low software overhead
• High-level command interface is backward compatible to Stand-Alone Fastext And Remote Interface
(SAFARI)
• 625 and 525 line display
• RGB interface to standard colour decoder ICs, current source
• Versatile 8-bit open-drain Input/Output (I/O) expander, 5 V tolerant
• Single 12 MHz crystal oscillator
• 3.3 V supply voltage.
SAA5264 features
• Automatic detection of transmitted pages to be selected by page up and page down
• 8 Page fastext decoder
• Table Of Pages (TOP) decoder with Basic Top Table (BTT) and Additional Information Tables (AITs)
• 4 Page user-defined list mode.
12.4.2. General Description
The SAA5264 is a single-chip ten page 625-line World System Teletext decoder with a high-level
command interface, and is SAFARI compatible.
The device is designed to minimize the overall system cost, due to the high-level command interface
offering the benefit of a low software overhead in the TV microcontroller.
The SAA5264 has the following functionality:
• 10 page teletext decoder with OSD, Fastext, TOP, default and list acquisition modes
• Automatic channel installation support
• Closed caption acquisition and display
• Violence Chip (VChip) support.
12.4.3. Pin Connections and Short Descriptions
SYMBOL PIN TYPE DESCRIPTION
Port 2: 8-bit programmable bidirectional port with alternative functions
P2.0/PWM 1 I/O output for 14-bit high precision Pulse Width Modulator (PWM)
P2.1/PWM0 2 I/O outputs for 6-bit PWMs 0 to 6
P2.2/PWM1 3 I/O
P2.3/PWM2 4 I/O
P2.4/PWM3 5 I/O
P2.5/PWM4 6 I/O
P2.6/PWM5 7 I/O
P2.7/PWM6 8 I/O
Port 3: 8-bit programmable bidirectional port with alternative functions
P3.0/ADC0 9 I/O inputs for the software Analog-to-Digital-Converter (ADC) facility
P3.1/ADC1 10 I/O

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P3.2/ADC2 11 I/O
P3.3/ADC3 12 I/O
P3.4/PWM7 30 I/O output for 6-bit PWM7
VSSC 13 I/O core ground
Port 0: 8-bit programmable bidirectional port
SCL(NVRAM) 14 I I2C-bus Serial Clock input to Non-Volatile RAM
SDA(NVRAM) 15 I/O I2C-bus Serial Data input/output (Non-Volatile RAM)
P0.2 16 I/O input/output for general use
P0.3 17 I/O input/output for general use
P0.4 18 I/O input/output for general use
P0.5 19 I/O 8 mA current sinking capability for direct drive of Light Emitting
Diodes (LEDs)
P0.6 20 I/O
P0.7 21 I/O input/output for general use
VSSA 22 -
analog ground
CVBS0 23 I Composite Video Baseband Signal (CVBS) input; a positive-going
1V
CVBS1 24 I (peak-to-peak) input is required; connected via a 100 nF capacitor
SYNC_FILTER 25 I sync-pulse-filter input for CVBS; this pin should be connected to VSSA
via a 100 nF capacitor
IREF 26 I reference current input for analog circuits; for correct operation a 24
κΩ resistor should be connected to VSSA
FRAME 27 O Frame de-interlace output synchronized with the VSYNC pulse to
produce a non-interlaced display by adjustment of the vertical
deflection circuits
TEST 28 I not available; connect this pin to VSSA
COR 29 O contrast reduction: open-drain, active LOW output which allows
selective contrast reduction of the TV picture to enhance a mixed
mode display
30 I/O P3.4/PWM7 (described above)
VDDA 31 -
analog supply voltage (3.3 V)
B 32 O Blue colour information pixel rate output
G 33 O Green colour information pixel rate output
R 34 O Red colour information pixel rate output
VDS 35 O video/data switch push-pull output for pixel rate fast blanking
HSYNC 36 I horizontal sync pulse input: Schmitt triggered for a Transistor
Transistor Level (TTL) version; the polarity of this pulse is
programmable by register bit TXT1.H POLARITY
VSYNC 37 I vertical sync pulse input; Schmitt triggered for a TTL version; the
polarity of this pulse is programmable by register bit TXT1.V
POLARITY
VSSP 38 - periphery ground
VDDC 39 - core supply voltage (+3.3 V)
OSCGND 40 -* crystal oscillator ground
XTALIN 41 I 12 MHz crystal oscillator input
XTALOUT 42 O 12 MHz crystal oscillator output
RESET 43 I reset input; if this pin is HIGH for at least 2 machine cycles (24
oscillator periods) while the oscillator is running, the device resets;
this pin should be connected to VDDP via a capacitor
VDDP 44 - periphery supply voltage (+3.3 V)
Port 1: 8-bit programmable bidirectional port
P1.0 45 I/O input/output for general use
P1.1 46 I/O input/output for general use
P1.2 47 I/O input/output for general use
P1.3 48 I/O input/output for general use
SCL 49 I I2C-bus Serial Clock input from application

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SDA 50 I/O I2C-bus Serial Data input from (application)
P1.4 51 I/O input/output for general use
P1.5 52 I/O input/output for general use
12.5. LM317
12.5.1. General Description
The LM117/LM217/LM317 are monolithic integrated circuit in TO-220, ISOWATT220, TO-3 and D 2
PAK packages intended for use as positive adjustable voltage regulators.
They are designed to supply more than 1.5A of load current with an output voltage adjustable over a
1.2 to 37V range.
The nominal output voltage is selected by means of only a resistive divider, making the device
exceptionally easy to use and eliminating the stocking of many fixed regulators.
12.5.2. Features
• Output voltage range : 1.2 To 37V
• Output current In excess of 1.5A
• 0.1% Line and Load Regulation
• Floating Operation for High Voltages
• Complete Series of Protections : Current Limiting, Thermal Shutdown And Soa Control
12.6. ST24LC21
12.6.1. Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits.
This device can operate in two modes: Transmit Only mode and I2C bidirectional mode. When powered,
the device is in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal
applied on VCLK. The device will switch to the I2C bidirectional mode upon the falling edge of the signal
applied on SCL pin. The ST24LC21 can not switch from the I2C bidirectional mode to the Transmit Only
mode (except when the power supply is removed). The device operates with a power supply value as
low as 2.5V. Both Plastic Dual-in-Line and Plastic Small Outline packages are available.
12.6.2. Features
• 1 million Erase/Write cycles
• 40 years data retention
• 2.5V To 5.5V single supply voltage
• 400k Hz compatibility over the full range of supply voltage
• Two wire serial interface I2C bus compatible
• Page Write (Up To 8 Bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
• Automatic address incrementing
• Enhanced ESD/Latch up
• Performances

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12.6.3. Pin connections
DIP Pin connections CO Pin connections
NC: Not connected
Signal names
SDA Serial data Address Input/Output
SCL Serial Clock (I2C mode)
Vcc Supply voltage
Vss Ground
VCLK Clock transmit only mode
12.7. TLC7733
12.7.1. Description
The TLC77xx family of micropower supply voltage supervisors are designed for reset control, primarily
in microcomputer and microprocessor systems.
During power-on, RESET is asserted when VDD reaches 1 V. After minimum VDD (. 2 V) is established,
the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage
(VI(SENSE) ) remains below the threshold voltage. An internal timer delays return of the output to the
inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor:
td= 2.1 x 10 4 x CT
where
CTis in farads
tdis in seconds
The TLC77xx has a fixed SENSE threshold voltage set by an internal voltage divider. When SENSE
voltage drops below the threshold voltage, the outputs become active and stay in that state until
SENSE voltage returns above threshold voltage and the delay time, td, has expired.
In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down
control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The
voltage monitor contains additional logic intended for control of static memories with battery backup
during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the
TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the
microprocessor (see Figure 10), the memory circuit is automatically disabled during a power loss. (In
this application the TLC77xx power has to be supplied by the battery.)
The TLC77xxQ is characterized for operation over a temperature range of –40°C to 125°C, and the
TLC77xxI is characterized for operation over a temperature range of –40°C to 85°C.

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12.8. 74LVC257A
12.8.1. Features
Wide supply voltage range of 1.2 to 3.6 V
In accordance with JEDEC standard no. 8-1A
CMOS lower power consumption
Direct interface with TTL levels
Output drive capability 50 _ transmission lines at 85°C
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
12.8.2. Description
The 74LVC257A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to
most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State operation, outputs can handle 5V. This
feature allows the use of these devices as translators in a mixed 3.3V/5V environment.
The 74LVC257A is a quad 2-input multiplexer with 3-state outputs, which select 4 bits of data from two
sources and are controlled by a common data select input (S). The data inputs from source 0 (1l 0 to 4l
0 ) are selected when input S is LOW and the data inputs from source 1 (1l 1 to 4l 1 ) are selected
when S in HIGH. Data appears at the outputs (1Y to 4Y) in true (non-inverting) form from the selected
inputs. The 74LVC257A is the logic implementation of a 4-pole, 2-position switch, where the position of
the switch is determined by the logic levels applied to S. The outputs are forced to a high impedance
OFF-state when OE is HIGH.
12.8.3. Pin Description
PIN NUMBER SYMBOL DESCRIPTION
1 S Common data select input
2, 5, 11, 14 1|0to 4|0Data inputs from source 0
3, 6, 10, 13 1|1to 4|1Data outputs from source 1
4,7,9,12 1Y to 4Y 3-State multiplexer outputs
8 GND Ground (0V)
15 OE 3-State output enable input (active LOW)
16 Vcc Positive supply voltage
12.9. 74LVC14A
12.9.1. Features
• Wide supply voltage range of 1.2 to 3.6 V
• In accordance with JEDEC standard no. 8-1A
• Inputs accept voltages up to 5.5 V
• CMOS low power consumption
• Direct interface with TTL levels
12.9.2. Applications
• Wave and pulse shapers for highly noisy environments
• Astable multivibrators
• Monostable multivibrators
12.9.3. Description
The 74LVC14A is a high-performance, low power, low-voltage Si-gate CMOS device and superior to
most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as
translators in a mixed 3.3 V/5 V environment.
The 74LVC14A provides six inverting buffers with Schmitt-trigger action. It is capable of transforming
slowly changing input signals into sharply defined, jitter-free output signals.

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12.9.4. Pin Description
PIN NUMBER SYMBOL DESCRIPTION
1, 3, 5, 9, 11, 13 1A – 6A Data inputs
2, 4, 6, 8, 10, 12 1Y – 6Y Data outputs
7 GND Ground (0V)
14 Vcc Positive supply voltage
12.10. LM1117
12.10.1. General Description
The LM1117 is a series of low dropout voltage regulators with a dropout of 1.2V at 800mA of load
current. It has the same pin-out as National Semiconductor’s industry standard LM317. The LM1117 is
available in an adjustable version, which can set the output voltage from 1.25V to 13.8V with only two
external resistors. In addition, it is also available in five fixed voltages, 1.8V, 2.5V, 2.85V, 3.3V, and 5V.
The LM1117 offers current limiting and thermal shutdown. Its circuit includes a zener trimmed bandgap
reference to as-sure output voltage accuracy to within ±1%. The LM1117 series is available in SOT-
223, TO-220, and TO-252 D-PAK packages. A minimum of 10µF tantalum capacitor is required at the
output to improve the transient response and stability.
12.10.2. Features
• Available in 1.8V, 2.5V, 2.85V, 3.3V, 5V, and Adjustable Versions
• Space Saving SOT-223 Package
• Current Limiting and Thermal Protection
• Output Current 800mA
• Line Regulation 0.2% (Max)
• Load Regulation 0.4% (Max)
• Temperature Range
— LM1117 0°C to 125°C
— LM1117I -40°C to 125°C
12.10.3. Applications
• 2.85V Model for SCSI-2 Active Termination
• Post Regulator for Switching DC/DC Converter
• High Efficiency Linear Regulators
• Battery Charger
• Battery Powered Instrumentation
12.10.4. Connection Diagrams

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12.11. IRF7314- IRF7316
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to
achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching
speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the
designer with an extremely efficient and reliable device for use in a wide variety of applications.
The SO-8 has been modified through a customized leadframe for enhanced thermal characteristics and
multiple-die capability making it ideal in a variety of power applications. With these improvements,
multiple devices can be used in an application with dramatically reduced board space. The package is
designed for vapor phase, infra red, or wave soldering techniques.
IRF7314 IRF7316
Absolute Maximum Ratings ( TA = 25°C Unless Otherwise Noted) (IRF7314)
Symbol Maximum Units
Drain-Source Voltage VDS -20
Gate-Source Voltage VGS ± 12 V
TA= 25°C -5.3
Continuous Drain Current TA= 70°C I-4.3
Pulsed Drain Current IDM -21
Continuous Source Current (Diode Conduction) IS -2.5
A
TA= 25°C 2.0
Maximum Power Dissipation P
1.3
W
Single Pulse Avalanche Energy EAS 150 mJ
Avalanche Current IAR -2.9 A
Repetitive Avalanche Energy EAR 0.20 mJ
Peak Diode Recovery dv/dt dv/dt -5.0 V/ ns
Junction and Storage Temperature Range TJ, TSTG -55 to + 150 °C
Absolute Maximum Ratings ( TA = 25°C Unless Otherwise Noted) (IRF7316)
Symbol Maximum Units
Drain-Source Voltage VDS -30
Gate-Source Voltage VGS ± 20 V
TA= 25°C -4.9
Continuous Drain Current TA= 70°C I-3.9
Pulsed Drain Current IDM -30
Continuous Source Current (Diode Conduction) IS -2.5
A
TA= 25°C 2.0
Maximum Power Dissipation TA= 70°C P1.3 W
Single Pulse Avalanche Energy EAS 140 mJ
Avalanche Current IAR -2.8 A
Repetitive Avalanche Energy EAR 0.20 mJ
Peak Diode Recovery dv/dt dv/dt -5.0 V/ ns

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Junction and Storage Temperature Range TJ, TSTG -55 to + 150 °C
12.12. MC34063A
1.5 A, Step-Up/Down/Inverting Switching Regulators
The MC34063A Series is a monolithic control circuit containing the primary functions required for
DCtoDC converters. These devices consist of an internal temperature compensated reference,
comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current
output switch. This series was specifically designed to be incorporated in StepDown and StepUp and
VoltageInverting applications with a minimum number of external components. Refer to Application
Notes AN920A/D and AN954/D for additional design information.
Features:
•Operation from 3.0 V to 40 V Input
•Low Standby Current
•Current Limiting
•Output Switch Current to 1.5 A
•Output Voltage Adjustable
•Frequency Operation to 100 kHz
•Precision 2% Reference
•PbFree Packages are Available

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12.13. LM2576- 52kHz Simple 3A Buck Regulator
12.13.1. General Description
The LM2576 series of monolithic integrated circuits provide all the active functions for a step-down
(buck) switching regulator. Fixed versions are available with a 3.3V, 5V, or 12V
fixed output. Adjustable versions have an output voltage range from 1.23V to 37V. Both versions are
capable of driving a 3A load with excellent line and load regulation. These regulators are simple to use
because they require a minimum number of external components and include internal frequency
compensation and a fixed-frequency oscillator. The LM2576 series offers a high efficiency replacement
for popular three-terminal adjustable linear regulators. It substantially reduces the size of the heat sink,
and in many cases no heat sink is required. A standard series of inductors available from several
different manufacturers are ideal for use with the LM2576 series. This feature greatly simplifies the
design of switch-mode power supplies. The feedback voltage is guaranteed to ±2% tolerance for
adjustable versions, and the output voltage is guaranteed to ±3% for fixed versions, within specified
input voltages and output load conditions. The oscillator frequency is guaranteed to ±10%. External
shutdown is included, featuring less than 200⎧A standby current. The output switch includes cycle-
bycycle current limiting and thermal shutdown for full protection under fault conditions.
12.13.2. Features
• 3.3V, 5V, 12V, and adjustable output versions
• Voltage over specified line and load conditions:
Fixed version: ±3% max. output voltage
Adjustable version: ±2% max. feedback voltage
• Guaranteed 3A output current
• Wide input voltage range:
4V to 40V

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• Wide output voltage range
1.23V to 37V
• Requires only 4 external components
• 52kHz fixed frequency internal oscillator
• Low power standby mode IQ typically < 200⎧A
• 80% efficiency (adjustable version typically > 80%)
• Uses readily available standard inductors
• Thermal shutdown and current limit protection
• 100% electrical thermal limit burn-in
12.13.3. Pin Configurations
12.14. DS90C385
12.14.1. General Description
The DS90C385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the
data streams over a fifth LVDS link.
Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock
frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using an 85 MHz
clock, the data throughput is 297.5 Mbytes/sec. Also available is the DS90C365 that converts 21 bits of
LVCMOS/LVTTL data into three LVDS (Low Voltage Differential Signaling) data streams. Both
transmitters can be programmed for Rising edge strobe or falling edge strobe through a dedicated pin.
A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver
(DS90CF386/DS90CF366) without any translation logic.
The DS90C385 is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which
provides a 44 % reduction in PCB footprint compared to the TSSOP package. This chipset is an ideal
means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.
12.14.2. Features
• 20 to 85 MHz shift clock support
• Best–in–Class Set & Hold Times on TxINPUTs
• Tx power consumption <130 mW (typ) @85MHz Grayscale
• Tx Power-down mode <200µW (max)
• Supports VGA, SVGA, XGA and Dual Pixel SXGA.
• Narrow bus reduces cable size and cost