Transmeta Crusoe TM5400 Guide

System Design Guide
Transmeta Crusoe™ Processor
Model TM5400/TM5600
Preliminary Information
Confidential Information—NDA Required

October 13, 2000 System Design Guide
Confidential Information—NDA Required
Crusoe™ Processor Model TM5400/TM5600
System Design Guide
TMDFS-19, Revision 1.9, October 13, 2000
Confidential Information—NDA Required
Property of:
Transmeta Corporation
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Copyright © 2000 Transmeta Corporation. All rights reserved.

TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
Confidential Information—NDA Required 3
Table of Contents
Overview ....................................................................................................................................11
Chapter 1 System Block Diagram ........................................................................................................13
1.1 Power Supply Requirements........................................................................ 14
1.2 Description of Elements in System Block Diagram ..................................... 16
1.2.1 Processor......................................................................................................................16
1.2.2 CD DDR SDRAM .....................................................................................................16
1.2.3 DI SDR SDRAM ........................................................................................................17
1.2.4 Clocking......................................................................................................................23
1.2.5 Using BIOS ROM for CMS storage ............................................................................23
1.2.6 System Reset................................................................................................................24
Chapter 2 Design Considerations ........................................................................................................25
2.1 Important Processor Considerations............................................................ 25
2.2 Important Power Management Issues .......................................................... 26
2.3 DI PCB Layout Guidelines ......................................................................... 27
2.4 TM5400/TM5600 LongRun™ Design Considerations ............................ 28
2.4.1 About LongRun™ Technology ...................................................................................28
2.4.2 LongRun Power Supply ...............................................................................................29
2.4.3 VDDCORE Supply Transition Rates and LongRun ....................................................30
2.4.4 CVDD Rise and Fall Times .........................................................................................30
2.5 Thermal Design Considerations.................................................................. 31
2.6 South Bridge Recommendation................................................................... 31

October 13, 2000 PreliminaryInformation TM5400/TM5600 System Design Guide
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2.7 Power Planes and Power Supply Decoupling ............................................... 31
2.8 Serial Flash Write Protection Circuit ........................................................... 31
2.8.1 Overview .....................................................................................................................32
2.8.2 Serial Flash Write Protection Circuitry.........................................................................32
2.8.3 Schematic Diagram of the PLD in a System ................................................................34
2.8.4 Pinout .........................................................................................................................34
2.8.5 JEDEC Fuse Map ........................................................................................................35
2.8.6 CUPL Source Code .....................................................................................................36
2.8.7 Software Support .........................................................................................................38
2.9 Mode Bit ROM Settings ............................................................................. 40
2.9.1 Programming the Mode Bit ROM with WinTMM .....................................................40
2.9.2 Programming the Mode-Bit ROM with a Device Programmer ....................................42
Chapter 3 PWB Layout ..............................................................................................................................43
3.1 Very Important Layout Requirements ......................................................... 43
3.2 Layout Guidelines ....................................................................................... 44
3.2.1 Recommended Eight Layer PWB Stackup ...................................................................44
3.2.2 Recommended Ten Layer PWB Stackup......................................................................44
3.3 Power Supply Decoupling Layout ............................................................... 45
3.4 Processor Footprint ..................................................................................... 47
3.5 BGA Pin Escape Diagram ........................................................................... 48
3.6 Recommended Standard Spacing/Line/Via Constraints............................... 49
3.6.1 Allegro Extended Spacing Constraints..........................................................................49
3.7 Recommended PWB Fabrication Notes ...................................................... 52

TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
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3.8 DDR SDRAM............................................................................................ 53
3.8.1 DDR Trace Route Examples........................................................................................54
3.8.2 Secondary Side (Bottom) .............................................................................................56
Chapter 4 Thermal Design Considerations .....................................................................................59
4.1 Overview..................................................................................................... 59
4.2 Thermal Design Guidelines......................................................................... 59
4.3 Thermal Transfer Device (TTD) Example Design....................................... 60
4.4 Thermal Measurements............................................................................... 61
4.4.1 400Mhz TM120 at 1.7V .............................................................................................61
4.5 Power Measurements................................................................................... 62
4.6 TTD Mechanical Specifications .................................................................. 63
4.7 Thermal Transfer Device Pictures................................................................ 65
Chapter 5 Crusoe Processor Reference Schematics Description .......................................67
5.1 Core Schematics.......................................................................................... 67
5.2 System Level Reference Schematics ............................................................. 71

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TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
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List of Tables
TABLE 1 Power Supply Requirements.........................................................................................15
TABLE 2 TM3200 to TM5400/TM5600 VRDA Pins ...............................................................28
TABLE 3 Power Consumption of TM3200 at Thermal Measurement Operating conditions ......62

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TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
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List of Figures
FIGURE 1 Core System Block Diagram............................................................................................13
FIGURE 2 Transmeta Debug Connector A .......................................................................................21
FIGURE 3 Transmeta Debug Connector B .......................................................................................22
FIGURE 4 System Reset....................................................................................................................24
FIGURE 5 TM5400/TM5600 VRDA Connection and Timing Diagram for LongRun™ ...............29
FIGURE 6 TM5400/TM5600 VDDCORE Underside BGA Decoupling Example..........................46
FIGURE 7 TM5400/TM5600 Mechanical Footprint .......................................................................47
FIGURE 8 BGA Pin Escape Example................................................................................................48
FIGURE 9 Recommended DDR Layout...........................................................................................54
FIGURE 10 4-Chip DDR Memory Layout, Top Layer.......................................................................55
FIGURE 11 4-Chip DDR Memory Layout, Internal Layer.................................................................56
FIGURE 12 4-Chip DDR Memory Layout, Bottom Layer .................................................................57
FIGURE 13 Thermal Measurement Probe Placement in Laptop System .............................................60
FIGURE 14 Thermal Measurements of TTD in Laptop System–Running Windows (Idle) ................61
FIGURE 15 Thermal Measurements of TTD in Laptop System–Running DOS in Windows (Busy) .62
FIGURE 16 Thermal Transfer Device Mechanical Cross Section.........................................................63
FIGURE 17 TTD Mechanical Top View ............................................................................................63
FIGURE 18 TTD Mechanical Bottom View.......................................................................................64
FIGURE 19 TTD Mechanical Bottom View.......................................................................................64
FIGURE 20 Crusoe Processor and TTD Mounting Holes ..................................................................65
FIGURE 21 TTD Over the Crusoe Processor .....................................................................................65
FIGURE 22 TTD In Place Over the Crusoe Processor........................................................................66
FIGURE 23 Bottom of PC Board, Screws for TTD ............................................................................66

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TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
Confidential Information—NDA Required 11
Overview
This design guide describes the specific details of a notebook PC motherboard design for the Crusoe™
Processor Model TM5400/TM5600 (hereafter known as TM5400/TM5600).
The core block diagram (see Figure 1) shows the major elements of a design that connect to a Transmeta
TM5400/TM5600 Processor. All connectivity, with a few exceptions, between the processor and other core
elements has been shown. Special considerations and signals not shown in the diagram are described in the
text. TM5400/TM5600 Reference Schematics that show detailed electrical connectivity are available. A full
description of the schematics is provided in this text. The description at the block diagram level is intended
to provide a broad overview of processor design issues. For specific details about the TM5400/TM5600
reference design see the descriptions of the schematics in Chapter 5, Crusoe Processor Reference Schematics
Description. Note that schematics describe both the TM3200 and TM5400/TM5600 processors.
These are some of the terms used in this book:
SUSPEND_STATUS Status output from the south bridge to signal that a power suspend state is
being entered. (SUS_STAT# from the Intel PIIX4 and SUSPENDJ from the
ALI M1535)
STR_CTL Suspend to RAM control signal output from power management section of
south bridge. (SUSB# from the Intel PIIX4 and OFF_PWR2 from the ALI
M1535).
STD_CTL Suspend to disk control signal output from the power management section
of south bridge. (SUSC# from the Intel PIIX4 and OFF_PWR3 from the
ALI M1535).
STR Suspend to RAM power down state. In this power management state,
system state is preserved in RAM while power to the processor is removed.
(RAM remains powered on in self-refresh mode). AKA Power state S3.
STD Suspend to disk power down state. In this power management state, system
state is preserved in the hard disk and power is off to the rest of the system
(including RAM). AKA power state S4.
V_3 3.3V power supply, always on.
V_3S 3.3V power supply, switched. This supply is turned off during STR and STD
power down states.

October 13, 2000 PreliminaryInformation TM5400/TM5600 System Design Guide
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TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
Confidential Information—NDA Required 13
Chapter 1
System Block Diagram
FIGURE 1 Core System Block Diagram
The TM5400/TM5600 includes both the CPU and the North Bridge functionality. To a motherboard
designer, this means that the processor looks very much like a north bridge. The TM5400/TM5600
supports two DRAM interfaces, one for DDR (Double Data Rate) SDRAMs (CD DRAM port), and the
other for regular SDRAMs (DI DRAM port). On the TM5400/TM5600, designers can choose to use
either SDRAM interfaces, together or independently, depending on their design’s cost and performance
requirements.
In the diagram, note how the power signals that feed the component are listed in each block. This helps the
reader to identify suspend and switched power distribution to core components. Descriptions of each supply
are described in Power Supply Requirements on page 14.
The major elements shown in the block diagram are as follows:
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To Rest Of Motherboard
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TM3200/TM5x00 System Block Diagram
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Transmeta Corp.
Confidential
NDA Required
06/08/00
TM3200/TM5x00 Processor
V_VDDIO25, V_3S, VDD_CORE
CMS CD Port DDR
SDRAM
V_DDRCORE, V_25
DI Port SDR SDRAM
V_3
CPU CORE Power
Supply
Vout = VDD_CORE,
PWRGD_CORE
Memory Power
Supply
Vout = V_25, V25_S
Transmeta Debug
Connector A (30 pin)
Transmeta Debug
Connector B (24 pin)
(User configurable pins)
Temp
Sensor
(I2C)
V_3S
8Mbit
Serial
CMS Flash
V_3S
2k-bit
Serial
Mode Bit
ROM
V_3S
Series Termination
DIODE_CATHODE
DIODE_ANODE
SROM_SCLK,
SROM_SOUT,
SROM_SIN,
SROM_CS[1:0]
CFG_SRDATA,
CFG_SRCLK
SUSPEND_STATUS
Quick
Switch
Isolation
V_5
CD_DQ[63:0], CD_A[12:0], CD_DQS[7:0],
CD_BA[1:0], CD_CS#[3:0],
CD_CLKA/A#, CD_CLKB/B#, CD_RAS#,
CD_CAS#, CD_WE#
CD_CKE[1:0]
Series Termination
SUSPEND_STATUS
Quick
Switch
Isolation
V_5
SD_DQ[63:0], SD_A[12:0], SD_DQMB[7:0],
SD_CS#[7:0], SD_BA[1:0], SD_CAS#,
SD_RAS#, SD_WE#, SD_CLK[7:0]
SD_CKE[3:0]
DI SD
interface
signals
P_AD[31:0]
SUSPEND_STATUS (from
South bridge)
EPROMA[2:0] (optional)
P_C/BE#[3:0]
P_CLKRUN#, P_DEVSEL#, P_FRAME#
P_GNT#[5:0]
P_HOLDA#
P_HOLD#
P_IRDY#, _P_LOCK#, P_PAR
RESET# P_PCLK
P_PERR#, P_STOP#, P_TRDY#
P_REQ#[5:0]
P_SERR#
STD_CTL
STR_CTL
POWERGOOD
P_FERR#
IGNNE#, INIT#, INTR, NMI, SMI#
S_SCLK,
S_SDATA (I2C
interface)
DEBUG_INIT
(DOCKING),
NM_DEBUG_INIT
(RNMI)
CLKIN, STPCLK#, SLEEP#
JTAG (TCK, TDO,
TDI, TMS,
TRST#)
P_PCI_RST#
RESET#
SYS_RST# -
connect to system
level reset
STR_CTL
STD_CTL
to south
bridge
Temp
Alert to
South
Bridge
all System POWERGOOD signals
(wire ORd)
DI SDRAM
DELAY
LOOP
{S_CLKIN,
S_CLKOUT}
POWERGOOD
VRDA[4:0] (TM160 only)
CD DDR interface on
TM5400 ONLY.
CD interface
signals
DI interface
signals
(TM5400/TM5600 only)
1

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• CD Port DDR SDRAM. Can support up to 2 banks of DDR DRAMs in various configurations of
64Mbit, 128Mbit, or 256Mbit devices.
• DI Port SDR SDRAM. The TM5400/TM5600 can support up to 4 banks of various configurations of
64Mbit, 128Mbit or 256Mbit devices.
• The CPU core switched mode high efficiency power supply.
• The 2.5V power supplies for the I/O power pins on the DDR SDRAMs and TM5400/TM5600 DDR
interface. On the TM3200, connect IOVDD25 and C_VREF to VDDCORE.
• The Thermal Sensor. This connects to a thermal sensing diode built into the processor.
• The 2Kbit Mode Bit SROM. System dependent configuration options vital to proper chip operation
are stored in this device and read by the processor at boot time.
• The 1Mbyte serial flash ROM for CMS. This is optional but recommended. CMS is stored in this
device. Other options for CMS code (such as sharing BIOS ROM) are described in the text.
• The Transmeta Debug Module (TDM) connector. This adds some low level debug support to facilitate
in design bring up as well as connectivity to the Transmeta ICE for software development.
• SDRAM Quick Switch Isolation. These are used to ensure that CKE signals to the SDRAMs remain
stable during processor power transitions. Since the Crusoe processor does not have a suspend-power
well, output signals are undefined during power transitions and subject to glitch.
• There are several elements and signals not shown but are described in the text below.
1.1 Power Supply Requirements
The block diagram shows the power supplies for each of the major components. The power source for all
notebook computers is either a battery (< 20V) or a DC wall adapter of a comparable voltage. An
intelligent switching mechanism is needed to create a stable V_DC or V_SOURCE that is used to supply
the regulators that generate system voltages.
The power supply network must be capable of generating the following supplies for the system:

TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
Confidential Information—NDA Required 15
The block does not show the supply that generates V_3, V_3S, V_5, and V_5S.
NOTE All power supplies to the processor must be powered on at the same time. All supplies must have similar
switch on and off characteristics within 10ms of each other.
Current requirements of each supply should be calculated on a per design basis.
There are several ways to design a power supply that can accomplish the above requirements. See the
Reference Schematics for an example of the supplies.
Power supply connections made to each system block are discussed within the individual block discussions.
TABLE 1 Power Supply Requirements
Power Supply Description
V_3 3.3V that is valid for all power states except for Suspend to Disk(STD)/Soft
off (SOFF) states (controlled by STD_CTL Power Management control
signal)
V_3S 3.3V Switched that is valid for all states except Suspend to RAM (STR) and
STD/SOFF (controlled by STR_CTL)
V_25 2.5V that is valid for all power states except for STD/SOFF ( controlled by
STD_CTL)
V_25S 2.5V Switched that is valid for all power states except for STR and STD/
SOFF (controlled by STR_CTL)
V_5 5V that is valid for all power states except STD/SOFF (controlled by
STD_CTL)
V_5S 5V Switched that is valid for all power states except STR and STD/SOFF
(controlled by STR_CTL).
VDD_CORE The TM5400/TM5600 has VRDA pins which can be connected to the
VDD_CORE regulator to do dynamic power management.
POWERGOOD_CORE Reset type signal that is the wire OR of the POWERGOOD signals from
each of the system supplies. Signal is valid when all of the system voltages are
stable.

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1.2 Description of Elements in System Block Diagram
1.2.1 Processor
PCI and PC Compatibility
PCI and PC CompatibilityPCI and PC Compatibility
PCI and PC Compatibility
• The PCI interface is 33MHz, 3.3V. The arbiter supports five REQ/GNT pairs. CLKRUN is
supported.
• The PCC (PC compatibility) signals are used in communication with the south bridge. These include
INIT, NMI, SMI, STPCLK, IGNNE, FERR, CPURST, INTR
Power Supply
Power SupplyPower Supply
Power Supply
The processor uses V_25S for IOVDD25 (2.5V used for CD interface I/O), V_3S for IOVDD (I/O supply
for all 3.3V pins), and VDD_CORE for CVDD (variable core voltage).
See power supply layout and decoupling section for recommendations.
1.2.2 CD DDR SDRAM
The CD DDR SDRAM port is only supported on the TM5400/TM5600.
The TM5400/TM5600 CD memory port supports 64Mbit, 128Mbit, or 256Mbit DDR SDRAM devices.
It is capable of running at extremely fast rates (see processor spec for details). The frequency at which DDR
is capable of running depends on several factors. Loading is critical and it is recommended that only 1 bank
of x16 bit devices be used to minimize load count. Also, it is not recommended to use DDR memory on a
DIMM or other expansion method since this can load the signals too much. The interface is capable of 2
banks of DDR memory and, although the interface can function with more loading than recommended, it
will be at the cost of speed and performance. The recommended configuration, again, is 4 devices of x16 bit
memory, soldered to the PC board incorporating the layout guidelines described in the Layout
Considerations part of this document.
Clock enable isolation during power down states
Clock enable isolation during power down statesClock enable isolation during power down states
Clock enable isolation during power down states
The CD_CKE[] clock enable signals need to be isolated between the TM5400/TM5600 and the SDRAM.
This is because power states exist where the TM5400/TM5600 is powered down and the SDRAM remains
powered (STR). The TM5400/TM5600 does not have a suspend-power well and, like any CMOS
circuitry, the outputs are undefined for short periods of time during power transitions. It is likely that all
the signals glitch as power is applied or removed from the chip. If the clock enable signal on the SDRAM
remains at a stable state, which prevent activity within the SDRAM during power transitions, the data
integrity is ensured. The SUSPEND_STATUS signal from the south bridge remains asserted while in STR

TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
Confidential Information—NDA Required 17
mode and is therefore used to control the isolation. It is recommended that a Quicklogic QS3257 quick
switch MUX or similar part be used. The output should MUX between a pull-down and the CD_CKE[]
signal from the TM5400/TM5600; controlled by SUSPEND_STATUS. See TM3200/TM5400/TM5600
Reference Schematics for example circuit.
Signal termination
Signal terminationSignal termination
Signal termination
Series termination is recommended on all signals. Impedance should be calculated per specific designs. See
Reference Schematics for example termination.
Power Supply
Power SupplyPower Supply
Power Supply
The VDDIO25 power supply pins of the DDR memory are connected to V_25. Currently, there are 2
types of DDR SDRAM that operate from different CORE voltages. V_DDRCORE should be connected
to either V_25 for 2.5V or V_3 for 3.3V depending on the type of DDR used in the design.
Connect the TM5400/TM5600 VDDIO25 to V25S. The CD interface for a TM5400/TM5600 has a
C_VREF input which requires VDDIO25/2. This should be generated with a 1% voltage divider from
V25S as in the Reference Schematics.
1.2.3 DI SDR SDRAM
NOTE DI memory termination values have changed. Use 22 ohms on data lines, 10 ohms on addr/control signals.
PCB trace impedance of all signals should be 60 ohms. See DI PCB Layout Guidelines on page 27.
The TM5400/TM5600 DI single data rate SDRAM port is very similar to the CD port but less restrictive
since the clock rates are lower. The frequency at which the DI port is run is dependent upon the loading so
care must still be taken to ensure that it is minimized.
The TM5400/TM5600 DI port supports only 4 banks of SDRAM. There are 4 clocks and 2 clock enables.
Recommended Configurations
Recommended ConfigurationsRecommended Configurations
Recommended Configurations
Timing is the main consideration in DI SDRAM selection. In order to operate at the highest speeds, it is
recommended that only homogeneous solutions of either socketed DIMM memory or soldered down
memory be used. When using DIMMs, it is recommended that the memory boards use x16-bit devices to
lower the overall device count and signal loading. Also, it is recommended that only a maximum of 2
DIMM slots be used to meet high speed loading requirements and also retain compatibility with Crusoe
processors.

October 13, 2000 PreliminaryInformation TM5400/TM5600 System Design Guide
18 Confidential Information—NDA Required
Bank Selection
Bank SelectionBank Selection
Bank Selection
The Crusoe architecture forces CMS memory to be in the highest physical addresses. The banks are paired
to support up to 2 DIMMs on the TM5400/TM5600. If the permanent memory in the system is soldered
down, use S_CS#[2]. If a DIMM is used, connect S_CS#[3:2] to it.
Signal Delay Loop
Signal Delay LoopSignal Delay Loop
Signal Delay Loop
On the SDR interface, the clock output named S_CLKOUT feeds back to the input named S_CLKIN.
The propagation delay of this feedback signal is used to adjust the setup and hold time of SDR read data. It
should be terminated just like the other SDR clocks: with a 33 ohm series resistor at the source. The total
propagation delay of this signal includes the portion before and after the series resistor. That total should be
equal to the sum of the average data line length and the average clock line length.
Clock Enable Isolation During Power Down States
Clock Enable Isolation During Power Down StatesClock Enable Isolation During Power Down States
Clock Enable Isolation During Power Down States
The S_CKE#[] clock enable signals need to be isolated between the processor and the SDRAM. This is
because power states exist where the processor is powered down and the SDRAM remains powered (STR).
The processor does not have a suspend-power well and, like any CMOS circuitry, the outputs are undefined
for short periods of time during power transitions. It is likely that all the signals glitch as power is applied or
removed from the chip. If the clock enable signal on the SDRAM remains at a stable state, which prevent
activity within the SDRAM during power transitions, the data integrity is ensured.
The SUSPEND_STATUS signal from the south bridge remains asserted while in STR mode and is therefore
used to control the isolation. It is recommended that a Quicklogic QS3257 quick switch MUX or similar
part be used. The output should MUX between a pull-down and the S_CKE#[] signal from the processor;
controlled by SUSPEND_STATUS. See the Core Reference Schematics for example circuit.
Signal Termination
Signal TerminationSignal Termination
Signal Termination
Series termination is recommended on all signals. Impedance should be calculated per specific design. See
the Reference Schematics for termination example.
Miscellaneous Notes
Miscellaneous NotesMiscellaneous Notes
Miscellaneous Notes
If DIMMs are used, be sure to connect serial presence detect bus to the south bridge (not shown).
All SDRAM power supplies should be connected to V_3 (controlled by STD_CTL).
8Mbit Serial CMS Flash
8Mbit Serial CMS Flash8Mbit Serial CMS Flash
8Mbit Serial CMS Flash
Since the Crusoe processors are hybrids that uses a blend of hardware and software to emulate an x86
processor, the hardware requires a serial flash memory device where the CMS (Code Morphing Software) is
stored. CMS needs 1MB of memory in its compressed state. The SROM interface has all the signals needed
to interface to 2 manufacturer’s serial flash ROM devices (Macronix and Atmel). There is no standardized

TM5400/TM5600 System Design Guide Preliminary Information October 13, 2000
Confidential Information—NDA Required 19
format for serial flash devices at the time of the processor’s design, so the format that was common to these
manufacturers was selected as the interface.
To date, Atmel has up to 8Mbit devices and Macronix has up to 4Mbit devices. If using a single 8Mbit
device, only one chip select is needed, else, both are used to interface to the memory.
See the Reference Schematics for circuit example using Atmel 8Mbit device.
The serial flash uses V_3S power supply since it needs to be powered off when the processor is off.
2kb Mode Bit ROM
2kb Mode Bit ROM2kb Mode Bit ROM
2kb Mode Bit ROM
Crusoe processors use a 2-wire serial interface to download the Configuration Mode bits from this device at
boot-up. The Configuration Mode bits instruct the CPU on several important boot and initialization
options.
The contents of the mode-bit ROM are read into the processor at power-on, configuring the processor to
begin execution with optimal performance timings over a large range of system operating configurations.
Compensating for process variation device sensitivity for current TM5400/TM5600 processors requires the
use of the external mode-bit ROM with a particular mode-bit parameter configuration that is slightly
different than the default parameters hard-wired into the processors. Use of the external mode-bit ROM
with the mode-bit parameters described in this document is required for guaranteed operation of all current
TM5400/TM5600 production parts. For more information, see Mode Bit ROM Settings on page 40.
Currently, the only approved part for use as a Config Mode bit SROM is Microchip Semiconductors'
93LC56B 128x16 2kb serial flash ROM.
This device is powered from V_3S.
Write-Protect PLD addition to CMS Serial Flash ROM
Write-Protect PLD addition to CMS Serial Flash ROMWrite-Protect PLD addition to CMS Serial Flash ROM
Write-Protect PLD addition to CMS Serial Flash ROM
A 22LV10 PLD is added to intercept the SROM_CS[1:0]# signals to the serial Flash SROM device(s).
The PLD intercepts write cycles to the device when writes are not authorized (controlled by a GPIO pin
from the south bridge chip). This addition is required for all systems using serial Flash ROM for CMS
storage; systems using the parallel ROM for CMS storage do not require a PLD. For more information,
see Serial Flash Write Protection Circuit on page 31.
Core Temperature Sensor
Core Temperature SensorCore Temperature Sensor
Core Temperature Sensor
This device connects to the DIODE_CATHODE and DIODE_ANODE pins of the processor. The
temperature sensor should be I2C compatible to connect to south bridge SMBUS or similar. Also, connect
temp sensor ALERT# signal to south bridge.
See the Reference Schematics for example device and circuit.
This device is powered from V_3S.

October 13, 2000 PreliminaryInformation TM5400/TM5600 System Design Guide
20 Confidential Information—NDA Required
TDM Debug Connection
TDM Debug ConnectionTDM Debug Connection
TDM Debug Connection
The Transmeta Debug Module (TDM) communicates to the target through two, high density Flex cables;
TDCA (30pin) and TDCB (options 24pin user connection). The TDCA is shown with it’s connections to
the core system. See the TDM spec for more information on TDCB or see the Reference Schematics for an
example of how TDCA connects and how TDCB can be used.
The TDM and the debug connection is used for:
•FlashingCMSROM
•FlashModeBitROM
• Connecting the Transmeta ICE
•Debugging
See diagram below for pinout and signal descriptions.