Transmeta Crusoe TM5500 Guide

TM5500/TM5800
System Design Guide
July 17, 2002

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Transmeta Corporation
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Copyright © 2001-2002 Transmeta Corporation. All rights reserved.
July 17, 2002
2
TM5500/TM5800 System Design Guide
Crusoe™ Processor Model TM5500/TM5800
System Design Guide
Revision 1.3
Revision History:
1.0 July 2, 2001 - first release
1.1 December 6, 2001 - updated schematics, reorganized and added new information, misc corrections
1.2 June 17, 2002 - changed DDR interface spec to one bank only, removed “Preliminary” mark
1.3 July 17, 2002 - updated MAX1718 core power supply example, removed ISL6211 and FAN5250 examples

July 17, 2002
3
Table of Contents
List of Tables ..........................................................................................................................................5
List of Figures .........................................................................................................................................7
Chapter 1 Introduction and Naming Conventions ................................................................................................9
1.1 Overview.....................................................................................................................................9
1.2 Reference Documents ..............................................................................................................10
1.3 Naming Conventions.................................................................................................................10
1.3.1 Power Management Mode Terms ..............................................................................11
1.3.2 Power Network Names...............................................................................................12
1.3.3 Signal Names .............................................................................................................12
Chapter 2 Example System Block Diagram and Schematics ............................................................................13
2.1 System Block Diagram..............................................................................................................13
2.2 Processor Schematics ..............................................................................................................15
Chapter 3 Processor Power Supplies and Power Management ........................................................................21
3.1 Power Supplies.........................................................................................................................21
3.1.1 Core Power Supply Requirements ............................................................................22
3.1.2 VRM Core Power Supply Example.............................................................................25
3.1.3 PLL Power Supply .....................................................................................................30
3.1.4 I/O Power Supplies.....................................................................................................33
3.1.5 Decoupling Capacitors................................................................................................34
3.2 Power Supply Sequencing .......................................................................................................35
3.2.1 Power Sequencing Requirements ..............................................................................35
3.2.2 Power Sequencing Circuit Examples..........................................................................36
3.3 Power Supply Voltage Supervisor.............................................................................................38
3.4 POWERGOOD Block Diagram Example..................................................................................40
3.5 State Transition Timing Requirements......................................................................................42
Chapter 4 DDR Memory Design ............................................................................................................................51
4.1 DDR Memory Interface .............................................................................................................51
4.2 Clock Enable Isolation...............................................................................................................52
4.3 Signal Termination....................................................................................................................52
4.4 DDR Reference Voltage............................................................................................................53
4.4.1 DDR Reference Voltage Noise Filter Circuit...............................................................53
4.5 DDR Memory Interface Design Guidelines ...............................................................................54
4.6 PCB Placement and Routing Example .....................................................................................55
4.7 DDR SDRAM Schematics.........................................................................................................59
Chapter 5 SDR Memory Design ............................................................................................................................65
5.1 SDR Memory Interface..............................................................................................................65

July 17, 2002
4
Table of Contents
5.2 SDR Memory Interface Design Guidelines................................................................................66
5.2.1 Bank Selection............................................................................................................66
5.2.2 Clock Enable Isolation During Power-down States.....................................................67
5.2.3 Signal Termination......................................................................................................67
5.2.4 Miscellaneous Notes...................................................................................................67
5.3 SDR SDRAM Layout Notes.......................................................................................................67
5.3.1 SDR SDRAM Memory Interface Timing......................................................................67
5.3.2 Example Design Strategy............................................................................................68
5.3.3 Write Timing ...............................................................................................................69
5.3.4 Read Timing................................................................................................................70
5.3.5 Uncertainty in the Feedback Calculation.....................................................................71
5.3.6 Using Soldered-down Memory....................................................................................71
5.3.7 Recommended Design Procedure..............................................................................76
5.3.8 Design Example..........................................................................................................77
5.4 SDR SDRAM Schematics .........................................................................................................77
Chapter 6 System Design Considerations ...........................................................................................................83
6.1 Clocking ....................................................................................................................................83
6.2 System Reset ............................................................................................................................86
6.3 Signal Pull-ups and Pull-downs.................................................................................................87
6.4 Mode-bit ROM ..........................................................................................................................89
6.5 Code Morphing Software ROM .................................................................................................91
6.5.1 Serial Flash ROM Interface.........................................................................................91
6.5.2 Serial Flash ROM Write Protection Circuit..................................................................93
6.5.3 Combined BIOS/CMS Parallel ROM Interface............................................................96
6.6 Southbridge ...............................................................................................................................98
6.6.1 Qualified Southbridge Devices....................................................................................98
6.6.2 Using CLKRUN...........................................................................................................98
6.6.3 Southbridge Schematics .............................................................................................98
6.7 Thermal Design .......................................................................................................................103
6.8 Thermal Diode and Thermal Sensor ......................................................................................103
6.8.1 Thermal Sensor Circuit .............................................................................................103
6.8.2 Thermal Sensor Issues .............................................................................................104
6.8.3 Thermal Sensor Layout.............................................................................................104
6.8.4 Thermal Sensor Example Schematic........................................................................105
6.9 TDM Debug Interface Connection...........................................................................................107
Chapter 7 PCB Layout Guidelines ......................................................................................................................111
7.1 PCB Design Layout.................................................................................................................111
7.2 Example PCB Fabrication Notes.............................................................................................112
7.3 Board Design Guidelines.........................................................................................................113
7.3.1 Printed Circuit Board Stackup ..................................................................................113
7.3.2 Allegro Standard Spacing Constraints .....................................................................113
7.3.3 Allegro Extended Spacing Constraints .....................................................................114
7.3.4 Allegro Extended Physical (Lines/Vias) Constraints ................................................115
7.3.5 Allegro Extended Electrical (Lines/Vias) Constraints ...............................................115
7.4 Footprint and Pin Escape Diagram .........................................................................................116
Appendix A System Design Checklists .................................................................................................................117
Appendix B Serial Write-protection PLD Data .......................................................................................................123
Index .....................................................................................................................................................129

July 17, 2002
5
List of Tables
Table 1: Supported ACPI Processor States ......................................................................11
Table 2: Supported ACPI System States...........................................................................11
Table 3: Power Net Naming Conventions..........................................................................12
Table 4: Signal Naming Conventions ................................................................................12
Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors..................22
Table 6: Default Power-on Start Voltage VRDA (VID) Output Codes................................23
Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM...............................24
Table 8: MAX1718 Core Power Supply Output Control Selector ......................................25
Table 9: MAX1718 DSX Voltage Configuration.................................................................26
Table 10: Power Supply Sequencing Timing Specifications................................................35
Table 11: DDR SDRAM Memory Configurations.................................................................51
Table 12: SDR SDRAM Memory Configurations.................................................................65
Table 13: SDR SDRAM Interface Device Specifications.....................................................68
Table 14: Write Timing Compensation ................................................................................69
Table 15: Signal Pull-up/Pull-down Requirements ..............................................................87
Table 16: PLD Pinout...........................................................................................................94
Table 17: Recommended Eight Layer PCB Stackup.........................................................113
Table 18: Standard Spacing/Line/Via Constraints ............................................................113
Table 19: Extended Global Spacing/Line/Via Constraints ................................................114
Table 20: Extended Physical Constraints .........................................................................115
Table 21: Extended Electrical Constraints ........................................................................115

July 17, 2002
6
List of Tables

July 17, 2002
7
List of Figures
Figure 1: Example Schematic Naming System...................................................................11
Figure 2: Example System Block Diagram .........................................................................13
Figure 3: PLL / Processor Core Voltage Tracking Requirement.........................................30
Figure 4: Power Supply Sequencing...................................................................................35
Figure 5: Recommended DDR Reference Voltage Circuit with Ferrite Bead Noise Filter ..53
Figure 6: Recommended 4-Device DDR Memory Chip Placement....................................55
Figure 7: Recommended 4-Device DDR Memory Signal Routing - Top Layer...................56
Figure 8: Recommended 4-Device DDR Memory Signal Routing - Internal Layer.............57
Figure 9: Recommended 4-Device DDR Memory Signal Routing - Bottom Layer..............58
Figure 10: Physical SDRAM Configurations .........................................................................68
Figure 11: Read Timing Compensation ................................................................................70
Figure 12: Adjustment of CLKIN Delay.................................................................................71
Figure 13: Optimum Placement and Routing........................................................................72
Figure 14: Sub-optimal Placement........................................................................................72
Figure 15: Data Structure Diagram.......................................................................................73
Figure 16: Address Line Structure Diagram..........................................................................74
Figure 17: Clock Line Structure Diagram..............................................................................74
Figure 18: Data Mask Structure Diagram .............................................................................75
Figure 19: Clock Enable Structure Diagram .........................................................................75
Figure 20: System Reset Diagram........................................................................................86
Figure 21: Schematic Diagram of Serial Flash Write-protection PLD in System ..................95
Figure 22: Recommended CLKRUN Circuit .........................................................................98
Figure 23: Transmeta Debug Connector (TDCA)...............................................................108
Figure 24: Mechanical Footprint .........................................................................................116
Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map.................................................124
Figure 26: Write Protection TSSOP-24 CUPL Source Code..............................................125

July 17, 2002
8
List of Figures

July 17, 2002
9
Chapter 1
Introduction and Naming
Conventions
1.1 Overview
This design guide is organized into the following sections:
•Introduction and Naming Conventions (this chapter) introduces the conventions used in this document,
including possible differences between hardware names for power supplies, pins, etc. and the reference
schematics used throughout the document.
• Chapter 2, Example System Block Diagram and Schematics presents the Crusoe TM5500/TM5800
processor in the context of a block diagram that shows necessary components and their connections.
The reference schematic for the processor itself is also provided.
• Chapter 3, Processor Power Supplies and Power Management describes the power supply network in
detail.
• Chapter 4, DDR Memory Design provides design guidelines and layout requirements for incorporating
DDR SDRAM memory into a design.
• Chapter 5, SDR Memory Design provides design guidelines and layout requirements for incorporating
SDR SDRAM memory into a design.
• Chapter 6, System Design Considerations describes a variety of design issues, including clocking, reset,
ROM interfaces, signal pull-up/pull-down requirements, thermal sensor, and southbridge interfaces.
• Chapter 7, PCB Layout Guidelines discusses physical issues related to memory and component
interfaces, power supplies, signal integrity, mounting and spacing constraints, tolerances and fabrication
guidelines, and footprint and pin escape diagrams.
• Appendix A, System Design Checklists includes cross-referenced checklists to follow while designing a
system.
• Appendix B, Serial Write-protection PLD Data includes the JEDEC fuse map and CUPL source code for
the write-protection PLD required for serial-ROM Code Morphing software placement. This issue is
described in Serial Flash ROM Write Protection Circuit on page 93 in Chapter 6, System Design
Considerations.
•AnIndex is also included.

July 17, 2002
10
Introduction and Naming Conventions
1.2 Reference Documents
The following documents are available from Transmeta for use in conjunction with this design guide. Some of
these documents are extensively referenced in the design guide, and should be consulted as specified in the
text.
• TM5500/TM5800 Data Book
• TM5500/TM5800 Package Specifications and Manufacturing Guide
•TM5500/TM5800 Thermal Design Guide
•TM5500/TM5800 Development and Manufacturing Guide
•TM5500/TM5800 BIOS Programmer’s Guide
•TM5500/TM5800 IBIS Models
•TM5500/TM5800 BSDL file
• TM5500/TM5800 Code Morphing Software Release Notes
• TM5500/TM5800 Technical Bulletins and Errata documents
1.3 Naming Conventions
Power supply and signal names used in the Data Book and other hardware-specific materials can be different
from those used on the reference schematics. This section shows the terms used in the System Design
Guide and the reference schematics, and correlates them with the hardware-specific names used elsewhere.
In general, the hardware symbols in the schematics show the hardware names for each item (signal or power
line). The alphanumeric marker at the connection between symbol and line is the ball number, described in
detail in the Data Book. The line itself shows the schematic net name, i.e. the name that is used throughout
this document to refer to that net/signal/line.
Note
The block diagram and reference schematics included in this book offer general guidelines for integrating
TM5500/TM5800 processors into product designs. For detailed processor-specific information, consult the
reference documents listed below.

July 17, 2002
11
Introduction and Naming Conventions
The following diagram shows how to locate the various schematic names:
1.3.1 Power Management Mode Terms
The power management modes supported by TM5500/TM5800 processors are discussed in detail in Chapter
1, Functional Interface Description, in the Data Book. The following tables show the ACPI power and sleep
states supported by TM5500/TM5800 processors and referenced in this document.
Figure 1: Example Schematic Naming System
Table 1: Supported ACPI Processor States
ACPI State ACPI State Name Description
C0 Normal Active power state with processor executing instructions.
C1 Auto Halt Sleep state entered by processor executing HALT instruction.
C2 Quick Start Sleep state requiring chipset/hardware support. This state is lower
power than C1.
C3 Deep Sleep Sleep state requiring chipset/hardware support. This state is lower
power than C2.
Table 2: Supported ACPI System States
ACPI State ACPI State Name Description
S0 Working Normal active state (not sleeping).
S1 Power-on Suspend Processor not executing instructions. Processor state and RAM
context maintained.
S3 Suspend-to-RAM
(STR)
Current processor state is suspended and stored in volatile RAM (that
is kept powered). Only _STR and _ALWAYS power supplies are
active.
pin name
ball number
schematic name

July 17, 2002
12
Introduction and Naming Conventions
Note that some terms must be combined for a full description of system state (e.g. Working/Auto Halt vs.
Working/Quick Start). For more details on ACPI states, see the ACPI specification.
For information on timing requirements between states, see State Transition Timing Requirements on
page 42. Power specifications for each of the supported power management modes are provided in Chapter
3, Electrical Specifications in the Data Book.
1.3.2 Power Network Names
Transmeta’s reference schematics use a standard naming convention for power supply nets, provided in the
table below.
1.3.3 Signal Names
Transmeta’s reference schematics call out many signals which may be named slightly differently in hardware-
oriented documents such as the Data Book. The following table illustrates the character conventions used in
the schematics:
S4 Suspend-to-Disk
(STD)
Current processor state is suspended and saved to non-volatile disk.
All power supplies except _ALWAYS are off.
S5 Soft Off System is turned off. All power supplies except _ALWAYS are off.
Table 3: Power Net Naming Conventions
Convention Description
V_name A switched voltage such as V_CPU_CORE, off during S3, S4, and S5
Vn_d_STR A voltage present in S3 (STR), off during S4 and S5
Vn_dA switched voltage at n.d volts, off during S3, S4, and S5
V_Nn_dA negative voltage at n.d volts, off during S3, S4, and S5
Vn_d_ALWAYS An always-on voltage, i.e. present in all ACPI sleep states
Table 4: Signal Naming Conventions
Character Description Example
# Denotes asserted low signals. Signal names without this suffix are
assumed to assert high.
LOWSIG#
.., : Used to separate elements in a list. EIGHTBITBUS[7..0]
D[7:0]
/ Can be used to separate multiple uses of a pin. USEA/USEB
[ ] Delineates bus name from element list. EIGHTBITBUS[7..0]
Table 2: Supported ACPI System States (Continued)
ACPI State ACPI State Name Description

July 17, 2002
13
Chapter 2
Example System Block Diagram
and Schematics
2.1 System Block Diagram
The block diagram below shows major elements of a TM5500/TM5800 processor-based system design.
Signals and bus interconnections are also shown. For detailed circuit design information, see the reference
schematics throughout this document (also available in OrCAD format from your Transmeta representative).
Figure 2: Example System Block Diagram
To Rest Of Motherboard
Crusoe Processor
V2_5, V3_3,
V_CPU_CORE, V_CPU_PLL
CPU Core
Power Supply
V_CPU_CORE
Memory
Power Supply
V2_5_STR, V3_3_STR
Transmeta Debug Connector A
(30-pin)
Temperature
Sensor
V3_3
8Mbit Serial
Flash for
CMS
2kbit Serial
Mode-Bit
ROM
Series Termination
SUSPEND#
DDR_CKE[1:0]
Series Termination
SUSPEND#
SDR_CKE[3:0]
SUSPEND#
EPROMA[2:1] (optional)
PCI_C/BE#[3:0]
PCI_CLKRUN#, PCI_DEVSEL#, PCI_FRAME#
PCI_IRDY#, PCI_LOCK#, PCI_PAR
CPU_RST#
CLK_PCI_TM
PCI_PERR#, PCI_STOP#, PCI_TRDY#
PCI_REQ#[5:0]
PCI_SERR#
SUSC#
SUSB#
PWRGOOD
PCI_FERR#
CPU_IGNNE#, INIT#, INTR, NMI, SMI#
CPU_CLK, CPU_STPCLK#, SUSPEND#
PCI_RST#
CPU_RST#
SYS_RST#
connect to system-level reset
Temp Alert
to
southbridge
all System POWERGOOD signals
(wire ORed)
POWERGOOD
VRDA[4:0]
DDR Interface Signals
SDR Interface Signals
PCI_AD[31:0]
PCI_GNT#[5:0]
PCI_HLDA#
PCI_HLD#
TDM_TCK,
TDO,TDI,TMS,
TRST#
SRCLK, SRDATA
SROM_SCLK,
SROM_SOUT,
SROM_SIN,
SROM_CS[1:0]
TDM_SCL
TDM_SDA
(Serial Debug
Bus interface)
DDR SDRAM
V2_5_STR
SDR SDRAM
V3_3_STR
SDR_DQ[63:0], SDR_A[12:0],
SDR_DQMB[7:0],SDR_CS#[3:0],
SDR_BA[1:0], SDR_CAS#,SDR_RAS#,
SDR_WE#, SDR_CLK[3:0]
DDR_DQ[63:0], DDR_A[12:0],
DDR_DQS[7:0],DDR_BA[1:0], DDR_CS#[3:0],
DDR_DQM[7:0]DDR_CLKA/A#, DDR_CLKB/B#,
DDR_RAS#,DDR_CAS#, DDR_WE#
DIODE_CATHODE
DIODE_ANODE
Transmeta Corp.
Confidential
NDA Required
06/04/2001
DEBUG_INIT
NM_DEBUG_INIT
High-Speed Bi-
Directional Level-
Translator Isolation
V5_0_ALWAYS
V3_3
V3_3
SDR SDRAM
Delay Loop
(SDR_CLKIN,
SDR_CLKOUT)
V5_0_ALWAYS
High-Speed Bi-
Directional Level-
Translator Isolation
1

July 17, 2002
14
Example System Block Diagram and
Schematics
TM5500/TM5800 processors include both core processor and northbridge functionality. For a motherboard
designer, this means the processor looks very much like a northbridge. TM5500/TM5800 processors support
two DRAM interfaces, one for Double Data Rate (DDR) SDRAMs and the other for Single Data Rate (SDR)
SDRAMs. Designers can choose to use either or both SDRAM interfaces, depending on their system cost
and performance requirements.
In the block diagram, note that power signals that feed each component are listed in the component’s block.
This helps to identify suspend and switched power distribution to each component. Descriptions of each
supply are described in Chapter 3, Processor Power Supplies and Power Management.
The major elements shown in the block diagram are outlined below:
•Processor Core Power Supply. The processor core high-efficiency switched-mode power supply. See
Chapter 3, Processor Power Supplies and Power Management.
•Memory Power Supplies. The power supplies for SDR and DDR SDRAM memory. See Chapter 3,
Processor Power Supplies and Power Management.
•DDR SDRAM Interface. The processor can support up to two identical banks of DDR SDRAMs in
various configurations of 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit devices. See Chapter 4, DDR
Memory Design.
•SDR SDRAM Interface. The processor can support up to four banks of SDR SDRAMs in various
configurations of 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit devices. See Chapter 5, SDR Memory
Design.
• SDRAM High-speed Bidirectional Level-translator Isolation. Signal isolation is used to ensure that
CKE signals to the SDRAMs remain stable during processor power transitions. Since the processor does
not have a suspend power well, output signals are undefined during power transitions and subject to
glitching.
•PCI Interface and PCC Signals. The PCI interface is 33 MHz, 3.3 V. The arbiter supports five REQ/GNT
pairs. CLKRUN is supported (see Using CLKRUN on page 98). PCC (PC compatibility) signals are used
for communication with the southbridge. See Southbridge on page 98.
•Code Morphing Software Serial Flash ROM. Code Morphing software is stored in this optional (but
recommended) 1 Mbyte device. See Serial Flash ROM Interface on page 91. Other options for Code
Morphing software code storage (such as sharing the BIOS ROM) are also described. See Combined
BIOS/CMS Parallel ROM Interface on page 96.
•Serial Flash Write-protection Circuit. If a serial flash ROM is used for Code Morphing software, a PLD
(programmable logic device) write-protection device must be added to the serial flash ROM circuit. See
Serial Flash ROM Write Protection Circuit on page 93.
•Mode-bit ROM (required). System-dependent configuration options vital to proper processor operation
are stored in this required 2 Kbit device and read by the processor at boot time. See Mode-bit ROM on
page 89.
•Thermal Sensor. An external thermal sensor is used in conjunction with a thermal sensing diode built
into the processor. See Thermal Diode and Thermal Sensor on page 103.
•Transmeta Debug Module (TDM) Interface. This adds some low-level debug support to facilitate in-
design bring-up, as well as connectivity to the Transmeta Virtual In-Circuit Emulator CE (TMVICE) for
software development. See TDM Debug Interface Connection on page 107.

July 17, 2002
15
Example System Block Diagram and
Schematics
2.2 Processor Schematics
The following pages show TM5500/TM5800 processor reference schematics.

A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
A
BasilThursday,November 29,2001
1 5
TM5800 DDR Interface
3940 Freedom Circle
Santa Clara, CA. 95054
[phone]
DOCUMENT#
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Corporation. All rights reserved.
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proprietaryinformationof Transmeta
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except inaccordance with applicable
agreements. This copyrightnoticedoes not
evidenceany actual orintended publication of
suchdocument. Pageof
Title:
DocumentNumber:
Size:
Revision:
Date:Author:
Project:
DDR_A6
DDR_DQ32
DDR_DQM6
DDR_DQ59 DDR_DQM2
DDR_DQ26
DDR_DQ60
DDR_DQ50
DDR_DQ28
DDR_DQ41
DDR_DQS1
DDR_DQ16
DDR_A5
DDR_DQ7
DDR_DQM5
DDR_DQS7
DDR_DQ48
DDR_DQ36
DDR_DQ13
DDR_DQS2
DDR_DQ42
DDR_DQ51
DDR_DQ6
DDR_A2
DDR_DQ10
DDR_A4
DDR_DQ52
DDR_DQ14
DDR_A1
DDR_DQ23
DDR_DQ0
DDR_DQ56
DDR_DQS6
DDR_DQ44
DDR_DQ43 DDR_A10
DDR_DQ15
DDR_A8
DDR_DQ57
DDR_DQ1
DDR_DQ24
DDR_DQ29
DDR_DQ30
DDR_A9
DDR_DQ35
DDR_DQ8
DDR_DQ27
DDR_A11
DDR_DQ47
DDR_DQM4
DDR_A0
DDR_DQ46
DDR_DQ33
DDR_DQ11
DDR_DQM7
DDR_DQ34
DDR_DQS3
DDR_DQ54
DDR_DQM3
DDR_DQ5
DDR_DQ4
DDR_DQ9
DDR_DQM0
DDR_DQ55
DDR_DQ45
DDR_DQ25
DDR_DQ12 DDR_DQS4
DDR_DQ58
DDR_DQ38
DDR_A3
C_VREF
DDR_DQS0
DDR_DQ21
DDR_A12
DDR_DQ31
DDR_DQ61
DDR_DQ39
DDR_DQ19
DDR_DQ18
DDR_DQ20
DDR_DQ53
DDR_DQ17
DDR_A7
DDR_DQ3
DDR_DQ63
DDR_DQ37
DDR_DQ2
DDR_DQM1
DDR_DQ62
DDR_DQ49
DDR_DQ22
DDR_DQS5
DDR_DQ40
DDR_DQ4_R
DDR_DQ41_R
DDR_DQ11_R
DDR_DQ48_R
DDR_DQ42_R
DDR_DQ10_R
DDR_DQ52_R
DDR_DQ28_R
DDR_DQ16_R
DDR_DQ61_R
DDR_DQ17_R
DDR_DQ9_R
DDR_DQ37_R
DDR_DQ27_R
DDR_DQ20_R
DDR_DQ53_R
DDR_DQ54_R
DDR_DQ56_R
DDR_DQ26_R
DDR_DQ32_R
DDR_DQ6_R
DDR_DQ5_R
DDR_DQ34_R
DDR_DQ36_R
DDR_DQ24_R
DDR_DQ58_R
DDR_DQ43_R
DDR_DQ57_R
DDR_DQ12_R
DDR_DQ40_R
DDR_DQ39_R
DDR_DQ1_R
DDR_DQ25_R
DDR_DQ63_R
DDR_DQ55_R
DDR_DQ13_R
DDR_DQ49_R
DDR_DQ33_R
DDR_DQ18_R
DDR_DQ44_R
DDR_DQ30_R
DDR_DQ62_R
DDR_DQ7_R
DDR_DQ29_R
DDR_DQ21_R
DDR_DQ46_R
DDR_DQ50_R
DDR_DQ59_R
DDR_DQ15_R
DDR_DQ23_R
DDR_DQ22_R
DDR_DQ31_R
DDR_DQ3_R
DDR_DQ14_R
DDR_DQ45_R
DDR_DQ35_R
DDR_DQ8_R
DDR_DQ19_R
DDR_DQ47_R
DDR_DQ38_R
DDR_DQ51_R
DDR_DQ0_R
DDR_DQ2_R
DDR_DQ60_R
CLK_DDRA_R
DDR_A11_R
DDR_A9_R
DDR_BA0_R
DDR_DQM3_R
DDR_CS0_R#
DDR_A10_R
DDR_DQS5_R
DDR_A0_R
DDR_A8_R
DDR_A5_R
DDR_A2_R
DDR_MWE_R#
DDR_DQS1_R
DDR_DQM5_R
DDR_A7_R
DDR_CS3_R#
DDR_A12_R
DDR_RAS_R#
DDR_A3_R
DDR_DQS0_R
DDR_DQS6_R
DDR_DQM7_R
DDR_BA1_R
DDR_DQM6_R
DDR_CAS_R#
DDR_DQS3_R
DDR_CKE_MUX1_R
DDR_A6_R
DDR_DQS7_R
DDR_CS2_R#
DDR_A1_R
DDR_DQM0_R
DDR_DQM1_R
DDR_DQM4_R
DDR_DQM2_R
DDR_DQS4_R
DDR_A4_R
DDR_CS1_R#
DDR_DQS2_R
DDR_CKE_MUX0_R
CLK_DDRB_R
CLK_DDRB_R#
CLK_DDRA_R#
DDR_RAS#
CLK_DDRB#
CLK_DDRADDR_DQ[63..0]
DDR_BA0
DDR_BA1
DDR_CAS#
DDR_DQS[7..0]
DDR_A[12..0]
DDR_CS2#
DDR_CKE_MUX0
CLK_DDRA#
DDR_CS1#
DDR_CS0#
DDR_MWE#
DDR_CKE_MUX1
CLK_DDRB
DDR_DQM[7..0]
DDR_CS3#
V2_5
RN12A 24
1 8
RN17B 24
2 7
RN1A 10
1 8
RN7C 24
3 6
RN22C 24
3 6
RN9B 24
2 7
RN14A 10
1 8
RN20C 24
3 6
RN3C 24
3 6
RN7B 24
2 7
RN22B 24
2 7
RN10B 24
2 7
RN18A 10
1 8
R9 10
1 2
RN6C 24
3 6
RN1B 10
2 7
RN17C 24
3 6
RN16D 10
4 5
RN20D 24
4 5
RN11D 10
4 5
RN14B 10
2 7
RN7D 24
4 5
RN20A 24
1 8
RN3A 24
1 8
RN6B 24
2 7
RN1D 24
4 5
RN13D 24
4 5
RN19C 24
3 6
RN25D 24
4 5
R8 10
1 2
RN2A 10
1 8
RN17D 24
4 5
RN11B 10
2 7
RN14C 10
3 6
RN16C 10
3 6
RN22A 24
1 8
RN9A 24
1 8
R3 10
1 2
RN5A 24
1 8
(PART 1 OF 5)
DDR
U1A
Crusoe BGA474
AD14
AE15
AD15
AE16
AC19
AB18
AB19
AA18
AA19
AA17
Y19
Y18
W19
W18
V19
V18
U19
U18
AB11
P18
N19
N18
M19
L19
L18
K16
M15
M16
M17
N15
N16
P16
T16
T17
U15
U16
V16
V17
W15
W16
Y15
Y16
Y17
AA15
AA16
AB14
AA13
AB13
AC13
AA12
AE13
AD13
AE14
AD19
AB16
AA11
AD18
AC18
P19
AB12
AD12
M18
P15
V15
K19
AE12
AE11
AD11
Y7
AE6
AB10
AA9
AC11
AA10
Y11
Y9
Y8
AD10
AD16
AE18
T19
R18
P17
T15
AC16
AA14
AD8
AE8
AD7
AE7
AD6
AC7
AB7
AA7
AB8
AA8
AE9
AC9
AB9
AE17
AD17
T18
R19
R15
R16
AB15
AC15
AE10
AD9
C_DQ4
C_DQ5
C_DQ6
C_DQ7
C_DQ10
C_DQ13
C_DQ12
C_DQ15
C_DQ14
C_DQ53
C_DQ16
C_DQ17
C_DQ18
C_DQ19
C_DQ20
C_DQ21
C_DQ22
C_DQ23
C_DQ63
C_DQ25
C_DQ26
C_DQ27
C_DQ28
C_DQ30
C_DQ31
C_DQ32
C_DQ33
C_DQ34
C_DQ35
C_DQ36
C_DQ37
C_DQ39
C_DQ40
C_DQ41
C_DQ42
C_DQ43
C_DQ45
C_DQ46
C_DQ47
C_DQ48
C_DQ49
C_DQ50
C_DQ51
C_DQ52
C_DQ54
C_DQ56
C_DQ57
C_DQ58
C_DQ59
C_DQ60
C_DQ1
C_DQ2
C_DQ3
C_DQ8
C_DQ55
C_DQ62
C_DQ9
C_DQ11
C_DQ24
C_DQ61
C_DQ0
C_DQ29
C_DQ38
C_DQ44
C_VREF
C_WE#
C_RAS#
C_CAS#
C_CKE1
C_CKE0
C_CLKB#
C_CLKB
C_CLKA#
C_CLKA
C_CS3#
C_CS2#
C_CS1#
C_CS0#
C_DQS0
C_DQS1
C_DQS2
C_DQS3
C_DQS4
C_DQS5
C_DQS6
C_DQS7
C_A0
C_A1
C_A2
C_A3
C_A4
C_A5
C_A6
C_A7
C_A8
C_A9
C_A10
C_A11
C_A12
C_DQMB0
C_DQMB1
C_DQMB2
C_DQMB3
C_DQMB4
C_DQMB5
C_DQMB6
C_DQMB7
C_BA0
C_BA1
RN2B 24
2 7
RN21A 24
1 8
RN8A 24
1 8
RN11C 10
3 6
RN12B 24
2 7
RN5D 24
4 5
RN19B 24
2 7
RN24D 24
4 5
RN2C 10
3 6
RN14D 10
4 5
RN11A 10
1 8
RN15C 24
3 6
RN16B 10
2 7
RN20B 24
2 7
RN6D 24
4 5
R4 10
1 2
RN2D 24
4 5
RN4A 24
1 8
RN1C 24
3 6
RN12C 24
3 6
RN4D 24
4 5
C1
0.1uF
12
RN15D 24
4 5
R10 10
1 2
R2
2.80K
1%
12
RN25B 24
2 7
RN15A 24
1 8
RN23C 24
3 6
R5 10
1 2
RN16A 10
1 8
RN5C 24
3 6
RN9D 24
4 5
RN25A 24
1 8
RN13C 24
3 6
RN12D 24
4 5
RN5B 24
2 7
RN19A 24
1 8
RN24B 24
2 7
R1
2.15K
1%
12
RN17A 24
1 8
RN4C 24
3 6
R6 10
1 2
RN21B 24
2 7
RN8B 24
2 7
RN23D 24
4 5
RN25C 24
3 6
RN13B 24
2 7
RN18C 10
3 6
RN10C 24
3 6
RN4B 24
2 7
RN15B 24
2 7
R7 10
1 2
RN7A 24
1 8
RN3D 24
4 5
RN21C 24
3 6
RN8C 24
3 6
RN24C 24
3 6
RN22D 24
4 5
RN10D 24
4 5
RN18D 10
4 5
RN10A 24
1 8
RN19D 24
4 5
RN23A 24
1 8
RN6A 24
1 8
RN9C 24
3 6
RN21D 24
4 5
RN3B 24
2 7
RN8D 24
4 5
RN23B 24
2 7
RN24A 24
1 8
RN13A 24
1 8
RN18B 10
2 7

A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
PLACE R11 CLOSE TO SOURCE, PROCESSOR BALL V6
TM5800 Design Guide
Custom
A
BasilThursday,November 29,2001
2 5
TM5800 SDR Interface
3940 Freedom Circle
Santa Clara, CA. 95054
[phone]
DOCUMENT#
Copyright (C)1995-2001 Transmeta
Corporation. All rights reserved.
This documentcontains confidentialand
proprietaryinformationof Transmeta
Corporation. It is not tobe disclosed orused
except inaccordance with applicable
agreements. This copyrightnoticedoes not
evidenceany actual orintended publication of
suchdocument. Pageof
Title:
DocumentNumber:
Size:
Revision:
Date:Author:
Project:
SDR_CLKOUT
SDR_CLKIN
SDR_DQ62_R
SDR_DQ1_R
SDR_DQ46_R
SDR_DQ20_R
SDR_DQ21_R
SDR_DQ24_R
SDR_DQ63_R
SDR_DQ53_R
SDR_DQ55_R
SDR_DQ41_R
SDR_DQ31_R
SDR_DQ0_R
SDR_DQ42_R
SDR_DQ12_R
SDR_DQ5_R
SDR_DQ39_R
SDR_DQ52_R
SDR_DQ47_R
SDR_DQ61_R
SDR_DQ7_R
SDR_DQ28_R
SDR_DQ48_R
SDR_DQ36_R
SDR_DQ18_R
SDR_DQ8_R
SDR_DQ23_R
SDR_DQ57_R
SDR_DQ50_R
SDR_DQ59_R
SDR_DQ60_R
SDR_DQ51_R
SDR_DQ15_R
SDR_DQ45_R
SDR_DQ26_R
SDR_DQ4_R
SDR_DQ34_R
SDR_DQ40_R
SDR_DQ17_R
SDR_DQ56_R
SDR_DQ38_R
SDR_DQ6_R
SDR_DQ10_R
SDR_DQ32_R
SDR_DQ54_R
SDR_DQ35_R
SDR_DQ37_R
SDR_DQ9_R
SDR_DQ29_R
SDR_DQ16_R
SDR_DQ14_R
SDR_DQ44_R
SDR_DQ33_R
SDR_DQ25_R
SDR_DQ43_R
SDR_DQ19_R
SDR_DQ49_R
SDR_DQ13_R
SDR_DQ30_R
SDR_DQ27_R
SDR_DQ11_R
SDR_DQ3_R
SDR_DQ2_R
SDR_DQ58_R
SDR_DQ22_R
SDR_CKE_MUX1_R
SDR_BA1_R
SDR_CS2_R#
SDR_A8_R
SDR_A10_R
SDR_CS0_R#
SDR_A5_R
SDR_A1_R
SDR_BA0_R
SDR_DQM2_R
SDR_DQM5_R
SDR_A0_R
CLK_SDR1_R
SDR_MWE_R#
NC_U1_K4
SDR_CAS_R#
NC_U1_K3
NC_U1_L5
SDR_A12_R
SDR_DQM6_R
SDR_DQM3_R
SDR_DQM1_R
CLK_SDR0_R
SDR_CS1_R#
CLK_SDR2_R
SDR_A3_R
SDR_A2_R
SDR_A4_R
SDR_RAS_R#
SDR_A9_R
SDR_DQM0_R
SDR_A11_R
NC_U1_K5
SDR_A7_R
SDR_A6_R
CLK_SDR3_R
SDR_CKE_MUX0_R
SDR_DQM4_R
SDR_DQM7_R
SDR_CS3_R#
SDR_MWE#
SDR_DQ14
SDR_DQ57
SDR_DQ37
SDR_DQ41
SDR_DQ3
SDR_DQ59
SDR_DQ34
SDR_DQ51
SDR_CAS#
SDR_DQ22
SDR_DQ58
SDR_A4SDR_DQ35
SDR_BA0
SDR_DQM0
SDR_DQ38
SDR_CS2#
SDR_DQ8
SDR_RAS#
SDR_DQ39
SDR_DQ45
SDR_DQ42
SDR_DQ33
SDR_DQ63
SDR_A5
SDR_A12
SDR_DQ20
CLK_SDR2
SDR_DQM6
SDR_DQ27
SDR_DQM1
SDR_DQ25
SDR_A7
SDR_DQ9
SDR_DQ31
SDR_DQ48
SDR_A11
SDR_DQ2
SDR_DQ62
SDR_DQ24
SDR_DQ26
SDR_DQ32
SDR_DQ0
SDR_DQ60
SDR_DQ4
SDR_DQ40
SDR_DQM5
SDR_DQ43
SDR_DQ52
SDR_DQM3
SDR_A6
SDR_DQ50
SDR_DQ47
SDR_DQ12
SDR_CS3#
SDR_DQM7
SDR_DQ15
SDR_DQ55
SDR_DQ46
SDR_DQ23
SDR_DQ53
SDR_DQ54
CLK_SDR3
SDR_A1
SDR_DQ11
SDR_DQ36
SDR_DQ44
SDR_DQ30
SDR_DQ21
CLK_SDR1
SDR_DQ7
SDR_DQ17
CLK_SDR0
SDR_DQM4
SDR_DQ49
SDR_DQ61
SDR_DQ18
SDR_A0
SDR_DQ1
SDR_CS1#
SDR_DQ56
SDR_DQM2
SDR_CKE_MUX0
SDR_DQ29
SDR_A8
SDR_DQ16
SDR_DQ5
SDR_DQ19
SDR_DQ28
SDR_DQ10
SDR_A2
SDR_DQ13
SDR_CS0#
SDR_A10
SDR_DQ6
SDR_CKE_MUX1
SDR_BA1
SDR_A3
SDR_A9
RN47A 33
1 8
RN45B 33
2 7
RN36A 33
8 1
RN43B 33
2 7
RN28A 33
1 8
RN31D 10
4 5
RN32B 33
2 7
RN36C 33
3 6
RN39B 10
2 7
RN33B 10
2 7
RN48B 33
2 7
RN27C 33
3 6
RN48C 33
3 6
RN45D 33
4 5
RN35B 33
2 7
RN44C 10
3 6
RN29C 33
3 6
RN40C 33
3 6
RN31C 33
3 6
RN39C 33
3 6
RN38B 10
2 7
RN33D 10
4 5
RN48D 33
4 5
RN27A 33
1 8
RN49C 33
3 6
RN43C 33
3 6
RN34C 33
3 6
RN47D 33
4 5
RN29B 33
2 7
RN42B 10
2 7
RN43A 33
1 8
RN30C 33
3 6
RN38A 33
1 8
RN38D 10
4 5
R13 22
1 2
RN46A 33
8 1
RN31B 10
2 7
RN28B 33
2 7
RN37D 10
4 5
RN45C 33
3 6
SDR
(PART 2 OF 5)
U1B
Crusoe BGA474
P3
N4
V5
P4
N5
M1
P1
N1
P2
N2
M2
K1
W5
AB4
AB5
AA5
Y5
AC4
AD3
AD2
AC2
AC1
AD1
AA4
AA3
Y4
Y3
W4
G4
G6
G5
E6
F5
D5
E5
D6
F4
F3
E3
E4
D4
B5
C5
C4
AA6
AC5
AD5
AD4
AE3
AE5
AE4
AE2
AB2
AB1
AA2
AA1
Y2
Y1
W2
W1
F1
F2
E1
D1
E2
C1
D2
B1
B2
B3
A4
A2
B4
A3
A5
C2 U1
U4
H4
H3
U5
U2
H2
H1
T4
T3
T1
T2
M3
M4
M5
L4
L5
K3
K4
K5
J2
J1
L2
L1
V4
AB6 V6
R5
P5
K2
S_A0
S_A1
S_A2
S_A3
S_A4
S_A5
S_A6
S_A7
S_A8
S_A9
S_A10
S_A11
S_DQ0
S_DQ1
S_DQ2
S_DQ3
S_DQ4
S_DQ5
S_DQ6
S_DQ7
S_DQ8
S_DQ9
S_DQ10
S_DQ11
S_DQ12
S_DQ13
S_DQ14
S_DQ15
S_DQ16
S_DQ17
S_DQ18
S_DQ19
S_DQ20
S_DQ21
S_DQ22
S_DQ23
S_DQ24
S_DQ25
S_DQ26
S_DQ27
S_DQ28
S_DQ29
S_DQ30
S_DQ31
S_DQ32
S_DQ33
S_DQ34
S_DQ35
S_DQ36
S_DQ37
S_DQ38
S_DQ39
S_DQ40
S_DQ41
S_DQ42
S_DQ43
S_DQ44
S_DQ45
S_DQ46
S_DQ47
S_DQ48
S_DQ49
S_DQ50
S_DQ51
S_DQ52
S_DQ53
S_DQ54
S_DQ63
S_DQ62
S_DQ61
S_DQ60
S_DQ59
S_DQ58
S_DQ57
S_DQ56
S_DQ55 S_DQMB0
S_DQMB1
S_DQMB2
S_DQMB3
S_DQMB4
S_DQMB5
S_DQMB6
S_DQMB7
S_CS0#
S_CS1#
S_CS2#
S_CS3#
S_CLK0
S_CLK1
S_CLK2
S_CLK3
S_CLK4
S_CLK5
S_CLK6
S_CLK7
S_CKE0
S_CKE1
S_BA0
S_BA1
S_CAS#
S_CLKIN S_CLKOUT
S_RAS#
S_WE#
S_A12
RN44A 10
1 8
RN47B 33
2 7
RN33C 33
3 6
RN42A 33
1 8
RN32D 33
4 5
RN38C 33
3 6
R14 22
1 2
RN41D 10
4 5
R11 33
1 2
RN26A 33
8 1
RN30D 10
4 5
RN49A 33
1 8
RN37B 10
2 7
RN28D 33
4 5
RN44D 33
4 5
RN35D 33
4 5
RN46B 33
2 7
RN37A 33
1 8
RN42C 33
3 6
RN32C 33
3 6
R15 22
1 2
RN41B 10
2 7
RN47C 33
3 6
RN29D 10
4 5
RN30A 33
1 8
RN41A 33
8 1
RN36B 10
2 7
RN31A 33
8 1
RN45A 33
8 1
RN35C 33
3 6
RN37C 33
3 6
RN46D 33
4 5
RN43D 33
4 5
RN40B 10
2 7
RN26B 33
2 7
RN34A 33
8 1
RN30B 10
2 7
RN48A 33
1 8
RN29A 33
1 8
RN41C 33
3 6
RN36D 10
4 5
RN32A 33
1 8
RN39A 33
8 1
RN34D 10
4 5
RN49D 33
4 5
RN27B 33
2 7
RN26C 33
3 6
RN46C 33
3 6
RN40D 10
4 5
RN44B 33
2 7
RN35A 33
8 1
RN42D 33
4 5
RN28C 33
3 6
RN33A 33
1 8
R12 22
1 2
RN40A 33
1 8
RN39D 10
4 5
RN34B 10
2 7
RN27D 33
4 5
RN49B 33
2 7
RN26D 33
4 5

A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TM5800 Design Guide
Custom
A
BasilThursday,November 29,2001
3 5
TM5800 PCI Interface
3940 Freedom Circle
Santa Clara, CA. 95054
[phone]
DOCUMENT#
Copyright (C)1995-2001 Transmeta
Corporation. All rights reserved.
This documentcontains confidentialand
proprietaryinformationof Transmeta
Corporation. It is not tobe disclosed orused
except inaccordance with applicable
agreements. This copyrightnoticedoes not
evidenceany actual orintended publication of
suchdocument. Pageof
Title:
DocumentNumber:
Size:
Revision:
Date:Author:
Project:
PCI_AD4
RSVD_G1_PU
PCI_AD14 RSVD_H6_PU
PCI_AD22
PCI_AD19
PCI_AD17
PCI_AD23 NC_RSVD_J4
RSVD_V3_PU
RSVD_F7_PU
PCI_AD21
RSVD_V2_PU
PCI_AD12
PCI_AD31
PCI_AD20
NC_RSVD_R4
PCI_AD26
RSVD_W6_PU
PCI_AD15
RSVD_E7_PD
PCI_AD25
PCI_AD18
PCI_AD5
NC_SNIFF_VCORE
PCI_AD10
NC_SNIFF_GND
RSVD_V1_PU
PCI_AD28
PCI_AD6
NC_RSVD_T5
NC_RSVD_J5
PCI_AD27
RSVD_G13_PD
PCI_AD2
NC_RSVD_D7
PCI_AD1
PCI_AD11
PCI_AD16 NC_RSVD_R2
PCI_AD3
PCI_AD7
PCI_AD0
NC_RSVD_G11
PCI_AD13
RSVD_H5_PU
PCI_AD8
PCI_AD30
PCI_AD9
PCI_AD29
PCI_AD24
PCI_SERR#
PCI_CBE3#
PCI_GNT4#
PCI_FRAME#
PCI_IRDY#
PCI_AD[31..0]
PCI_CBE2#
PCI_TRDY#
UNPROTECT
CLK_PCI_TM
PCI_GNT3#
PCI_CBE1#
PCI_PAR
PCI_GNT2#
PCI_HLDA#
PCI_GNT5#
PCI_GNT0#
PCI_CBE0#
PCI_RST#
PCI_CLKRUN#
PCI_GNT1#
PCI_DEVSEL#
PCI_STOP#
PCI_REQ0#
PCI_REQ5#
PCI_REQ4#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_HLD#
V3_3V3_3 V3_3 V3_3V3_3V3_3
R?
10K
12
RN50C 10K
3 6
RN54C 10K
3 6
RN52D 10K
4 5
RN51B 10K
2 7
RN51C 10K
3 6
RN53A 10K
1 8
RN55A 10K
1 8
RN50D 10K
4 5
RN51D 10K
4 5
RN54B 10K
2 7
(PART 3 OF 5)
PCI
RESERVED
U1C
Crusoe BGA474
B19
C18
B18
B17
D16
E16
E17
C16
F16
E15
D15
F15
C15
E14
D14
B15
E12
F11
E11
D11
D12
C11
E10
D10
F9
E9
D9
B8
C9
B9
A9
A10
A12
B11
A11
B10
D19
D18
E19
E18
F19
F18
G15
A16
F13
A15
G16
F17
J18
A17
A13
B12
E13C19
A14
B14
F8
F12
E8
D13 C13
B13
G13
G2
W6
H5
G1
V2
D7
AE19
V1
V3
H6
E7
F7
G11
R1
R2
T5
R4
J4
J5
P_AD0
P_AD1
P_AD2
P_AD3
P_AD4
P_AD5
P_AD6
P_AD7
P_AD8
P_AD9
P_AD10
P_AD11
P_AD12
P_AD13
P_AD14
P_AD15
P_AD16
P_AD17
P_AD18
P_AD19
P_AD20
P_AD21
P_AD22
P_AD23
P_AD24
P_AD25
P_AD26
P_AD27
P_AD28
P_AD29
P_AD30
P_AD31
P_C/BE0#
P_C/BE1#
P_C/BE2#
P_C/BE3#
P_REQ0#
P_REQ1#
P_REQ2#
P_REQ3#
P_REQ4#
P_REQ5#
P_GNT0#
P_GNT1#
P_GNT2#
P_GNT3#
P_GNT4#
P_GNT5#
P_CLKRUN#
P_DEVSEL#
P_FRAME#
P_IRDY#
P_HLDA#P_HOLD#
P_LOCK#
P_PAR
P_PCLK
P_PERR#
P_PCI_RST#
P_SERR# P_STOP#
P_TRDY#
RSVD_G13
RSVD_G2
RSVD_W6
RSVD_H5
RSVD_G1
RSVD_V2
RSVD_D7
RSVD_AE19
RSVD_V1
RSVD_V3
RSVD_H6
RSVD_E7
RSVD_F7
RSVD_G11
RSVD_R1
RSVD_R2
RSVD_T5
RSVD_R4
RSVD_J4
RSVD_J5
R17
4.7K
12
RN52A 10K
1 8
RN52B 10K
2 7
RN55D 10K
4 5
RN54A 10K
1 8
RN52C 10K
3 6
R16 10K
1 2
RN51A 10K
1 8
RN50B 10K
2 7
RN55C 10K
3 6
R18
4.7K
12
RN54D 10K
4 5
RN53B 10K
2 7
RN50A 10K
1 8
RN53C 10K
3 6
RN55B 10K
2 7

A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
SYSTEMS THAT DO NOT INSTALL MODE BIT ROM:
INSTALL PU WHEN CMS IS IN THE SERIAL ROM
INSTALL PD WHEN CMS IS IN THE PARALLEL ROM
TM5800 Design Guide
Custom
A
BasilTuesday,December 04, 2001
4 5
TM5800 Sideband
3940 Freedom Circle
Santa Clara, CA. 95054
[phone]
DOCUMENT#
Copyright (C)1995-2001 Transmeta
Corporation. All rights reserved.
This documentcontains confidentialand
proprietaryinformationof Transmeta
Corporation. It is not tobe disclosed orused
except inaccordance with applicable
agreements. This copyrightnoticedoes not
evidenceany actual orintended publication of
suchdocument. Pageof
Title:
DocumentNumber:
Size:
Revision:
Date:Author:
Project:
NC_EPROMA0
VRDA0
VRDA3
VRDA2
VRDA1
VRDA4
NM_DEBUG_INT
PWRGOOD
SROM_CS0#
CLK_CPU
EPROMA1
SROM_SIN
CPU_INIT#
SROM_SCLK
TDM_TMS
CPU_STPCLK# DIODE_CATHODE
SRCLK
CPU_IGNNE#
TDM_SROM_CS1#
CPU_FERR#
TDM_TRST#
DEBUG_INT
CPU_SMI#
TDM_TCK
TDM_SDA
TDM_TDO
TDM_RST#
DIODE_ANODE
PCI_RST#
TDM_TDI
CPU_NMI
TDM_SCL
CPU_INTR
SRDATA
EPROMA2
SROM_SOUT
SUSPEND#
VRDA[4..0]
V3_3V3_3
R21 10K
12
R25 1.2K
1 2
R30 3.3K
12
R22 10K
12
R29
4.7K
NI
12
R20 10K
12
R19 4.7KNI
12
R23 1.2K
12
R27
10K
12
R31 3.3K
12
R32 3.3K
12
R28
10K
12
R26 4.7K
1 2
R33 3.3K
12
R24 1.2K
12
(PART 4 OF 5)
U1D
Crusoe BGA474
C7
G7
H19
G18
G19
H17
G14
H15
H18
D8
A8
K17
H14
W11
G9
W7
A19
W9
Y12
Y13
V14
W14
W13
A18
B16
H16
J16
J15
J19
B7
K15
L15
L16
K18
A6
B6
AE1
CLKIN
PWRGOOD
RESET#
INIT#
INTR
NMI
SMI#
IGNNE#
STPCLK#
SLEEP#
CFG_SDATA
SROM_SIN
DEBUG_INT
NM_DEBUG_INT
TRST#
TCK
TMS
TDI
VRDA0
VRDA1
VRDA2
VRDA3
VRDA4
DIODE_ANODE
DIODE_CATHODE
FERR#
EPROMA0
EPROMA1
EPROMA2
CFG_SCLK
SROM_CS0#
SROM_CS1#
SROM_SCLK
SROM_SOUT
S_SCLK
S_SDATA
TDO

A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
TANT TANT
TANT
POLYPOLY POLY POLY POLY
NOTE: C2 IS NOT INSTALLED, HOWEVER,
IT IS STRONGLY RECOMMENDED THAT
DESIGNS INCLUDE FABRICATION PADS
(FOOTPRINTS) FOR THESE PARTS.
TM5800 Design Guide
Custom
A
BasilThursday,November 29,2001
5 5
TM5800 PWR & GND
3940 Freedom Circle
Santa Clara, CA. 95054
[phone]
DOCUMENT#
Copyright (C)1995-2001 Transmeta
Corporation. All rights reserved.
This documentcontains confidentialand
proprietaryinformationof Transmeta
Corporation. It is not tobe disclosed orused
except inaccordance with applicable
agreements. This copyrightnoticedoes not
evidenceany actual orintended publication of
suchdocument. Pageof
Title:
DocumentNumber:
Size:
Revision:
Date:Author:
Project:
U1_A7
V2_5
V_CPU_PLLV3_3
V_CPU_CORE
C40
1uF
CC0805
12
C45
1uF
CC0805
12
C12
1uF
CC0805
12
FB1
100_Ohms@100MHz
HI_0603
1 2
C25
1uF
CC0805
12
C35
1uF
CC0805
12
(PART 5 OF 5)
U2E
Crusoe_BGA474
FRED
A7
C6
C14
D3
D17
H7
H13
J3
J6
J8
J12
J14
J17
K7
K13
L6
L14
M7
N3
N6
P7
R6
T7
U3
U6
U8
V7
AB3
AC6
M13
N14
P13
R14
T13
U12
U14
V13
N17
U17
AB17
AC14
H9
H11
J10
K9
K11
L8
L10
L12
M9
M11
N8
N10
N12
P9
P11
R8
R10
R12
T9
T11
U10
V9
V11
L17
M6
M8
M10
M12
M14
N7
N9
N11
N13
P6
P8
P10
P12
P14
R3
R7
R9
R11
R13
R17
T6
T8
T10
T12
T14
U7
U9
U11
U13
V8
V10
V12
W3
W8
W10
W12
W17
Y6
Y10
Y14
AC3
AC8
AC10
AC12
AC17
C3
C8
C10
C12
C17
F6
F10
F14
G3
G8
G10
G12
G17
H8
H10
H12
J7
J9
J11
J13
K6
K8
K10
K12
K14
L3
L7
L9
L11
L13
PLLVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
IOVDD25
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+
C3
22uF
CC7343
12
C46
0.1uF
12
C27
1uF
CC0805
12
C2
0.1uF
NI
12
C47
0.1uF
12
C13
1uF
CC0805
12
C15
1uF
CC0805
12
+
C56
270uF
CC7343
12
C48
0.1uF
12
C41
1uF
CC0805
12
C49
0.1uF
12
C34
1uF
CC0805
12
C22
1uF
CC0805
12
C42
1uF
CC0805
12
C6
1uF
CC0805
12
C50
0.1uF
12
C14
1uF
CC0805
12
C51
0.1uF
12
+
C55
270uF
CC7343
12
C33
1uF
CC0805
12
C21
1uF
CC0805
12
C52
0.1uF
12
C53
0.1uF
12
C7
1uF
CC0805
12
+
C54
270uF
CC7343
12
C38
1uF
CC0805
12
C31
1uF
CC0805
12
+
C17
22uF
CC7343
12
C20
1uF
CC0805
12
C18
1uF
CC0805
12
C32
1uF
CC0805
12
C8
1uF
CC0805
12
+
C58
270uF
CC7343
12
C28
1uF
CC0805
12
C9
1uF
CC0805
12
C19
1uF
CC0805
12
C36
1uF
CC0805
12
C44
1uF
CC0805
12
C37
1uF
CC0805
12
C26
1uF
CC0805
12
C5
1uF
CC0805
12
C24
1uF
CC0805
12
C29
1uF
CC0805
12
+
C57
270uF
CC7343
12
C10
1uF
CC0805
12
C30
1uF
CC0805
12
C39
1uF
CC0805
12
C43
1uF
CC0805
12
+
C4
22uF
CC7343
12
C16
1uF
CC0805
12
C11
1uF
CC0805
12
C23
1uF
CC0805
12