Cypress Semiconductor CY7C1019BN User manual

128K x 8 Static RAM
CY7C1019BN
Cypress Semiconductor Corporation • 198ChampionCourt • San Jose,CA 95134-1709 • 408-943-2600
Document #: 001-06425 Rev. ** Revised February 1, 2006
Features
•Highspeed
—t
AA = 12, 15 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Functionally equivalent to CY7C1019
Functional Description
The CY7C1019BN is a high-performance CMOS static RAM
organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0through I/O7) is then written into the location
specified on the address pins (A0through A16).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O0through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1019BN is available in standard 32-pin TSOP Type
II and 400-mil-wide SOJ packages.
14 15
Logic Block Diagram Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
ROW DECODER
SENSE AMPS
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
A11 A13 A12
A
A10
CE
A A16
A9
1
2
3
4
5
6
7
8
9
10
11
14 19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15 17 18
A7
A1
A2
A3
CE
I/O0
I/O1
VCC
A13
A16
A15
OE
I/O7
I/O6
A12
A11
A10
A9
I/O2
A0
A4
A5
A6
I/O4
VCC
I/O5
A8
I/O3
WE
VSS
A14
VSS
/ TSOPII
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CY7C1019BN
Document #: 001-06425 Rev. ** Page 2 of 8
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VCC to Relative GND[1] ....–0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State[1] ....................................–0.5V to VCC + 0.5V
DC Input Voltage[1].................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selection Guide
7C1019BN-12 7C1019BN-15 Unit
Maximum Access Time 12 15 ns
Maximum Operating Current 140 130 mA
Maximum Standby Current 10 10 mA
L 1 1 mA
Operating Range
Range Ambient Temperature[2] VCC
Commercial 0°C to +70°C 5V ±10%
Industrial –40°C to +85°C 5V ±10%
Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
-12 -15
UnitMin. Max. Min. Max.
VOH Output HIGH Voltage VCC =Min., IOH =–4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
VIH Input HIGH Voltage 2.2 VCC+ 0.3 2.2 VCC+ 0.3 V
VIL Input LOW Voltage[1] –0.3 0.8 –0.3 0.8 V
IIX Input Leakage
Current GND < VI< VCC –1 +1 –1 +1 µA
IOZ Output Leakage
Current GND < VI <VCC, Output Disabled –5 +5 –5 +5 µA
ICC VCC Operating
Supply Current VCC = Max.,IOUT = 0 mA, f = fMAX = 1/tRC 140 130 mA
ISB1 Automatic CE
Power-Down Current
—TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or
VIN < VIL, f = fMAX
40 40 mA
L20 20
ISB2 Automatic CE
Power-Down Current
—CMOSInputs
Max. VCC,
CE > VCC – 0.3V,
VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10 10 mA
L1 1
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA= 25°C, f = 1 MHz,
VCC = 5.0V 6pF
COUT Output Capacitance 8 pF
Notes:
1. VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TAis the “Instant On” case temperature.
3. Tested initially and after any design or process changes that may affect these parameters.
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CY7C1019BN
Document #: 001-06425 Rev. ** Page 3 of 8
AC Test Loads and Waveforms
Switching Characteristics[4] Over the Operating Range
Parameter Description
-12 -15
UnitMin. Max. Min. Max.
Read Cycle
tRC Read Cycle Time 12 15 ns
tAA Address to Data Valid 12 15 ns
tOHA Data Hold from Address Change 3 3 ns
tACE CE LOW to Data Valid 12 15 ns
tDOE OE LOW to Data Valid 6 7 ns
tLZOE OE LOW to Low Z 0 0 ns
tHZOE OE HIGH to High Z[5, 6] 67ns
tLZCE CE LOW to Low Z[6] 33 ns
tHZCE CE HIGH to High Z[5, 6] 67ns
tPU CE LOW to Power-Up 0 0 ns
tPD CE HIGH to Power-Down 12 15 ns
Write Cycle[7, 8]
tWC Write Cycle Time 12 15 ns
tSCE CE LOW to Write End 9 10 ns
tAW Address Set-Up to Write End 8 10 ns
tHA Address Hold from Write End 0 0 ns
tSA Address Set-Up to Write Start 0 0 ns
tPWE WE Pulse Width 8 10 ns
tSD Data Set-Up to Write End 6 8 ns
tHD Data Hold from Write End 0 0 ns
tLZWE WE HIGH to Low Z[6] 33 ns
tHZWE WE LOW to High Z[5, 6] 67ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 30-pF load capacitance.
5. tHZOE, tHZCE, and tHZWE are specifiedwith a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(a) (b)
≤ 3 ns ≤3ns
OUTPUT
R1 480ΩR1 480Ω
R2
255ΩR2 255Ω
167Ω
Equivalent to: THÉVENIN EQUIVALENT
1.73V
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CY7C1019BN
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Data Retention Characteristics Over the Operating Range (L Version Only)
Parameter Description Conditions Min. Max. Unit
VDR VCC for Data Retention No input may exceed VCC + 0.5V
VCC = VDR = 2.0V,
CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
2.0 V
ICCDR Data Retention Current 300 µA
tCDR[3] Chip Deselect to Data Retention Time 0 ns
tROperation Recovery Time 200 µs
Data Retention Waveform
3.0V3.0V
tCDR
VDR >2V
DATA RETENTION MODE
tR
CE
VCC
Switching Waveforms
Read Cycle No. 1[9, 10]
Read Cycle No. 2 (OE Controlled)[10, 11]
Notes:
9. Device is continuously selected. OE, CE = VIL.
10.WE is HIGH for read cycle.
11.Address valid prior to or coincident with CE transition LOW.
PREVIOUS DATA VALID DATA VALID
tRC
tAA
tOHA
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE tHZCE
tPD
HIGH
OE
CE
ICC
ISB
IMPEDANCE
ADDRESS
DATA OUT
VCC
SUPPLY
CURRENT
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CY7C1019BN
Document #: 001-06425 Rev. ** Page 5 of 8
Write Cycle No. 1 (CE Controlled)[12, 13]
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
Notes:
12.Data I/O is high impedance if OE = VIH.
13.If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
14.During this period the I/Os are in the output state and input signals should not be applied.
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD tSD
tSCE
tSCE
CE
ADDRESS
WE
DATA I/O
tHD
tSD
tPWE tSA
tHA tAW
tSCE
tWC
tHZOE
DATAIN VALID
CE
ADDRESS
WE
DATA I/O
OE
NOTE 14
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CY7C1019BN
Document #: 001-06425 Rev. ** Page 6 of 8
Write Cycle No. 3 (WE Controlled, OE LOW)[13]
Switching Waveforms (continued)
DATA VALID
tHD
tSD
tLZWE
tPWE tSA
tHA tAW
tSCE
tWC
tHZWE
CE
ADDRESS
WE
DATA I/O NOTE 14
Truth Table
CE OE WE I/O0–I/O7Mode Power
H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)
Ordering Information
Speed
(ns) Ordering Code Package Diagram Package Type Operating Range
12 CY7C1019BN-12VC 51-85033 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019BN-12ZC 51-85095 32-Lead TSOP Type II
CY7C1019BN-12ZXC 51-85095 32-Lead TSOP Type II (Pb-free)
15 CY7C1019BN-15VC 51-85033 32-Lead 400-Mil Molded SOJ Commercial
CY7C1019BN-15ZXC 51-85095 32-Lead TSOP Type II (Pb-free)
Please contact local sales representative regarding availability of these parts
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CY7C1019BN
Document #: 001-06425 Rev. ** Page 7 of 8
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
All product or company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
51-85033-A
51-85033-*B
32-pin (400-mil) Molded SOJ (51-85033)
51-85095-**
32-pin TSOP II (51-85095)
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CY7C1019BN
Document #: 001-06425 Rev. ** Page 8 of 8
Document History Page
Document Title: CY7C1019BN 128K x 8 Static RAM
Document Number: 001-06425
REV. ECN NO. Issue Date Orig. of Change Description of Change
** 423847 See ECN NXR New Data Sheet
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