TrueTime VME-SG2 560-5608 User manual
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Model 560-5608
VME-SG2
SERIAL NUMBER_______________
Revision A
January 8, 1999
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560-5608.IND.doc i Rev. A
TABLE OF CONTENTS
SECTION PARAGRAPH TITLE
ONE GENERAL INFORMATION
1.1 Scope of Manual
1.2 Purpose of Equipment
1.3 Physical Description
1.4 Environmental Specifications
1.5 Power Requirements
1.6 Signal Specifications
1.6.1 General To All Modes
A. VME Bus
B. Interrupts
C. Time Compare Outputs
D. External Freeze Event Input
E. Rate Generator Output
F. Auto Leap Year
G. Internal Oscillator
H. External Start Input
I. Pulse Rate
J. IRIG B DC (TTL) Time Code Output
K. IRIG B Amplitude Modulated Time Code Output
L. IRIG B DC (TTL) Time Code Output
1.6.2 Generator Specifications
A. General
B. External Time Base
1.6.3 Sync-Generator Specification
A. General
B. GPS Reference
C. Reference Code Input, Carrier
D. Reference Code Input, DC (RS-422)
1.6.4 I/O Connector Specifications
A. VME P2/J2 Connector
B. Front Panel BNC Connector
1. External Event Input
2. Reference Code Input
3. Generator Code Output
4. 1 PPS Output
TWO INSTALLATION AND OPERATION
2.1 Introduction
2.2 Installation
2.3 Operation, General Information
2.4 Operation, Detailed Information
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560-5608.IND.doc ii Rev. A
TABLE OF CONTENTS
(Continued)
SECTION PARAGRAPH TITLE
TWO INSTALLATION AND OPERATION
2.4.1 Generator
2.4.2 GPS Synchronized Generator
2.4.3 Code Synchronized Generator
2.4.4 Front Panel Indicators And Display
2.4.5 Oscillator Discipline
2.4.6 Reading Time
2.4.7 Reading Position
2.4.8 Loading Position
2.4.9 Operational Configuration And Status Registers
2.4.10 VME Interrupt Control
2.4.11 VME-SG-GPS Memory Map
2.5 Programming Examples
THREE MANUFACTURERS SPECIFICATIONS
FOUR DRAWINGS
Drawing Number Title
560-1146 VME-SG Front Panel Assembly/BOM
560-5608 VME-SG2 Assembly/BOM
560-5603 VME Processor Board Assembly/BOM
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GENERAL INFORMATION
1.1 SCOPE OF MANUAL
This manual contains the information necessary to operate and maintain the TrueTime
VME Timing Cards. Multiple configurations are described. This VME product line
consists of the VME Timing board which by itself is referred to as the VME-SG. When a
GPS Engine is added to the basic VME Timing board assembly the product becomes
known as the GPS-VME. All functions described in this manual are available in the
GPS-VME version. The VME-SG does not provide GPS related functions. Both the
GPS-VME and the VME-SG may be configured with the optional alphanumeric display
front panel assembly. In this manual these two board configurations are referred to as
the Model VME-SG-GPS.
1.2 PURPOSE OF EQUIPMENT
The VME-SG-GPS is a precision time source that conforms with the IEEE 1014.C-1
VMEbus Specification. The VME-SG-GPS operates in one of the following three
modes: Generator, GPS Synchronized Generator (GPS-VME only) or Code
Synchronized Generator. In all modes the VME-SG-GPS is designed to supply precise
time to a VME based computer. The time consists of microseconds through thousands
of years. In the Generator mode the time can be started, stopped and preset via the
VME bus. The Generator counters can also be started using an external reference 1
PPS pulse. In the GPS Synchronized Generator mode the card operates with the GPS
Engine. Time and position are derived from the NAVSTAR Global Positioning System
(GPS). In the Code Synchronized Generator mode the generator will phase lock to an
external IRIG B time code. The code format can be either amplitude modulated or DC
shift at RS-422 logic levels. In all synchronized modes the internal oscillator is
disciplined to remove any frequency offset with respect to the external reference. This
is necessary to maintain precise phase lock and to minimize drift error if the input
reference is lost.
Time information and status are available to the VME computer bus in five, 16 bit words.
Each word contains up to 4 packed BCD time values. Since no time ready flags must
be set before time information can be read, the data is immediately available (zero
latency). On board DIP switches select the memory address space where the VME-SG
board resides.
Two independent time capture register sets are provided. Time is latched or "frozen" in
one set of registers by a user read operation via the VME bus. This will provide time on
request. The second set of capture registers has the time latched into it when an
External Event pulse occurs. This allows time tagging of an External Event. An event
normally is programmed to generate an interrupt to flag its occurance.
A Rate Generator is provided that is configured by the user to output one of 5 different
pulse rates to the P2 connector. The Rate Pulse can also be configured to produce an
interrupt to the VME processor.
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Two Time Compare register sets are available that are preset with time values from
hundreds of days through microseconds via the VME bus. When either compare time is
equal to the generator time an output pulse is generated.
Four independently programmable interrupts are available each with software selectable
priority. The interrupt sources are the External Event, Rate Pulse, Time Compare 1 and
Time Compare 2.
The VME-SG-GPS is configured as an A16/D16 slave board responding to the Address
Modifier codes hex 29 (short non-priviledged) and hex 2D (short supervisory). The
VME-SG-GPS is memory mapped on any 256 byte boundary of the VME bus short
address space using the eight position DIP switch located on the board.
1.3 PHYSICAL DESCRIPTION
The VME-SG configuration is a single slot board meeting the VME standard 6U height
specification. When the optional display is added two slots are required. The GPS-VME
configuration requires two slots with a 6U height.
1.4 ENVIRONMENTAL SPECIFICATIONS
The Model VME-SG-GPS is designed to operate over a wide ambient temperature
range.
The environmental specifications are:
a. Operating - 0 to +50 degrees C (+32 to +122 F)
b. Storage - -17 to +100 degrees C (0 to +212 F)
c. Humidity - To 95% relative, non-condensing
1.5 POWER REQUIREMENTS
The maximum input power specifications are:
a.Voltage - +5VDC @ 700 ma
+ 12 VDC @ 50 ma each,
(from VME bus connector)
1.6 SIGNAL SPECIFICATIONS
1.6.1 GENERAL TO ALL MODES
A. VME Bus - Falling edge of /DSA to falling Access Time edge
of /DTAK is less than 400 nanoseconds.
B. Interrupts
Number - Four independent
Priority - Configurable to any of seven levels.
Sources - External Event
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- Programmed Rate Generator
- Programmed Compare Time #1
- Programmed Compare Time #2
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C. Time Compare Outputs
Outputs a pulse at the programmed compare time #1.
Outputs a pulse at the programmed compare time #2.
Asserts the Interval level during the interval between compare time #1 and
compare time #2.
Resolution - 1 microsecond
Pulse Width - 2 milliseconds
Compare Mask - milliseconds through hundreds of days
Signal Level - Positive going, +5v @ +/- 6ma
See section 1.6.4 for P2/J2 pin assignment
D. External Freeze Event Input
Edge - Rising or falling
Input - Logic 0: 0 +.5 VDC
Voltage Logic 1: +2.5 to 5 VDC
Input - 4.7 K ohms to +5 VDC
The External Freeze Event signal may be input at the front panel BNC or on the
P2/J2 connector. See section 1.6.4 for P2/J2 pin assignment.
E. Rate Generator Output
Outputs a programmed pulse rate. Rising edge on-time.
Rates - 10K, 1K, 100, 10 and 1 Pulse Per Second (PPS)
Signal Level - Positive going, +5v @ +/- 6ma
See section 1.6.4 for P2/J2 pin assignment.
F. Auto Leap Year - calculated using year
G. Internal Oscillator (TCVCXO)
Frequency - 10MHz
Stability - 1 PPM, 0 to +50 Degrees C
Aging - < 1PPM/Year
H. External Start Input
Start Timing - Selectable positive or negative edge.
Input Voltage - Logic Zero: 0vdc, +/- .5vdc
Logic One: >+2.5vdc, <+5vdc
Input Impedance: 4.7K Ohms to +5v
The External Start signal is input on the P2/J2 connector.
See section 1.6.4 for P2/J2 pin assignment.
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I. Pulse Rate
Frequencies - 1PPS
Duty Cyle - 50%
Amplitude - 0vdc to +5vdc @ +/- 6ma
Timing - Positive going edge on time
See section 1.6.4 for P2/J2 pin assignment.
J. IRIG B DC Time Code Output (TTL)
Amplitude - 0vdc to +5vdc @ +/- 6ma
See section 1.6.4 for P2/J2 pin assignment.
K. IRIG B Amplitude Modulated Time Code Output
Amplitude - Adjustable from 0vpp to 10vpp into 600 Ohms to
ground
Ratio - Adjustable from 2:1 to 5:1
See section 1.6.4 for P2/J2 pin assignment.
L. IRIG B DC Time Code Output (RS-422)
Signal Output - RS-422 Logic Levels
See section 1.6.4 for P2/J2 pin assignment.
1.6.2 GENERATOR SPECIFICATIONS
A. General Specifications
Indicators - Power, 1PPS
LEDs
B. External Time Base Input (generator only)
Frequency - 10MPPS
Input Voltage - Logic Zero: 0vdc, +/- .5vdc
Logic One: >+2.5vdc, <+5vdc
The External Time Base signal is input on the P2/J2 connector.
See section 1.6.4 for P2/J2 pin assignment.
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1.6.3 SYNCHRONIZED GENERATOR SPECIFICATIONS
A. General Specifications
Indicator - Power
LEDs - 1 PPS
- Phase Locked
- Input Code Error
B. GPS Reference
Phase - Less than 1 microsecond to UTC,
Accuracy typically less than 500 nanoseconds
Osc. Freq. - Better than 1 E -7, typically 5 E -8
Discipline
Phase - 100 nanosecond after PHASE LOCK
Correction
Step Size
Position - Latitude, Longitude and Elevation 100 meters
2DRMS
Time To - <20 minutes when at least 4 satellites available
First Lock
User Time - + 99999 nanoseconds
Bias
Local Offset - + 12 hours
C. Reference Code Input, Carrier
Format - IRIG B122
Amplitude - 1vpp to 10vpp
Impedance - 10K ohms to ground
Ratio - 2:1 to 5:1
Error - Fixed at 3 frames
Bypass
Osc. Freq. - Better than 1 E -7, typically 5 E -8
Discipline
Phase - Less than 2 microsecond, typically
Accuracy less than 1 microsecond
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Phase - 100 nanosecond after PHASE LOCK Correction
Step Size
Phase - + 1 millisecond in 1 microsecond steps
Compensation
The Time Code signal may be input at the front panel BNC or on the P2/J2
connector.
See section 1.6.4 for P2/J2 the pin assignment.
D. Reference Code Input, DC Shift (RS-422)
Format - IRIG B122
Signal - RS-422 logic level
Impedance - 120 ohms selectable using JP1
Error - Fixed at 3 frames
Bypass
Phase - Less than 1 microsecond, typically
Accuracy less than 500 nanoseconds
Osc. Freq. - Better than 1 E -7, typically 5 E -8
Discipline
Phase - 100 nanosecond after PHASE LOCK
Correction
Step Size
The Time Code signal is input at the P2/J2 connector.
See section 1.6.4 for P2/J2 the pin assignment.
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1.6.4 I/O CONNECTOR SPECIFICATIONS
1. VME P2/J2 Connector
Table 1-1
Note:
Gen Codes and Ref Codes are IRIG B format.
Ref Code Out (RS-422) is the Ref Code Input signal re-driven through an
RS-422 driver for daisy chained systems.
2. Front Panel BNC Connectors
a. External Event Input
The External Event input is available on the front panel BNC labeled EXT
EVENT. This input is in parallel with the same input on the P2/J2
connector.
b. Reference Code Input
The amplitude modulated time code input is available on the front panel
BNC labeled CODE IN. This input is in parallel with the same input on
the P2/J2 connector.
c. Generator Code Output
The amplitude modulated time code output is available on the front panel
BNC labeled GEN CODE. This output is in parallel with the same output
on the P2/J2 connector.
d. 1PPS Output
The 1 pulse per second (PPS) output is available on the front panel BNC
labeled 1PPS. This output is in parallel with the same output on the
P2/J2 connector.
PIN # ASSIGNMENT PIN # ASSIGNMENT
C1 1PPS OUT A1 GND
C2 RATE PULSE OUT A2 GND
C3 CODE INPUT (AM) A3 GND
C4 TIME COMP #1 OUT A4 GND
C5 TIME COMP #2 OUT A5 GND
C6 INTERVAL OUT A6 GND
C7 EXT EVENT INPUT A7 GND
C8 EXTERNAL OSC INPUT A8 GND
C9 GEN CODE OUT DC (TTL) A9 GND
C10 GEN CODE OUT AM A10 GND
C11 GEN CODE OUT (RS-422)+ A11 GEN CODE OUT (RS-422)-
C12 REF CODE IN (RS-422)+ A12 REF CODE IN (RS-422)-
C13 REF CODE OUT (RS-422)+ A13 REF CODE OUT (RS-422)-
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1.6.5 JUMPER SPECIFICATIONS
RS-422 - Install jumper between JP1-2 and JP1-3
Term Res to enable termination (ON). Install
(120 ohms) jumper between JP1-1 and JP1-2 to disable (OFF).
GPS battery - Install jumper between JP2-2 and JP2-3
backup to connect battery (ON). Install jumper between JP2-1
and JP2-2 to disable (OFF).
1.6.6 OPTIONAL FRONT PANEL ALPHANUMERIC DISPLAY
Type - 4 character by 4 line LED
Display - Time (days, hrs, min & sec)
Info Date (month, day-of-month, year)
Oper Mode (gen, code sync-gen, GPS sync-gen*)
Sync Status (oper errors, phase)
Latitude*(degrees, minutes& seconds)
Longitude* (degrees, minutes & seconds)
Elevation* (meters)
Tracking Status* (number of satellites)
Self Test (error code)
*available in GPS-VME only
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SECTION TWO
INSTALLATION AND OPERATION
2.1 INTRODUCTION
This section contains installation instructions and operating procedures for the VME-SG-GPS.
As stated in section one there are two configurations of this product. The timing processor
board alone is referred to as the VME-SG 2. When the GPS Engine is installed the board is
referred to as the GPS-VME. The GPS-VME is capable of providing GPS related functions
only.
2.2 INSTALLATION
Unpack the unit and carefully inspect it for shipping damage. Any damage must be reported to
the carrier immediately.
Prior to insertion of the card into the users subrack the following setup/configuration operations
must be performed.
A. Base Address Selection:
The VME-SG-GPS will operate in the short address space selected by the DIP switch
located in U2. The DIP switch has 8 sections identified as 1 - 8. Each section may be set
ON or OFF to place the address space of the VME-SG-GPS on any 256-byte boundary.
The switch sections correspond to VME address bits A8 - A15. Section 1 selects the
least significant address. When the switch is in the ON position the zero address
condition is asserted. Therefore, to select the lowest address in VME memory all 8 switch
sections should be set "ON".
VME ADDRESS STRUCTURE
(24 bits represented)
MSB 23,22,21,20 19,18,17,16 15,14,13,12 11,10,9,8 7,6,5,4 3,2,1,0 LSB
|_________| |_________| |________| |______| |____| |_____|
| | | | | |
X X 0 0 B B
Figure 1 represents an OFFSET address of 00 Hex XX00BB where XX is the user defined MSB’s, 00
is the user selectable VME-SG-GPS OFFSET and BB is the Board address space which is allocated
for the VME-SG-GPS’s I/O.
Switch Positions 1 through 8 control the OFFSET address of the VME-SG card.
To set the OFFSET ADDRESS:
Select the offset address HEX value you want to use, such as 3A
Convert the hex value to BINARY, 00111010
REVERSE the order of the Binary number, 01011100
Set switches 1-8 using this REVERSE BINARY NUMBER. ON=0, OFF=1
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(Example 1) OFFSET ADDRESS XX3ABB
0=ON, 1=OFF Hex 3A
Black= Switch Position Binary 00111010
Reversed Order 01011100
(Example 2)
FACTORY DEFAULT OFFSET ADDRESS XXOOBB
Hex 00
Binary 00000000
Reversed Order 00000000
(Example 3) OFFSET ADDRESS XX55BB
Hex 55
Binary 01010101
Reversed Order 10101010
B. Backplane Jumpers:
The VME-SG-GPS has interrupt capability and the /IACKIN and the /IACKOUT signal
lines are passed in and out of the board. Be sure that any backplane jumpers on these
pins in the slot allocated to the VME-SG-GPS are removed even if the VME-SG-GPS
interrupts are not enabled.
C. P2 Connector Conflicts:
Some systems use the P2/J2 connector for their local bus or other control signals.
Several VME-SG-GPS input and output signals are located on the P2/J2 connector in
rows A and C. Verify that there is no conflict. Table 1-1 in section 1.6.4 describes the
pins used on the P2/J2 connector.
Mount the unit in the desired location and secure the front panel mounting screws. Mount
the antenna in the desired location (see drawing 142-800). Connect the antenna lead-in
to the front panel of the VME-SG-GPS.
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2.3 OPERATION, GENERAL INFORMATION
This section describes operating procedures for the standard VME-SG-GPS. This manual
describes some options that may not be present in the users particular card configuration.
Section 2.5 provides programming examples to further illustrate the operational capabilities of
the VME-SG-GPS.
The VME-SG-GPS is configured as an A16/D16 slave board responding to the Address
Modifier codes hex 29 (short non-privileged) and 2D (short supervisory). The interface consists
of address decode logic, the VME-2000 interface controller chip and various bus interface
handshake logic.
There are three operating modes that may be selected by the user. They are Generator, GPS
Synchronized Generator and Code Synchronized Generator mode. At power up, the unit will
initialize itself in the GPS Synchronized Generator mode.
Time and status information that is read from the card and configuration and control information
that is written to the card is achieved with a 16 bit Dual Port RAM and specific hardware
registers. The Dual Port RAM is the storage location for time, status and control information.
The VME-SG-GPS writes the time and status words to the RAM at locations controlled by RAM
addressing logic. Other areas of the RAM are written to directly via the VME interface to load
configuration and control words. All operating modes and control of the VME-SG-GPS is
performed using these location. Section 2.4.9 provides a detailed description of the control
registers.
The VME-SG-GPS is capable of generating interrupts from up to four independent sources.
The sources are the External Event input, the Pulse Rate logic and the 2 Time Compare
Outputs. Each interrupt source separately configured with priority level as well as the interrupt
vector returned over the VME bus during an interrupt acknowledge sequence. The Bus Interrupt
Module (BIM) handles the VME interrupt operations. This device is programmed directly over
the VME interface. Section 2.4.10 describes the Interrupt Control logic.
The VME-SG-GPS Rate Generation logic provides 5 different pulse rate outputs. The pulses
can also trigger the VME bus interrupt (INT1). All pulse rate outputs are synchronous with the
board timing. The pulse rate output is also available on the P2/J2 bus. Section 2.4.9
describes programming the Rate Generation Logic. Section 2.5 lists example routines.
The VME-SG-GPS contains 2 Time Coincidence Compare registers that each output a strobe
at their programmed compare times. There is also an Interval logic level that is triggered high
with compare strobe #1 and set low with compare strobe #2. The strobes are rising edge on-
time and are set microsecond resolution. The compare strobes are also used to generate
interrupts (INT2 and INT3) to the VME interface.
Time is captured using the External Event detection logic. The external event pulse active edge
(rising or falling) selection is defined by Configuration Register #2, bit #2 (see section 2.4.6).
When the external event pulse occurs, Time Capture register #2 contains the time. The
External Event input pulse is programmed to generate the VME bus interrupt (INT0) to flag the
user that the event input occurred.
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A battery is provided on the board to supply power to the GPS Engine when the main power is
off. The battery power drives RAM memory and a real time clock located on the GPS Engine
card. The RAM is used to store position and almanac information. If this information is not
available at power up the GPS Engine will perform a cold start and enter a Search The Sky
mode to locate satellites. When a satellite is tracked, new almanac data is downloaded. This
process can take anywhere from 12 to 25 minutes. This process is necessary to compute
position and determine accurate time. See Position Mode in section 2.4 for more information.
After the VME-SG-GPS has attained phase lock and computed position, these parameters are
maintained in the battery backed GPS Engine even if power is lost. When power is restored
these parameters will be transferred into the time and position registers in the main processor
board. This occurs a few seconds after the card has initialized itself. If UTC time is selected
for output (config register #2, bit 7) the time information will indicate a difference of several
seconds after power up since GPS time rather than UTC time is maintained in the GPS Engine
during the power down time.
A jumper is installed on JP2 between pins 2 and 3 to connect the battery at the factory prior to
shipment. If the card is to be stored for extended periods (months) the jumper should be
installed between pins 1 and 2 which disconnects the battery. When power is ON there is no
battery current drain.
2.4 OPERATION, DETAILED INFORMATION
2.4.1 GENERATOR
The Generator accumulates time using an internal or external time base and provides
time information to the VME bus consisting of microseconds through thousands of
years. The VME-SG-GPS contains two time capture register sets. Each capture
register consists of five 16 bit word locations where the current time is "frozen". Time is
captured in register number 1 when a time requests via the VME bus occurs. Time is
captured in register number 2 by an External Event input. This allows the user to
request time on demand as needed and also record when an external event has
occurred even if both occur simultaneously.
The generator is started and stopped using Configuration Register #1. The user may
preset the time from milliseconds through years while the Generator is stopped or
running. The generator can be synchronously started using an externally generated 1
PPS signal. The start strobe, when enabled, is input via the External Event input
connector. Either the rising or falling transition of the pulse is selected.
2.4.2 GPS SYCHRONIZED GENERATOR
The GPS Synchronized Generator mode operates as a Generator that is synchronized
to the GPS Engine. The GPS Engine receives transmissions from the Global
Positioning Satellite system and derives time that is traceable to the National Institute of
Standards and Technology (NIST). If the GPS Engine indicates that good time is
available, the card will phase lock the generator time registers. The VME-SG-GPS card
contains a Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO).
The VCTCXO is disciplined to remove any frequency errors. The phase errors are
removed by the Phase Correction logic which advances or retards the generator time
using 100 nanoseconds steps.
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When time from the GPS Engine is valid the front panel LOCK LED will blink slowly (2
second rate) until the phase errors are less than 10 microseconds. At that time the
LOCK LED will blink faster (twice per second) until the generator is phase locked to < 1
microsecond and the oscillator frequency has stabilized. At that time the LOCK LED will
be ON continuously. When time from the GPS Engine is not valid the LOCK LED will be
OFF. If the GPS Engine is not operating properly the red LED indicator on the front
panel identified as ERR illuminates. This LED may illuminate momentarily when power
is applied to the card or when the operational mode is changed. See Table 2-1 .
2.4.3 CODE SYCHRONIZED GENERATOR
The Code Synchronized Generator mode operates as a Generator that is synchronized
to an external IRIG B input code. The VME-SG-GPS card will operate with either IRIG B
amplitude modulated or IRIG B DC shift at RS-422 logic levels. The code input format
selection is made via Configuration register 2, bit 3. The Sync-Gen will phase lock to
the input code and discipline the VCTCXO. The phase correction logic advances or
retards the time to keep it phase locked to the IRIG reference. The Generator time is
phase shifted by 100 nanoseconds steps. The front panel LOCK LED indicator operates
in the same manner as in the GPS Synchronized Generator mode indicating relative
phase accuracy. See table 2-1. An ERR LED indicator on the front panel illuminates
when the input code is not present, is of the wrong format or fails to pass numerous
error detection criteria.
2.4.4 FRONT PANEL INDICATORS AND DISPLAY
LED INDICATORS - The VME-SG-GPS front panel has four indicator LEDs. They are
labeled POWER, 1PPS, LOCK and ERR. The POWER indicator is on when power is
applied to the card. The 1PPS indicator will blink once per second when the generator
is running. The LOCK and ERR indicators are only used in the synchronized generator
modes. The table below and sections 2.4.3 and 2.4.2 describe their operation.
LED
NAME CONDITION DEFINITION
LOCK Blinking Slowly Phase Error> 10 microseconds
Blinks Twice/sec Phase Error < 10 microseconds
ON Constantly Phase Error within spec
OFF Constantly Reference not valid
ERR ON Constantly Reference failure
OFF Constantly Reference is OK
Table 2-1, Front Panel LEDs
ALPHANUMERIC DISPLAY - An optional alphanumeric LED display is available that
consists of 4 lines by 4 characters. The display allows the user to observe time, date,
operational mode, sync status, position, satellite tracking status and self test results. A
switch on the front panel is used to select the different displays. The time display will
flash after power up in the GPS Sync-generator mode until LOCK has occurred. This
indicates that the time is not accurate.
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2.4.5 OSCILLATOR DISCIPLINE
The VME-SG-GPS will discipline the VCTCXO by driving a control voltage to the
oscillator so that its frequency relative to the time reference is as small as possible. The
accumulative phase error generated due to the frequency error of the oscillator is used
to drive the voltage control circuitry. If the time reference is lost oscillator discipline will
cease. The time will drift at a rate that is dependent on how well the oscillator was
disciplined and future changes in ambient temperature. The oscillator will discipline to
the reference to better than 1 part in ten to the seventh (typically 5 parts in ten to the
eighth). The oscillator has a temperature stability of 1 part in ten to the sixth from
0 to 50 degrees C. The major contributor to time drift when no reference is present is
temperature.
2.4.6 READING TIME
There are two capture register sets available in the VME-SG-GPS for the storing and
reading of the Generator time. There are time read examples in the Programming
Examples description Section 2.5.
Time Capture Registers #1
A computer read command via the VME interface is used to "freeze" the time in Capture
Register Set #1. The address that is read to assert the freeze is at the board base
address plus offset hex 40. The time is read in five 16 bit words at offsets hex 42 (word
1), 80 (word 2), 82 (word 3), 84 (word 4) and 86 (word5). Reading the location at offset
hex 44 releases the freeze registers.
Time Capture Register #2
Time Capture Register 2 is "frozen" by the External Event input pulse. The time is read
in five 16 bit words at offsets hex 46 (word 1), 88 (word 2), 8A (word 3), 8C (word 4) and
8E (word 5). Reading the location at offset hex 48 releases the freeze condition. The
External Event interrupt is used to determine that an external pulse occurred.
The data is in a packed BCD format as described below in table 2-2.
Table 2-2, Time Words
Data Bits
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word 1 Unit Msec Hund Mic-sec Tens Mic-sec Unit Mic-sec
Word 2 Tens Seconds Unit Seconds Hund Msec Tens Msec
Word 3 Tens Hours Unit Hours Tens Minutes Unit Minutes
Word 4 Status * Hund Days Tens Days Unit Days
Word 5 Thous Years Hund Years Tens Years Unit Years
* Status Definition
Bit 12 - Input Reference Error (Sync-Gen Modes)
Bit 13 - Phase Locked (Sync-Gen Modes)
Bit 14 - Reserved
Bit 15 - Reserved
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2.4.7 READING POSITION
When in the GPS synchronized generator mode position information is generated by the
GPS Engine. Position consists of latitude and longitude in degrees, minutes, seconds
with North/South/East/West indicators and elevation in meters above or below sea level.
The position information actually defines the location of the antenna.
Position data is read at address offsets hex 90 - 9E. All values are packed BCD except
for the North/South and East/West indications which are ASCII byte values. Table 2-3
below describes each position register with its address offset and data organization.
Table 2-3, Position
2.4.8 LOADING POSITION
When in the GPS synchronized generator mode the position of the antenna is loaded
using the position registers described above. It is sometimes advantageous to load the
position of the antenna since accurate antenna position will reduce timing errors.
Accurate time is computed if only one satellite is tracked when the position information
is known. Due to buildings or other physical obstruction 4 or more satellites may not be
in view with great enough regularity to allow the VME-SG-GPS card to compute position
conveniently.
The Position Computation Mode must first be set to KNOWN so the GPS Engine will
stop computing new position data. In all modes the position is output to the registers
described above except when the Position Update Inhibit bit is set. This bit is contained
in configuration register #2, bit #4. This bit allows the registers to be used for loading
new position from the VME bus.
0090 Latitude
(0, Hund, Tens, Units degrees)
0092 Latitude
(Tmin, Umin, Tsec, Usec)
0094 Latitude
(N/S, Tenths seconds)
0096 Longitude
(0, Hund, Tens, Units degrees)
0098 Longitude
(Tmin, Umin, Tsec, Usec)
009A Longitude
(E/W, Tenths Seconds)
009C Elevation
(Sign, Ten Thous & Thous Meters)
009E Elevation
(hund, Tens, Unit and Tenths Meters)
** The right most value is in the least
significant nibble of the 16 bit word.
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