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Revision 1
USER
I S
MANUAL
Revision B
JlB'le
11,
1980
Ccpyright
1980
Vector
Graphic
Inc.
7200-0203-03-02
Vector
ZCB
Single
Board CCJtplter
Section
Table
of
Contents
Specifications
I.
Perspective
1.1
The
ZCB
as
a system
••••••••••••••••••••••••••••••
~
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l-l
1.2
The
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as
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••••••••••••••••••••••••••••••••
1-1
1.
3
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1.4
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1.5
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1-2
1.5
.•
1
Serial
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••••••••••••••••••••••
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1-2
1.5.2
Serial
Asynchronous Communications
•••••••••••••••••••
1-3
1.5.3
Serial
Synchronous Communications
••••••••••••••••••••
1-3
1.5.4
RS-232C
Theory
•••••••••••••••••••••••••••••••••••••••
1-4
1.5.5
RS-232C
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••••••••••••••••••••.••••••••••
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1-5
1.5.6
Paral.lel l?C)'rts
•••••••••••••••••••••••••••••••••••••••
1-6
II.
User's
Guide
2.1
Introduction
•••••••••••••••••••••••••••••••••••••••••••••••
2-1
2.1.1
Standard
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what
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•••••••••••••••••
2-1
2.2
Cl?U
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•.••••••.••••••...••••
0
•••••••••••••••••••••••••
2-1
2.2.1
2.2.2
2.2.3
Running
the
system
at
2
or
4
MHz
••••••••••••••••••••
2-1
~
erlable/
disable
•.'
.......
It
•••••••••••
e
•••
III
.....
•
2-
2
Auto
WAIT
state
erlab1e/disab1e
••••••••••••••••••••••
2-2
2.
3
~
SectiCll"l
••••••••••••••••••••
'
••••••••••••••••••••••
2-2
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2708
EPRCMAddressing
•••••••••••••••••••••••••••••••
2-3
AuXiliary
Memory
Disab1e
••••••••••••••••••••••••••••
2-4
2716
EPROM
Addressing
•••••••••••••••••••••••••••••••
2-5
2732
EPROM
Addressing
•••••••••••••••••••••••••••••••
2-6
Enable on-board
EPROM
on
boot
•••••••••••••••••••••••
2-6
Phantan enab1e/disab1e
••••••••••••••••••••••••••••••
2-7
Jumper
areas
K,
Land M
•••••••••••••••••••••••••••••
2-7
2.4
I/O
Sectial
••••••••••••••••••••••••••••••••••••••••••••••••
2-7
2.4.1
2.4.2
2.4.3
2.4.4
Rev.
1-8
6/1l/80
I/O
Pc>rt
Mdressing
••.•••••••••••••••••••.••••••••••
2-7
Address Mirroring
disab1e/enab1e
••••••••••••••••••••
2-9
Asynchronous
Serial
Baud
Rate
Se1ection
•••••••••••••
2-11
HOw
to
connect
most
serial
terminals
and
printers
•••
2-11
Section
2.4.5
2.-4.6
2.4.7
2.4.S
2.4.9
Vector
ZCB
Single
Board Ccltplter
~
How
to
connect.
JOOSt
low speed
accustic
cooplers
•••••
2-15
COnnecting-additional
RS-232C
handshaking
lines
•••••
2-l5
USing
the
Parallel
Ports
••••••••••••••••••••••••••••
2-lS
COnnecting
Sprint
3
to
ZCB
••••••••••••••••••••••••••
2-l9
Connecting Vector
MP
to
ZCB
•••••••••••••••••••••••••
2-19
2.9 Spare
Clip-
and
Patch
areas
•••••••••••••••••••••••••••••••••
2-20
III.
'lheory
of
Operation·
3.1
System
operation
Block Diagram
•••••••••••••••••••••••••••••
3-l
3.2
Serial
Ports
•••••••••••••••••••••••••••••••••••••••••••••••
3-2
N.
Schematics
Rev.
l-B
6/ll/S0
vector
ZCB
Single
Board
COtplter
canpatibility:
Po\oter
Requirements
Availabili
ty:
EPRQ1s
included
with
board
Mem:n:y
Speed
SPOCIFlCATICNS-System
Most
5-100
systems.
+8VOC
@
970
rna.
(typ.)
+16
VDC
@
120
mao
-16
VDC
@
SO
rna.
Shi~
assenbled,
tested,
burned
in
~
no
kits.
SPECIFlCATIctS-EPRCM/RAM
65536
bytes
addressable,
1024
bytes
RAM
on
board,
3
EPRCM
sockets
on
board,
up
to
12K
addressable
nooe
RAM:
300ns.
EPRCM:
User
selected
(450.
ns.
typical)
RAM:
2114
static
EPROM:
270S,
2716,
2732
Standard
r.ocatiat
of
EOOOH-E7FEH
Systems
~i
tor
EPIOt
1?oWer-on~set
Junp
Auto
bOot on power
on/reset,
jl.mpS
to
rneIID1:Y
location
Options
EOOOS.
Shipped
enabled.
SPOCIFlCATICNS-CPU
Processor
Z-SOA
Nunber
of
Data
Bits
S
N\:mt)er
of
Mdress
Bits
16
Instructions
Clock
speed
Interrupts
I/O
devices
Dynamic
RAM
Rev.
I-B
6/11/80
15S,
including
all
78 S080
instructions
2
or
4
MHz,
j~r
selectable,
enabled
for
4 MHz.
Z-SO
Mode
0
(SOSO
rro::1e),
MODE
1,
mDE
2
256
I/O
addresses
Supports
dynamic mem::>ty
by
sending
Z-80
RFSH
on
bus
line
66
~
fast
resetlJ;:ower
on
clear
signal
generated
on
board.
•
Static
RAM
MWRITE
wai
t
state
generation
for
memories
slower
than
300
ns.
Bus
!Dad
Bufferin;
Phantan:
Mirrorin;
.
capacity
vector
ZCB
Single
Board
catpJter
Fully
canpatible
Jumper
option
to
generate
MWRITE
on
board
Standard:
option
enabled.
3
options:
generate
one
wait
state
on
each
bus
cycle,
generate
one
wait
state
after
each
Ml
instruction,
generate
no
wait
states.
Standard:
generate
one
wait
state
after
each
Ml
instruction.
1
stamard
T1'L
load
.on
all
inputs
Fan
out:
15
standard
(60 low power
shottky)
OUtput
buffer
disable
canpatible
with
Vector
Graphic
~
Boards,
which
generate
phantan
in
response
to
Power-on-clear
(PCX:).
Jumper
selectable:
on/off.
Standard:
enabled
Standard:
enabled,
can be
disabled.
SPECIFlCATICt&-I/O .
,,.--.;)
1
serial
RS-232
and
3
8-bitparallel
ports
programnablt:.
as
input
or
output.
Serial
port
1,
using
8251
controller
chip.
Port
addresses
Any
increnent
of
four
fran
OOH
to
FFH.
Preset
addresses
are:
Data,
04H
(echoed
on
06H)
1
Control,
05H
(echoed
on
07H.)
Signal
levels
EIA RS-232C
RS-232
handshakin;
Typical
handshakin;
is
provided,
ie.
RI'S, ers, OrR,
DSR,
etc.
Asynchronous
Rates
Data
bits
Step
bits
parity
Uo-9600
baw
(switch
selectable)
5 -
8,
programnable
1,
1
1/2,
or
2,
programnable
Even,
ood,
or
oone, programmable
Rev.
l-B
6/11/80
,.
~
-~
vector
ZCB
Single
Board
COtplter
Synchronous
Rates
Synch
detect
Clock
Parity
Data
bits
Sync
character
Parallel
Ports
Port
Addresses
latching
Signal
level
N\..mi:)er
of
lines
rata
transfer
cable
Rev.
1-8
6/11/80
OC-56K.
can
be
wired
for
internal
or
external
synch.
8251
SYNDET
line
is
not
connected.
N:lt
now
connected
to
the
external
\4\Orld
as
required
for
synchrcnous
operatioo.
Even,
odd,
or
none,
progranmable
5 -
8,
programmable
Single
or
double
synch
character
can
be
progtaliiled.
2-8
bit,
2-4
bit
can
be
programned as
3-8
bit.
Uses
an 8255
parallel
I/O
controller
chip.
Any
increment
of
four
fran
OOH
to
FFH.
Preset
addresses
are:
:Ebrt
A, 08H;
Port
B,
098;
:Ebrt
C,
OAH
and
the
Cootrol
Status
Register
at
000.
output
latched,
input
not
latched.
Tl'L
(i.nt:ut = 1 low power
Tl'L
load;
output
drives
1 'l"l'L
load)
•
8
lines
per
channel,
progranmable
for
input
or
output.
+5
VOC
and
GND
are
also
provided.
OVer
lOOK
bytes/second.
Cptional.
Has
34-pin
female
connector
and
34-line
ribbon
cable.
N:l
connector
is
at
the
other
end,
allowin3
user
to
configure
as
required.
r-tlst
be
ordered
separately.