Advantech SOM-5992 Guide

０
SOM-5992 COMe TYPE7
R1210 2018’09’25

０
Contents
1 Introduction .............................................................................................. ７
1.1 About This Document ........................................................................... ７
1.2 Acronyms / Definitions .......................................................................... ７
1.3 Reference Documents .......................................................................... １１
1.4 Revision History .................................................................................... １１
1.5 SOM-5992 Block Diagram .................................................................... １２
1.6 Module Pin-out Types 7 - Required and Optional Features ................. １３
2 COM Express Type 7 Interfaces.............................................................. １５
2.1 COM Express Type 7 Connector Layout .............................................. １５
2.2 COM Express Type 7 Connector Pin-out.............................................. １６
2.3 General Purpose PCI Express Lanes................................................... ２４
2.3.1 General Purpose PCIe Signal Definitions ........................................................ ２４
2.3.2 PCI Express Lane Configurations –SOM-5992 Type 7 Limitations ................ ３４
2.3.3 PCI Express General Routing Guidelines........................................................ ３６
2.3.3.1 PCI Express Insertion Loss Budget with Slot Card............................... ３６
2.3.3.2 PCI Express Insertion Loss Budget with Carrier Board PCIE Device... ３８
2.3.4 PCI Express Trace Length Guidelines............................................................. ４０
2.4 NC-SI .................................................................................................... ４２
2.4.1 NC-SI Signal Definitions .................................................................................. ４２
2.4.2 NC-SI General Routing Guidelines .................................................................. ４３
2.4.3 NC-SI Trace Length Guidelines ....................................................................... ４３
2.5 10GB Ethernet ...................................................................................... ４４
2.5.1 10GB LAN Signal Definitions ........................................................................... ４５
2.5.2 Example 10 GB Ethernet Designs ................................................................... ５３
2.5.2.1 2016 Silicon 10GbE Fiber Implementation ........................................... ５３
2.5.2.2 2016 Silicon 10GbE Copper Implementation........................................ ５４
2.5.2.3 Future Silicon 10GbE Fiber Implementation......................................... ５５
2.5.2.4 Future Silicon 10GbE Copper Implementation ..................................... ５６
2.5.3 AC Coupling of 10G_KR_TX Signals ............................................................... ５７
2.5.4 10GB LAN Routing Guidelines ........................................................................ ５８
2.5.4.1 10GB LAN KR Guidelines .................................................................... ５９
2.5.4.2 10GB LAN Sideban Guidelines ............................................................ ６０
2.6 Gb Ethernet........................................................................................... ６１
2.6.1 Gb Ethernet Signal Definitions......................................................................... ６１

１
2.6.2 SDP Pins.......................................................................................................... ６３
2.6.3 Gb Ethernet Routing Guidelines ...................................................................... ６４
2.6.4 Gb Ethernet Trace Length Guidelines ............................................................. ６５
2.6.5 Reference Ground Isolation and Coupling....................................................... ６６
2.7 USB2.0 Ports ........................................................................................ ６７
2.7.1 USB2.0 Signal Definitions................................................................................ ６７
2.7.1.1 USB Over-Current Protection (USB_x_y_OC#) .................................... ６９
2.7.1.2 Powering USB devices during S5......................................................... ６９
2.7.2 USB2.0 Routing Guidelines ............................................................................. ７０
2.7.2.1 USB 2.0 General Design Considerations and Optimization ................. ７１
2.7.2.2 USB 2.0 Port Power Delivery ............................................................... ７１
2.7.2.3 USB 2.0 Common Mode Chokes ......................................................... ７２
2.7.2.4 EMI / ESD Protection............................................................................ ７３
2.7.3 USB2.0 Trace Length Guidelines .................................................................... ７４
2.8 USB3.0.................................................................................................. ７５
2.8.1 USB3.0 Signal Definitions................................................................................ ７５
2.8.1.1 USB Over-Current Protection (USB_x_y_OC#).................................... ７８
2.8.1.2 EMI / ESD Protection............................................................................ ７８
2.8.2 USB3.0 Routing Guidelines ............................................................................. ７９
2.8.3 USB3.0 Trace Length Guidelines .................................................................... ８０
2.9 SATA..................................................................................................... ８１
2.9.1 SATA Signal Definitions................................................................................... ８１
2.9.2 SATA Routing Guidelines ................................................................................ ８２
2.9.2.1 General SATA Routing Guidelines ....................................................... ８３
2.9.3 SATA Trace Length Guidelines ....................................................................... ８５
2.10 LPC and eSPI Interface *SOM-5992 is not support eSPI................... ８６
2.10.1 LPC /eSPI Signal Definition ........................................................................... ８６
2.10.2 LPC Routing Guidelines................................................................................. ８９
2.10.2.1 General Signals .................................................................................. ８９
2.10.2.2 Bus Clock Routing .............................................................................. ８９
2.10.2.3 Carrier Board LPC Devices ................................................................ ８９
2.10.2.4 eSPI Devices ...................................................................................... ９０
2.10.3 LPC Trace Length Guidelines........................................................................ ９１
2.11 SPI –Serial Peripheral Interface Bus.................................................. ９２
2.11.1 SPI Signal Definition ...................................................................................... ９２
2.11.2 BIOS Boot Selection ...................................................................................... ９５
2.11.3 SPI Routing Guidelines.................................................................................. ９９

２
2.11.4 SPI Trace Length Guidelines ......................................................................... ９９
2.12 General Purpose I2C Bus Interface.................................................... １００
2.12.1 Signal Definitions ........................................................................................... １００
2.12.2 I2C Routing Guidelines .................................................................................. １０１
2.12.3 I2C Trace Length Guidelines ......................................................................... １０２
2.12.4 Connectivity Considerations .......................................................................... １０２
2.13 System Management Bus (SMBus).................................................... １０３
2.13.1 SMB Signal Definitions .................................................................................. １０４
2.13.2 SMB Routing Guidelines................................................................................ １０５
2.13.3 SMB Trace Length Guidelines ....................................................................... １０５
2.14. General Purpose Serial Interface....................................................... １０６
2.14.1 Serial interface Signal Definitions .................................................................. １０６
2.14.2 Serial interface Routing Guidelines................................................................ １０７
2.14.3 Serial interface Trace Length Guidelines....................................................... １０７
2.15 CAN Interface *SOM-5992 is not support CAN Interface. .................. １０８
2.15.1 CAN interface Signal Definitions.................................................................... １０８
2.15.2 CAN interface Routing Guidelines ................................................................. １０９
2.15.3 CAN interface Trace Length Guidelines ........................................................ １０９
2.16 Miscellaneous Signals ........................................................................ １１０
2.16.1 Miscellaneous Signals ................................................................................... １１０
2.16.2 Power Management Signals .......................................................................... １１４
2.16.3 Rapid Shutdown * SOM-5992 is not support............................................... １１７
2.16.4 Thermal Interface........................................................................................... １１８
2.16.5 Miscellaneous Signals Routing Guidelines .................................................... １１８
2.16.6 SDIO Signals Trace Length Guidelines ......................................................... １１９
2.17 Reserved Pins..................................................................................... １２０
2.17.1. Reserved Pins Definitions ............................................................................... １２０
3. Power......................................................................................................... １２１
3.1. General Power requirements.................................................................. １２１
3.2. ATX and AT Power Sequencing Diagrams ............................................ １２１
3.3. Design Considerations for Carrier Boards containing FPGAs/CPLDs ... １２５
4. Electrical Characteristics ........................................................................... １２６
4.1. Absolute Maximum Ratings.................................................................... １２６
4.2. DC Characteristics.................................................................................. １２６
4.3. Inrush Current......................................................................................... １２７

３
List of Tables
Table 1: Acronyms / Definitions Signal Table Terminology Descriptions.................................７
Table 2: Module Pin-out - Required and Optional Features ..................................................１３
Table 3: COM Express Type 7 Pin-out......................................................................................１６
Table 4: General Purpose PCI Express Signal Descriptions.................................................２４
Table 5: SOM-5992 PCI Express Lane Configurations ..........................................................３４
Table 6: PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board Slot Card......３７
Table 7: PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board Slot Card........３８
Table 8: PCI Express Insertion Loss Budget, 1.25 GHz with Carrier Board PCIe Device ３９
Table 9: PCI Express Insertion Loss Budget, 2.5 GHz with Carrier Board PCIe Device..３９
Table 10: PCI Express* Slot Card / Device Down Trace Length Guidelines.......................４１
Table 11: NC-SI Signal Description............................................................................................４２
Table 12: NC-SI Trace Length Guidelines ................................................................................４３
Table 13: 10GB LAN Signal Description ...................................................................................４５
Table 14: I2C Data Mapping to Carrier Board based PCA9539 I/O expander....................５２
Table 15: 10/100/1000 Ethernet Insertion Loss Budget, 100 MHz .......................................５８
Table 16: 10GB LAN KR Trace Length Guidelines .................................................................５９
Table 17: 10GB LAN Sideban Trace Length Guidelines ........................................................６０
Table 18: Gb Ethernet Interface Signal Descriptions ..............................................................６１
Table 19: 10/100/1000 Ethernet Insertion Loss Budget, 100 MHz .......................................６４
Table 20: Ethernet Trace Length Guidelines ............................................................................６５
Table 21: USB Signal Descriptions ............................................................................................６７
Table 22 :USB Insertion Loss Budget, 400 MHz......................................................................７０
Table 23: USB2.0 Trace Length Guidelines .............................................................................７４
Table 24: USB3.0 Signal Definitions ..........................................................................................７５
Table 25: USB3.0 Insertion Loss Budget ..................................................................................７９
Table 26: USB3.0 Trace Length Guidelines .............................................................................８０
Table 27: SATA Signal Definitions..............................................................................................８１
Table 28: SATA Insertion Loss Budge.......................................................................................８３
Table 29: SATA Trace Length Guidelines.................................................................................８５
Table 30: LPC/eSPI Interface Signal Definition........................................................................８６
Table 31: LPC Trace Length Guidelines ...................................................................................９１
Table 32: SPI Interface Signal Definition...................................................................................９２

４
Table 33: BIOS Selection Straps ................................................................................................９７
Table 34: SPI Trace Length Guidelines.....................................................................................９９
Table 35: General Purpose I2C Interface Signal Descriptions ..........................................１０１
Table 36: I2C Trace Length Guidelines.................................................................................１０２
Table 37: SMB Signal Definitions ...........................................................................................１０４
Table 38: SMB Trace Length Guidelines...............................................................................１０５
Table 39: Serial interface Signal Definitions .........................................................................１０６
Table 40: Serial interface Trace Length Guidelines ............................................................１０７
Table 41: CAN interface Signal Definitions...........................................................................１０８
Table 42: CAN interface Trace Length Guidelines ..............................................................１０９
Table 43: Miscellaneous Signal Definitions...........................................................................１１０
Table 44: Signal Definition SDIO ............................................................................................１１３
Table 45: Power Management Signal Definitions ................................................................１１４
Table 46: Thermal Management Signal Definitions.............................................................１１７
Table 47: Thermal Management Signal Definitions.............................................................１１８
Table 48: SDIO Trace Length Guidelines .............................................................................１１９
Table 49: RSVD Definitions.....................................................................................................１２０
Table 50: Power Management Timings.................................................................................１２３
Table 51: Absolute Maximum Ratings ...................................................................................１２６
Table 52: DC Current Characteristics1..................................................................................１２６
Table 53: DC Current Characteristics2..................................................................................１２６
Table 54 : Inrush Current .........................................................................................................１２７

５
List of Figures
Figure 1: SOM-5992 Block Diagram ..............................................................................................１２
Figure 2: COM Express Type7 Connector Layout...................................................................１５
Figure 3: PCI Express Insertion Loss Budget with Slot Card ................................................３６
Figure 4: PCI Express Insertion Loss Budget with Carrier Board PCIe Device..................３８
Figure 5: Topology for PCI Express Slot Card.........................................................................４０
Figure 6: Topology for PCI Express Device Down..................................................................４０
Figure 7: Topology for NC-SI......................................................................................................４３
Figure 8: 10G Ethernet Design for Fiber PHY with Broadwell DE ........................................５３
Figure 9: 10G Ethernet Design for Copper PHY with Broadwell DE ....................................５４
Figure 10: 10G Ethernet Design for Fiber PHY with Future SoC ..........................................５５
Figure 11: 10G Ethernet Design for Copper PHY with Future SoC ......................................５６
Figure 12: 10G Ethernet AC coupling –backplane system....................................................５７
Figure 13: 10G Ethernet AC coupling –direct cable ...............................................................５７
Figure 14: 10G Ethernet AC coupling –PHY on Carrier.........................................................５７
Figure 15: 10GBASE-KR Trace Length Budget.......................................................................５８
Figure 16: 10/100/1000 Ethernet Insertion Loss Budget ........................................................６４
Figure 17: Topology for Ethernet Jack.......................................................................................６５
Figure 18: USB 2.0 Insertion Loss Budget................................................................................７０
Figure 19: USB 2.0 Good Downstream Power Connection ...................................................７２
Figure 20: USB 2.0 A Common Mode Choke...........................................................................７２
Figure 21: Topology for USB2.0 .................................................................................................７４
Figure 22: USB3.0 Insertion Loss Budget.................................................................................７９
Figure 23: Topology for USB3.0 .................................................................................................８０
Figure 24: SATA Insertion Loss Budge .....................................................................................８２
Figure 25: Topology for SATA.....................................................................................................８５
Figure 26: Typical routing topology for a Module LPC device ...............................................８９
Figure 27: Topology for LPC .......................................................................................................９１
Figure 28: BIOS Selection LPC Mode .......................................................................................９６
Figure 29: BIOS Selection eSPI Mode ......................................................................................９６
Figure 30: Topology for SPI.........................................................................................................９９
Figure 31: Topology for I2C.....................................................................................................１０２
Figure 32: Topology for SMB ..................................................................................................１０５

６
Figure 33: Topology for Serial interface ................................................................................１０７
Figure 34: Topology for CAN interface ..................................................................................１０９
Figure 35: Topology for SDIO .................................................................................................１１９
Figure 36: ATX Style Power Up Boot –Controlled by Power Button................................１２２
Figure 37: AT Style Power Up Boot .......................................................................................１２３

７
1 Introduction
1.1 About This Document
This design guide provides information for designing a custom system Carrier Board for COM Express
Type 7 Module. It includes Signal Descriptions, Routing Guidelines and Trace Length Guidelines. The
main purpose is designing Carrier Board for helping customers fast and easy using the module of
Advantech to be designed.
1.2 Acronyms / Definitions
Table 1: Acronyms / Definitions Signal Table Terminology Descriptions
Term
Description
I/O 3.3V
Bi-directional signal 3.3V tolerant
I/O 5V
Bi-directional signal 5V tolerant
I 3.3V
Input 3.3V tolerant
I 5V
Input 5V tolerant
I/O 3V3_SBY
Bi-directional 3.3V tolerant active during Suspend and running state.
O 3.3V
Output 3.3V signal level
O 5V
Output 5V signal level
OD
Open drain output
P
Power input/output
S0, S1, S2, S3, S4,
S5
System states describing the power and activity level
S0 Full power, all devices powered
S1
S2
S3 Suspend to RAM System context stored in RAM; RAM is in standby
S4 Suspend to Disk System context stored on disk
S5 Soft Off Main power rail off, only standby power rail present
10GBase-KR
10 Gbit internal copper interface. Operates over a single lane and uses the
same physical layer coding (defined in IEEE 802.3 Clause 49) as
10GBASE-LR (Single Mode Fiber 1310 nm ) /ER (Single Mode Fiber 1550
nm) /SR (Multi Mode Fiber 850 nm)
10GBase-KX4
4x 10 Gbit internal copper interface. Operates over four lanes and uses the
same physical layer coding (defined in IEEE 802.3 Clause 48) as
10GBASE-CX4
ACPI
Advanced Configuration Power Interface –standard to implement power
saving modes in PC-AT systems

８
Term
Description
Basic Module
COM Express 125mm x 95mm Module form factor.
BIOS
Basic Input Output System –firmware in PC-AT system that is used to
initialize system components before
handing control over to the operating system.
BMC
Baseboard Management Controller
CAN
Controller-area network (CAN or CAN-bus) is a vehicle bus standard
designed to allow microcontrollers to
communicate with each other within a vehicle without a host computer.
Carrier Board
An application specific circuit board that accepts a COM Express Module.
Compact Module
COM Express 95x95 Module form factor
DIMM
Dual In-line Memory Module
DRAM
Dynamic Random Access Memory
EAPI
Embedded Application Programming Interface
Software interface for COM Express specific industrial functions
•System information
•Watchdog timer
•I2C Bus
•Flat Panel brightness control
•User storage area
•GPIO
EEPROM
Electrically Erasable Programmable Read-Only Memory
eSPI
Enhanced Serial Peripheral Interface
Extended Module
COM Express 155mm x 110mm Module form factor.
FR4
A type of fiber-glass laminate commonly used for printed circuit boards.
Gb
Gigabit
GBE
Gigabit Ethernet
GPI
General Purpose Input
GPIO
General Purpose Input Output
GPO
General Purpose Output
I2C
Inter Integrated Circuit –2 wire (clock and data) signaling scheme allowing
communication between integrated circuits, primarily used to read and load
register values.
LAN
Local Area Network
Legacy Device
Relics from the PC-AT computer that are not in use in contemporary PC
systems: primarily the ISA bus, UART-based serial ports, parallel printer
ports, PS-2 keyboards, and mice. Definitions vary as to what constitutes a
legacy device. Some definitions include IDE as a legacy device.

９
Term
Description
LPC
Low Pin-Count Interface: a low speed interface used for peripheral circuits
such as Super I/O controllers, which typically combine legacy-device
support into a single IC.
LS
Least Significant
MDIO
Management Data Input/Output, or MDIO, is a 2-wire serial bus that is used
to manage PHYs or physical layer devices in media access controllers
(MACs).
ME
Management Engine
Mini Module
COM Express 84x55mm Module form factor
MS
Most Significant
NA
Not Available
NC
No Connect
NC-SI
Network Controller Sideband Interface
OEM
Original Equipment Manufacturer
PC-AT
“Personal Computer –Advanced Technology”–an IBM trademark term
used to refer to Intel x86 based personal computers in the 1990s
PCB
Printed Circuit Board
PCI Express
PCIE
Peripheral Component Interface Express –next-generation high speed
Serialized I/O bus
PEG
PCI Express Graphics
PHY
Ethernet controller physical layer device
Pin-out Type
A reference to one of seven COM Express definitions for the signals that
appear on the COM Express Module connector pins.
Ra
Roughness Average –a measure of surface roughness, expressed in units
of length.
ROM
Read Only Memory –a legacy term –often the device referred to as a
ROM can actually be written to, in a special mode. Such writable ROMs are
sometimes called Flash ROMs. BIOS is stored in ROM or Flash ROM.
RTC
Real Time Clock –battery backed circuit in PC-AT systems that keeps
system time and date as well as certain system setup parameters
SAFS
eSPI tTerm for Slave Attached Flash Sharing where the Flash component is
attached behind a BMC component.
SATA
Serial AT Attachment: serial-interface standard for hard disks
SCSI
Small Computer System Interface –an interface standard for high end disk
drives and other computer peripherals

１０
Terminology
Description
SDP
Software-Definable Pin
SGMII
Serial Gigabit Media Independent Interface
SM Bus
System Management Bus
SO-DIMM
Small Outline Dual In-line Memory Module
SPD
Serial Presence Detect –refers to serial EEPROM on DRAMs that has
DRAM Module configuration information
SPI
Serial Peripheral Interface
Super I/O
An integrated circuit, typically interfaced via the LPC bus that provides
legacy PC I/O functions including PS2 keyboard and mouse ports, serial and
parallel port(s) and a floppy interface.
TPM
Trusted Platform Module, chip to enhance the security features of a
computer system.
USB
Universal Serial Bus
WDT
Watch Dog Timer.
XAUI
10 Gigabit / sec Attachment Unit Interface.
XGMII
10 Gigabit Media Independent Interface

１１
1.3 Reference Documents
Document
PICMGR COM.0 Revision 3.0 COM Express Base Specification, 2017’03’31 Final
Intel EDS Document
Intel Layout Guide Document
ATX12V Power Supply Design Guide Rev. 2.01
1.4 Revision History
Revision
Date
PCB Rev.
Changes
0.10
2017’02’14
A101-1
1.00
2017’10’02
A101-2
1. Change NC-SI interface connection from 10G to GbE0
& add GbE0 SDP Pin connection to B2B Conn.
2. Remove 10GB NC-SI connection to B2B Conn.
1.10
2018’03’02
A101-2
1. Modify AC coupling cap of the PCIe BUS.
1.20
09 25, 2018
A101-2
1. Modify LPC Clock output to 24MHz.

１２
1.5 SOM-5992 Block Diagram
Figure 1: SOM-5992 Block Diagram
LAN Sideband
Voltage
Translator
1 xPCIEx16 Gen3
2 x10GBASE-KR
COM-Express R3.0 Type 7
VR12.5
+VCORE
4 xUSB2.0
PCIEx8 Gen3
2 xSATA Gen3
SMBus
SPI BIOS SPI Bus
4 xUSB3.0 6 xPCIEx1 Gen2
PCIE[6:1]
PE2[7:0]PE1[15:0]
USB3[6:5]
USB3[2:1]
USB2[3:0]
SATA[1:0]
Socket Type :
BGA, 37.5 x 37.5, P1272,
0.7mm pitch, Pins - 1667
Processor Type :
Microserver Intel Xeon
D-1500 Series
( SoC )
BDW-DE
MaxLast Level Cache per
Cbo :1.5 MB
Number of cores :
8 or 16 based on SKU
PCIE[7]
1 xPCIEx1 Gen2 1 xPCIEx1 Gen2
PCIE[8]
1 xPCIEx1 Gen2
Option
PCIE[8]
DDR4 -1600, -1867,
-2133, -2400 MT/s
DDR4 SO-DIMM 2DPC
SO-DIMM x 4 (ECC)
MaxCapacity 64GB
Connector Row C,D
Intel
I210-AT
MDI
LINK#
Connector Row A,B
LAN NC-SI
TPM2.0
SLB9665
iManager WDT / GPIO / I2C
LAN Sideband
LPC BUS
RS1 / RS2 / FAN
LAN SPI Flash Bus
LAN SPI
Flash NVM

１３
1.6 Module Pin-out Types 7 - Required and Optional Features
COM Express Required and Optional features are summarized in the following table. The features
identified as Minimum (Min.) shall be implemented by all Modules. Features identified up to Maximum
(Max) may be additionally implemented by a Module.
Table 2: Module Pin-out - Required and Optional Features
Feature
Type 7 Min / Max
SOM-5992
System I/O
PCI Express Lanes 0 - 5
6 / 6
6
PCI Express Lanes 6 - 15
0 / 10
10
PCI Express Lanes 16 - 31
0 / 16
16
10G LAN Ports 0 - 3
0 / 4
2
NC-SI
0 / 1
1
1Gb LAN Port 0
1 / 1
1
Serial Ports 1 - 2
0 / 2
2
CAN interface on SER1
0 / 1
0
SATA Ports
0 / 2
2
USB 2.0 Ports
4 / 4
4
USB0 Client
0 / 1
0
USB 3.0 Ports
0 / 4
4
LPC Bus or eSPI
1 / 1
1
SPI (Devices)
1 / 2
2
Rapid Shutdown
0 / 1
0
System Management
SDIO (muxed on GPIO)
0 / 1
0
General Purpose I/O
8 / 8
8
SMBus
1 / 1
1
I2C
1 / 1
1
Watchdog Timer
0 / 1
1
Speaker Out
1 / 1
1
Carrier Board BIOS Flash Support
0 / 1
1
Reset Functions
1 / 1
1
Trusted Platform Module
0 / 1
1
Power Management
Thermal Protection
0 / 1
1
Battery Low Alarm
0 / 1
1
Suspend/Wake Signals
0 / 3
2
Power Button Support
1 / 1
1

１４
Feature
Type 7 Min / Max
SOM-5992
Power Good
1 / 1
1
VCC_5V_SBY Contacts
4 / 4
4
Sleep Input
0 / 1
1
Lid Input
0 / 1
1
Carrier Board Fan Control
0 / 1
1
Power
VCC_12V Contacts
24 / 24
24

１５
2 COM Express Type 7 Interfaces
2.1 COM Express Type 7 Connector Layout
Figure 2: COM Express Type7 Connector Layout
NA

１６
2.2 COM Express Type 7 Connector Pin-out
Table 3: COM Express Type 7 Pin-out
Connector Rows A and B
Pin#
Type 7 Description
SOM-5992
Difference
Pin#
Type 7 Description
SOM-5992
Difference
A1
GND(FIXED)
B1
GND(FIXED)
A2
GBE0_MDI3-
B2
GBE0_ACT#
A3
GBE0_MDI3+
B3
LPC_FRAME#/ESPI_CS0#
LPC_FRAME#
A4
GBE0_LINK100#
B4
LPC_AD0/ESPI_CS0
LPC_AD0
A5
GBE0_LINK1000#
B5
LPC_AD1/ESPI_CS1
LPC_AD1
A6
GBE0_MDI2-
B6
LPC_AD2/ESPI_CS2
LPC_AD2
A7
GBE0_MDI2+
B7
LPC_AD3/ESPI_CS3
LPC_AD3
A8
GBE0_LINK#
B8
LPC_DRQ0#/ESPI_ALERT0#
LPC_DRQ0#
A9
GBE0_MDI1-
B9
LPC_DRQ1#/ESPI_ALERT1#
LPC_DRQ1#
A10
GBE0_MDI1+
B10
LPC_CLK/ESPI_CK
LPC_CLK
A11
GND(FIXED)
B11
GND(FIXED)
A12
GBE0_MDI0-
B12
PWRBTN#
A13
GBE0_MDI0+
B13
SMB_CK
A14
GBE0_CTREF
NC
B14
SMB_DAT
A15
SUS_S3#
B15
SMB_ALERT#
A16
SATA0_TX+
B16
SATA1_TX+
A17
SATA0_TX
B17
SATA1_TX
A18
SUS_S4#
B18
SUS_STAT#/ESPI_RESET#
SUS_STAT#
A19
SATA0_RX+
B19
SATA1_RX+
A20
SATA0_RX
B20
SATA1_RX-
A21
GND(FIXED)
B21
GND(FIXED)
A22
PCIE_TX15+
B22
PCIE_RX15+
A23
PCIE_TX15-
B23
PCIE_RX15-
A24
SUS_S5#
SUS_S4#
B24
PWR_OK
A25
PCIE_TX14+
B25
PCIE_RX14+
A26
PCIE_TX14-
B26
PCIE_RX14-
A27
BATLOW#
B27
WDT
A28
(S)ATA_ACT#
B28
RSVD
A29
RSVD
B29
RSVD
A30
RSVD
B30
RSVD
A31
GND(FIXED)
B31
GND(FIXED)
A32
RSVD
B32
SPKR

１７
Connector Rows A and B
Pin#
Type 7 Description
SOM-5992
Difference
Pin#
Type 7 Description
SOM-5992
Difference
A33
RSVD
B33
I2C_CK
A34
BIOS_DIS0#/ESPI_SAFS
BIOS_DIS0#
B34
I2C_DAT
A35
THRMTRIP#
B35
THRM#
A36
PCIE_TX13+
B36
PCIE_RX13+
A37
PCIE_TX13-
B37
PCIE_RX13-
A38
GND
B38
GND
A39
PCIE_TX12+
B39
PCIE_RX12+
A40
PCIE_TX12-
B40
PCIE_RX12-
A41
GND(FIXED)
B41
GND(FIXED)
A42
USB2-
B42
USB3-
A43
USB2+
B43
USB3+
A44
USB_2_3_OC#
B44
USB_0_1_OC#
A45
USB0-
B45
USB1-
A46
USB0+
B46
USB1+
A47
VCC_RTC
B47
ESPI_EN#
NC
A48
RSVD
B48
USB0_HOST_PRSNT
NC
A49
GBE0_SDP
B49
SYS_RESET#
A50
LPC_SERIRQ/ESPI_CS1#
LPC_SERIRQ
B50
CB_RESET#
A51
GND(FIXED)
B51
GND(FIXED)
A52
PCIE_TX5+
B52
PCIE_RX5+
A53
PCIE_TX5-
B53
PCIE_RX5-
A54
GPI0
B54
GPO1
A55
PCIE_TX4+
B55
PCIE_RX4+
A56
PCIE_TX4-
B56
PCIE_RX4-
A57
GND
B57
GPO2
A58
PCIE_TX3+
B58
PCIE_RX3+
A59
PCIE_TX3-
B59
PCIE_RX3-
A60
GND(FIXED)
B60
GND(FIXED)
A61
PCIE_TX2+
B61
PCIE_RX2+
A62
PCIE_TX2-
B62
PCIE_RX2-
A63
GPI1
B63
GPO3
A64
PCIE_TX1+
B64
PCIE_RX1+
A65
PCIE_TX1-
B65
PCIE_RX1-
A66
GND
B66
WAKE0#
A67
GPI2
B67
WAKE1#

１８
Connector Rows A and B
Pin#
Type 7 Description
SOM-5992
Difference
Pin#
Type 7 Description
SOM-5992
Difference
A68
PCIE_TX0+
B68
PCIE_RX0+
A69
PCIE_TX0-
B69
PCIE_RX0-
A70
GND(FIXED)
B70
GND(FIXED)
A71
PCIE_TX8+
B71
PCIE_RX8+
A72
PCIE_TX8-
B72
PCIE_RX8-
A73
GND
B73
GND
A74
PCIE_TX9+
B74
PCIE_RX9+
A75
PCIE_TX9-
B75
PCIE_RX9-
A76
GND
B76
GND
A77
PCIE_TX10+
B77
PCIE_RX10+
A78
PCIE_TX10-
B78
PCIE_RX10-
A79
GND
B79
GND
A80
GND(FIXED)
B80
GND(FIXED)
A81
PCIE_TX11+
B81
PCIE_RX11+
A82
PCIE_TX11-
B82
PCIE_RX11-
A83
GND
B83
GND
A84
NCSI_TX_EN
B84
VCC_5V_SBY
A85
GPI3
B85
VCC_5V_SBY
A86
RSVD
B86
VCC_5V_SBY
A87
RSVD
B87
VCC_5V_SBY
A88
PCIE_CLK_REF+
B88
BIOS_DIS1#
A89
PCIE_CLK_REF-
B89
NCSI_RX_ER
A90
GND(FIXED)
B90
GND(FIXED)
A91
SPI_POWER
B91
NCSI_CLK_IN
A92
SPI_MISO
B92
NCSI_RXD1
A93
GPO0
B93
NCSI_RXD0
A94
SPI_CLK
B94
NCSI_CRS_DV
A95
SPI_MOSI
B95
NCSI_TXD1
A96
TPM_PP
B96
NCSI_TXD0
A97
TYPE10#
NC
B97
SPI_CS#
A98
SER0_TX
B98
NCSI_ARB_IN
A99
SER0_RX
B99
NCSI_ARB_OUT
A100
GND(FIXED)
B100
GND(FIXED)
A101
SER1_TX/CAN_TX
SER1_TX
B101
FAN_PWMOUT
A102
SER1_RX/CAN_RX
SER1_RX
B102
FAN_TACHIN